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ISL8501IRZ-T

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ISL8501IRZ-T

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Part Number ISL8501IRZ-T
Manufacturer Intersil
Description IC REG TRPL BUCK/LINEAR 24QFN
Datasheet ISL8501IRZ-T Datasheet
Package 24-VFQFN Exposed Pad
In Stock 15,940 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Oct 23 - Oct 28 (Choose Expedited Shipping)
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Part Number # ISL8501IRZ-T (PMIC - Voltage Regulators - Linear + Switching) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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ISL8501IRZ-T Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Linear + Switching
Datasheet ISL8501IRZ-TDatasheet
Package24-VFQFN Exposed Pad
Series-
TopologyStep-Down (Buck) (1), Linear (LDO) (2)
FunctionAny Function
Number of Outputs3
Frequency - Switching500kHz
Voltage/Current - Output 1Controller
Voltage/Current - Output 20.6 V ~ 4.2 V, 500mA
Voltage/Current - Output 30.6 V ~ 4.2 V, 500mA
w/LED DriverNo
w/SupervisorNo
w/SequencerNo
Voltage - Supply6 V ~ 25 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case24-VFQFN Exposed Pad
Supplier Device Package24-QFN (4x4)

ISL8501IRZ-T Datasheet

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FN6500 Rev 1.00 July 12, 2007 ISL8501 Triple Output Controller with 1A Standard Buck PWM and Dual LDOs DATASHEETOBSOLETE PRODUCTNO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tscThe ISL8501 is a high-performance, triple output controller that provides a single, high frequency power solution for a variety of point of load applications. The ISL8501 integrates a 1A standard buck PWM controller and switching MOSFET with two 500mA LDOs. The PWM controller in the ISL8501 drives an internal switching N-Channel power MOSFET and requires an external Schottky diode to generate an output voltage from 0.6V to 20V. The integrated power switch is optimized for excellent thermal performance up to 1A of output current. The standard buck input voltage range supports a fixed 5V or variable 6V to 25V range. The PWM regulator switches at a fixed frequency of 500kHz and utilizes simple voltage mode control with input voltage feed forward to provide flexibility in component selection and minimize solution size. Protection features include overcurrent, undervoltage, and thermal overload protection integrated into the IC. The ISL8501 power good signal output indicates loss of regulation on the PWM output. The ISL8501 features two adjustable LDO regulators using internal PMOS transistors as pass devices. Separate enable pins (EN_LDO1, EN_LDO2) control each LDO output. A single power good signal output indicates loss of regulation on either of the two LDO outputs. Independent overcurrent and thermal fault shutdown monitors are integrated into the LDO section. ISL8501 is available in a small 4mmx4mm Quad Flat No- Lead (QFN) package. Features • Standard Buck Controller with Integrated Switching Power MOSFET and Dual LDOs • Integrated Boot Diode • Input Voltage Range - Fixed 5V ±10% - Variable 6V to 25V • PWM Output Voltage Adjustable from 0.6V to 20V with Continuous Output Current up to 1A • Voltage Mode Control with Voltage Feed Forward • Fixed 500kHz Switching Frequency • Externally Adjustable Soft-Start Time • Output Undervoltage Protection • Dual LDO Adjustable Options - LDO1, 0.6V to 4.2V . . . . . . . . . . . . . . . . . . . . . . 500mA - LDO2, 0.6V to 4.2V . . . . . . . . . . . . . . . . . . . . . . 500mA • Individual Enable Inputs • Two PGOOD Outputs (PWM and both LDOs) • Overcurrent Protection • Thermal Overload Protection • Internal 5V LDO regulator • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • General Purpose • WLAN Cards-PCMCIA, Cardbus32, MiniPCI Cards- Compact Flash Cards • Hand-Held Instruments Pinout ISL8501 (24 LD QFN) TOP VIEW Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL8501IRZ* 85 01IRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D *Add “-T” suffix for tape and reel NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. C C 1 P G _P W M F B _P W M C O M P S S E N C C 2 P G _L D O E N _L D O 2 E N _L D O 1 G N D V C C FB_LDO1 VOUT1 VIN_LDO2 VIN_LDO1 VOUT2 FB_LDO2 VIN VIN PHASE PHASE BOOT PVCC 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 GND 25FN6500 Rev 1.00 Page 1 of 19 July 12, 2007

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ISL8501Typical Application Schematics FIGURE 1. VIN RANGE FROM 4.5V TO 5.5V 5V ISL8501 VIN C8 LDO2 1.8V R7 R8 L D O 1 E N A B L E FB_LDO2 L D O 2 E N A B L E L D O P G O O D E N _L D O 2 P G _ L D O C12 C4 C C 2 C C 1 V C C G N D C2 R4 VOUT2 R5 C6 LDO1 1.2V C O M P F B _P W M E N _L D O 1 C14 PVCC C9 P W M P G O O D P G _ P W M C5 S S P W M E N A B L E E N R1 R3 R2 C1 C3 VOUT C7 VOUT1 VIN_LDO1 VIN_LDO2 VIN C11 L +3.3V PHASE BOOT VOUT1 C10 ~2.5V UNREGULATED 301 100pF 10k 10pF 10nF 20k 2.21k 0.033F0.1F R6 5.11k 5.11k 22F 10F 22F 5.11k 2.55k 0.1F 1F 0.1F D 10H B340LB 100F 10F FB_LDO1FN6500 Rev 1.00 Page 2 of 19 July 12, 2007

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ISL8501FIGURE 2. VIN RANGE FROM 6V TO 25V Typical Application Schematics (Continued) 5V ISL8501 VIN C8 LDO2 1.8V R7 R8 L D O 1 E N A B L E FB_LDO2 L D O 2 E N A B L E L D O P G O O D E N _L D O 2 P G _ L D O C12 C4 C C 2 C C 1 V C C G N D C2 R4 VOUT2 R5 C6 LDO1 1.2V C O M P F B _P W M E N _L D O 1 C14 PVCC C9 P W M P G O O D P G _ P W M C5 S S P W M E N A B L E E N R1 R3 R2 C1 C3 VOUT C7 VOUT1 VIN_LDO1 VIN_LDO2 C11 L PHASE BOOT VOUT1 C10 301 100pF 10k 10pF 10nF 20k 2.21k 0.033F 0.1F R6 5.11k 5.11k 22F 10F 22F 5.11k 2.55k 0.1F 1F 0.1F D 10H B340LB 100F 10uF FB_LDO1FN6500 Rev 1.00 Page 3 of 19 July 12, 2007

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ISL8501Functional Block Diagram + - LDO1 PHASE (x2) VIN (x2) RAMP GENERATOR OSCILLATOR LDO 0.6V OC EA PWM POR EN_LDO1 EN_LDO2 GND VIN_LDO1 VOUT1 CC1 Gm FB_LDO1 REFERENCE + - LDO2 VIN_LDO2 VOUT2 CC2 Gm FB_LDO2 PG_LDO PG_PWM P V C C GATE DRIVE B O O T OC MONITOR + - C O M P + - F B VIN PVCC CONTROL SOFT-START 30A EN MONITOR VOLTAGE VCC MONITOR FAULT MONITOR VCC POWER-ON RESET MONITOR VIN_LDO1 VIN_LDO2 -15% COMP. -15% COMP. THERMAL MONITOR +150oC REF CONTROL LDO2 LOGIC POR FAULT REF CONTROL LDO1 LOGIC POR FAULT SS VINFN6500 Rev 1.00 Page 4 of 19 July 12, 2007

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ISL8501Absolute Maximum Ratings (Note 1) Thermal Information VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +26V VIN_LDOx to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V PHASE to BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +0.3V VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V VOUT, LDO1, LDO2 to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V FB_PWM, FB_LDOx to GND. . . . . . . . . . . . . . . . . . . . . -0.3V to +6V PG_PWM, PG_LDOx to GND . . . . . . . . . . . . . . . . . . . . -0.3V to +6V EN, EN_LDOx to GND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V CC1, CC2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V VCC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Thermal Resistance JA (°C/W) JC (°C/W) QFN Package (Notes 1, 2). . . . . . . . . . 36 5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to +150°C Junction Temperature Range. . . . . . . . . . . . . . . . . . -55°C to +150°C Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C Operating Temperature Range . . . . . . . . . . . . . . . . . -40°C to +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. *An accidental short between VCC and GND may cause excessive heating and permanent damage to the device. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details. Electrical Specifications Unless Otherwise Noted, All Parameter Limits are Guaranteed Over the Recommended Operating Conditions and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 7), VIN = 6V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SUPPLY VOLTAGE VIN Voltage Range VIN 6 25 V VIN connected to VCC 4.5 5.0 5.5 V VIN_LDOx Voltage Range (Note 6) 1.8 4.6 V VIN Operating Supply Current IOP (Note 3) 2.5 3.5 mA VIN Shutdown Supply Current ISD EN = EN_LDOx = GND 70 100 A POWER-ON RESET VCC POR Threshold Rising Edge 4.25 4.40 4.50 V Hysteresis 260 mV VIN_LDOx POR Threshold Rising Edge 1.2 V Hysteresis 200 mV INTERNAL VCC LDO VCC Output Voltage Range VIN = 6V to 25V, IVCC = 0mA to 50mA 4.5 5.00 5.5 V REFERENCE Reference Voltage VFB VIN = 6V to 25V, IREF = 0 0.590 0.6 0.609 V STANDARD BUCK PWM REGULATOR FB_PWM Line Regulation IOUT = 0mA, VIN = 6V to 25V -0.5 0.5 % FB_PWM Leakage Current VFB = 0.6V 0 50 100 nA OSCILLATOR AND PWM MODULATOR Nominal Switching Frequency fSW TA = -40°C to +85°C, VCC = 5V 450 500 550 kHz Modulator Gain AMOD VIN = 12V (AMOD = 10/VIN) 0.73 0.86 0.99 V/V Peak-to-Peak Sawtooth Amplitude VRAMP VIN = 12V (VPP = VIN/10) 1.2 V PWM Ramp Offset Voltage VOFFSET 0.70 0.8 0.91 V Maximum Duty Cycle DCMAX COMP >4V 80 83 % ERROR AMPLIFIER Open-Loop Gain 88 dB Gain Bandwidth Product GBWP 15 MHz Slew Rate SR COMP = 10pF 5 V/sFN6500 Rev 1.00 Page 5 of 19 July 12, 2007

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ISL8501ENABLE SECTION EN Threshold Rising Edge 1.2 1.7 2.2 V Hysteresis 350 mV EN_LDOx Logic Input Threshold Rising Edge 1.2 1.7 2.2 V Hysteresis 400 mV EN_LDOx Logic Input Current -1 1 A FAULT PROTECTION Thermal Shutdown Temperature TSD Rising Threshold 150 °C THYS Hysteresis 15 °C PWM UV Trip Level VUV Referred to Nominal VOUT 65 70 75 % PWM UVP Propagation Delay 360 ns PWM OCP Threshold (Note 4) 1.85 2.7 3.00 A OCP Blanking Time 150 ns POWER GOOD PG_PWM Trip Level Referred to Nominal VOUT Falling Edge, 15mV Hysteresis 84 88 92 % Rising Edge, 15mV Hysteresis 107 110 113 % PG_PWM and PG_LDOx Propagation Delay 160 ns PG_PWM Low Voltage ISINK = 4mA 0.3 V PG_PWM Leakage Current VPG_PWM = 5V, VFB_PWM = 600mV -1 1 A PG_LDOx Trip Level Referred to Nominal VOUT Falling Edge, 15mV Hysteresis 81 85 88 % PG_LDOx Low Voltage ISINK = 4mA 0.3 V PG_LDOx Leakage Current VPG_LDOx = 5V, VFB_LDOx = 600mV -1 1 A SOFT-START SECTION Soft-Start Threshold to Enable Buck 0.8 1.0 1.2 V Soft-Start Threshold to Enable PG 2.8 2.95 3.1 V Soft-Start Voltage High 3.3 V Soft-Start Charging Current 25 30 35 A Soft-Start Pull-down VSS = 3.0V 25 mA POWER MOSFET rDS(ON) IOUT = 100mA 120 350 m LDOx FB_LDOx Voltage Accuracy IOUT = 10mA -1.5 1.5 % FB Leakage Current VFB = 0.6V -200 -80 nA Output Current Limit 550 800 1000 mA Dropout Voltage IOUT = 450mA, VOUT > 2V (Note 5) 150 300 mV FB_LDOx Line Regulation IOUT = 0mA, VIN_LDO1 = 2.0 ~4.6V -0.6 0.6 %/V FB_LDOx Load Regulation IOUT = 10mA to 500mA ±0.5 % NOTES: 3. Test Condition: VIN = 15V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included. 4. Limits established by characterization and are not production tested. 5. The dropout voltage is defined as minimum amount VIN must exceed a desired VOUT operating point. VLDO = VIN_LDO - VOUT. 6. The input voltage VCC must be higher than VIN_LDO or the LDO will not function. 7. Specifications at -40°C to +85°C are guaranteed by +25°C test with margin limits. Electrical Specifications Unless Otherwise Noted, All Parameter Limits are Guaranteed Over the Recommended Operating Conditions and the Typical Specifications are Measured at the Following Conditions: TA = -40°C To +85°C (Note 7), VIN = 6V to 25V, Unless Otherwise Noted. Typical Values are at TA = +25°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITSFN6500 Rev 1.00 Page 6 of 19 July 12, 2007

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ISL8501Pin Descriptions VIN The input supply for the PWM regulator power stage and the source for the internal linear regulator that provides bias for the IC. Place a ceramic capacitor from VIN to GND, close to the IC for decoupling (typical 1F). PVCC Connect this pin to VCC. GND Ground connect for the IC and thermal relief for the package. The exposed pad must be connected to GND and soldered to the PCB. All voltage levels are measured with respect to this pin. VCC Internal 5V linear regulator output provides bias to all the internal control logic. The ISL8501 may be powered directly from a 5V (±10%) supply at this pin. When used as a 5V supply input, this pin must be externally connected to VIN. The VCC pin must always be decoupled to GND with a ceramic bypass capacitor (minimum 1F) located close to the pin. FB and COMP The standard buck regulator employs a single voltage control loop. FB is the negative input to the voltage loop error amplifier. COMP is the output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. Connecting an AC network across COMP and FB provide loop compensation to the amplifier. In addition, the PWM regulator power good and under- voltage protection circuitry use FB to monitor the regulator output voltage. PHASE Switch node connections to internal power MOSFET source, external output inductor, and external diode cathode. BOOT Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the necessary charge to turn and hold on the internal N-Channel MOSFET. Connect an external capacitor from this pin to PHASE. EN PWM controller enable input. The PWM converter and LDO's outputs are held off when the pin is pulled to ground. When the voltage on this pin rises above 1.7V, the chip is enabled. SS Program pin for soft-start duration. A regulated 30A pull-up current source charges a capacitor connected from the pin to GND. The output voltage of the converter follows the ramping voltage on the SS pin. VIN_LDO1, VIN_LDO2 Input voltage pin for each LDO. VOUT1, VOUT2 LDO output pins. Bypass with a minimum of 2.2F, low ESR capacitor to GND for stable operation. FB_LDO1, FB_LDO2 Used to set the output of LDO with the proper selection of resistor divider. The resistors should be selected to provide a minimum current of 200nA load for the LDO. CC1, CC2 Compensation capacitor connection for each LDO. Connect a 0.033F capacitor from each pin to ground. EN_LDO1, EN_LDO2 These pins are threshold-sensitive enable inputs for the individual LDOs. Held low, this pin disables the respective LDO. PG_PWM PWM converter power good output. Open drain logic output that is pulled to ground when the output voltage is outside regulation limits. Connect a 100k resistor from this pin to VCC. Pin is low when the buck regulator output voltage is not within 10% of the respective nominal voltage, or during the soft-start interval. Pin is high impedance when the output is within regulation. PG_LDO Combined LDO power good output. Connect a 100k resistor from this pin to VCC. TABLE 1. INPUT SUPPLY CONFIGURATION INPUT PIN CONFIGURATION 6V to 25V Connect the input supply to the VIN pin only. The VCC pin will provide a 5V output from the internal linear regulator. 5V ±10% Connect the input supply to the VIN and VCC pins.FN6500 Rev 1.00 Page 7 of 19 July 12, 2007

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ISL8501Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V, ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = +25°C. FIGURE 3. EFFICIENCY vs LOAD, VIN = 7V FIGURE 4. EFFICIENCY vs LOAD, VIN = 12V FIGURE 5. EFFICIENCY vs LOAD, VIN = 25V FIGURE 6. VOUT REGULATION vs LOAD, 500kHz 1.2VOUT FIGURE 7. VOUT REGULATION vs LOAD, 500kHz 1.2VOUT FIGURE 8. VOUT REGULATION vs LOAD, 500kHz 1.8VOUT 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) E F F IC IE N C Y ( % ) 1.5VOUT 1.2VOUT 1.8VOUT 2.5VOUT 3.3VOUT 5.0VOUT 0 10 20 30 40 50 60 70 80 90 100 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) E F F IC IE N C Y ( % ) 1.5VOUT 1.8VOUT 1.2VOUT 2.5VOUT 3.3VOUT 5.0VOUT 0 10 20 30 40 50 60 70 80 90 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) E F F IC IE N C Y ( % ) 1.5VOUT 1.8VOUT 1.2VOUT 2.5VOUT 3.3VOUT 5.0VOUT 1.212 1.213 1.214 1.215 1.216 1.217 1.218 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VIN 1.505 1.506 1.506 1.507 1.507 1.508 1.508 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VIN 1.806 1.807 1.807 1.808 1.808 1.809 1.809 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VINFN6500 Rev 1.00 Page 8 of 19 July 12, 2007

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ISL8501FIGURE 9. VOUT REGULATION vs LOAD, 500kHz 2.5VOUT FIGURE 10. VOUT REGULATION vs LOAD, 500kHz 3.3VOUT FIGURE 11. VOUT REGULATION vs LOAD, 5VOUT FIGURE 12. POWER DISSIPATION vs LOAD, 3.3VOUT FIGURE 13. INPUT POWER vs VIN, VOUT = 3.3V FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN Typical Performance Curves Circuit of Figure 2. VIN = 12V, VIN_LDO1 = VIN_LDO2 = VOUT1 = 3.3V, IOUT1 = 1A, VLDO1 = 1.2V, ILDO1 = 450mA, VLDO2 = 1.8V, ILDO2 = 450mA, TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = +25°C. (Continued) 2.500 2.501 2.501 2.502 2.502 2.503 2.503 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VIN 3.300 3.303 3.305 3.308 3.310 3.313 3.315 3.318 3.320 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VIN 5.005 5.006 5.007 5.008 5.009 5.010 5.011 5.012 5.013 5.014 5.015 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) O U T P U T V O LT A G E ( V ) 12VIN 25VIN 7VIN 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.00 0.25 0.50 0.75 1.00 1.25 1.50 OUTPUT LOAD (A) P O W E R D IS S IP A T IO N ( W ) 12VIN 25VIN 7VIN 0.00 0.02 0.04 0.06 0.08 0.10 0.12 5 7 9 11 13 15 17 19 21 23 25 INPUT VOLTAGE (V) IN P U T P O W E R ( W ) NO LOAD 3.310 3.312 3.314 3.316 3.318 3.320 5 7 9 11 13 15 17 19 21 23 25 O U T P U T V O LT A G E ( V ) INPUT VOLTAGE (V) NO LOAD 2A LOAD 1A LOADFN6500 Rev 1.00 Page 9 of 19 July 12, 2007

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