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KSZ8031RNL

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KSZ8031RNL

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Part Number KSZ8031RNL
Manufacturer Microchip Technology
Description IC TXRX ETHERNET 24QFN
Datasheet KSZ8031RNL Datasheet
Package 24-VFQFN Exposed Pad
In Stock 268 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Nov 2 - Nov 7 (Choose Expedited Shipping)
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Part Number # KSZ8031RNL (Interface - Drivers, Receivers, Transceivers) is manufactured by Microchip Technology and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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KSZ8031RNL Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Interface - Drivers, Receivers, Transceivers
Datasheet KSZ8031RNLDatasheet
Package24-VFQFN Exposed Pad
Series-
TypeTransceiver
ProtocolRMII
Number of Drivers/Receivers1/1
DuplexFull
Receiver Hysteresis-
Data Rate-
Voltage - Supply1.8V, 2.5V, 3.3V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case24-VFQFN Exposed Pad
Supplier Device Package24-QFN (4x4)

KSZ8031RNL Datasheet

Page 1

Page 2

KSZ8021RNL / KSZ8031RNL 10Base-T/100Base-TX PHY with RMII Support LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 2010 M9999-082710-1.0 General Description The KSZ8031RNL is a single-supply 10Base-T/100Base- TX Ethernet physical layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8031RNL is a highly-integrated, compact solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low noise regulator to supply the 1.2V core, and by offering 1.8/2.5/3.3V digital I/O interface support. The KSZ8031RNL offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors and switches. As the power-up default, the KSZ8031RNL uses a 25MHz crystal to generate all required clocks, including the 50MHz RMII reference clock output for the MAC. The KSZ8021RNL is the version that takes in the 50MHz RMII reference clock as the power-up default. To facilitate system bring-up and debugging in production testing and in product deployment, parametric NAND tree support enables fault detection between KSZ8031RNL I/Os and board, while Micrel’s LinkMD® TDR-based cable diagnostics permit identification of faulty copper cabling. The KSZ8031RNL and KSZ8021RNL are available in 24- pin, lead-free QFN packages (see Ordering Information). Data sheets and support documentation can be found on Micrel’s web site at: www.micrel.com. Features • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet Transceiver • RMII v1.2 Interface support with 50MHz reference clock output to MAC, and option to input 50MHz reference clock • RMII back-to-back mode support for 100Mbps copper repeater or media converter • MDC/MDIO Management Interface for PHY register configuration • Programmable interrupt output • LED outputs for link and activity status indication • On-chip termination resistors for the differential pairs • Baseline Wander Correction • HP Auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option • Auto-negotiation to automatically select the highest link- up speed (10/100 Mbps) and duplex (half/full) • Power down and power saving modes • LinkMD® TDR-based cable diagnostics for identification of faulty copper cabling • Parametric NAND Tree support for fault detection between chip I/Os and board ____________________________________________________________________________________________________________ Functional Diagram

Page 3

Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 2 M9999-082710-1.0 More Features • Loopback modes for diagnostics • Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V • Built-in 1.2V regulator for core • Available in 24-pin (4mm x 4mm) QFN package Applications • Game Console • IP Phone • IP Set-top Box • IP TV • LOM • Printer Ordering Information Part Number Temperature Range Package Lead Finish Description KSZ8021RNL 0°C to 70°C 24-Pin QFN Pb-Free RMII with 50MHz clock input (power-up default), Commercial Temperature KSZ8021RNLI (1) −40°C to 85°C 24-Pin QFN Pb-Free RMII with 50MHz clock input (power-up default), Industrial Temperature KSZ8031RNL 0°C to 70°C 24-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Commercial Temperature KSZ8031RNLI (1) −40°C to 85°C 24-Pin QFN Pb-Free RMII with 25MHz crystal/clock input and 50MHz RMII REF_CLK output (power-up default), Industrial Temperature Note: 1. Contact factory for lead time.

Page 4

Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 3 M9999-082710-1.0 Revision History Revision Date Summary of Changes 1.0 8/16/10 Data sheet created.

Page 5

Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 4 M9999-082710-1.0 Contents General Description .............................................................................................................................................................. 1 Features ................................................................................................................................................................................. 1 Functional Diagram............................................................................................................................................................... 1 Applications........................................................................................................................................................................... 2 Ordering Information ............................................................................................................................................................ 2 Revision History.................................................................................................................................................................... 3 Contents................................................................................................................................................................................. 4 List of Figures........................................................................................................................................................................ 6 List of Tables ......................................................................................................................................................................... 7 Pin Configuration – KSZ8021RNL / KSZ8031RNL.............................................................................................................. 8 Pin Description – KSZ8021RNL / KSZ8031RNL ................................................................................................................. 9 Strapping Options – KSZ8021RNL / KSZ8031RNL .......................................................................................................... 11 Functional Description: 10Base-T/100Base-TX Transceiver ......................................................................................... 12 100Base-TX Transmit.......................................................................................................................................................12 100Base-TX Receive........................................................................................................................................................12 10Base-T Transmit ...........................................................................................................................................................12 10Base-T Receive ............................................................................................................................................................13 Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 13 PLL Clock Synthesizer......................................................................................................................................................13 Auto-Negotiation ...............................................................................................................................................................13 RMII Data Interface..............................................................................................................................................................15 RMII Signal Definition .......................................................................................................................................................15 Reference Clock (REF_CLK) .......................................................................................................................................15 Transmit Enable (TXEN) ..............................................................................................................................................15 Transmit Data [1:0] (TXD[1:0]) .....................................................................................................................................15 Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 15 Receive Data [1:0] (RXD[1:0]) ......................................................................................................................................16 Receive Error (RXER) ..................................................................................................................................................16 Collision Detection........................................................................................................................................................16 RMII Signal Diagram – for KSZ8021/31RNL......................................................................................................................16 RMII – 25MHz Clock Mode...............................................................................................................................................16 RMII – 50MHz Clock Mode...............................................................................................................................................17 Back-to-Back Mode – 100Mbps Copper Repeater / Media Converter............................................................................ 18 RMII Back-to-Back Mode..................................................................................................................................................18 MII Management (MIIM) Interface.......................................................................................................................................19 Interrupt (INTRP) .................................................................................................................................................................19 HP Auto MDI/MDI-X .............................................................................................................................................................19 Straight Cable ...................................................................................................................................................................20 Crossover Cable ...............................................................................................................................................................20 LinkMD® Cable Diagnostics................................................................................................................................................21

Page 6

Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 5 M9999-082710-1.0 NAND Tree Support ............................................................................................................................................................21 NAND Tree I/O Testing.....................................................................................................................................................22 Power Management ............................................................................................................................................................22 Power Saving Mode..........................................................................................................................................................22 Energy Detect Power Down Mode ...................................................................................................................................22 Power Down Mode ...........................................................................................................................................................22 Slow Oscillator Mode ........................................................................................................................................................23 Reference Circuit for Power and Ground Connections .................................................................................................. 23 Register Map........................................................................................................................................................................24 Register Description ...........................................................................................................................................................24 Register Description (Continued)......................................................................................................................................25 Register Description (Continued)......................................................................................................................................26 Register Description (Continued)......................................................................................................................................27 Register Description (Continued)......................................................................................................................................28 Register Description (Continued)......................................................................................................................................29 Register Description (Continued)......................................................................................................................................30 Register Description (Continued)......................................................................................................................................31 Register Description (Continued)......................................................................................................................................32 Absolute Maximum Ratings(1) ............................................................................................................................................ 33 Operating Ratings(2) ............................................................................................................................................................ 33 Electrical Characteristics(3) ................................................................................................................................................ 33 Electrical Characteristics(3) (Continued) ........................................................................................................................... 34 Timing Diagrams .................................................................................................................................................................35 RMII Timing.......................................................................................................................................................................35 Auto-Negotiation Timing ...................................................................................................................................................36 MDC/MDIO Timing ...........................................................................................................................................................37 Reset Timing.....................................................................................................................................................................38 Reset Circuit ........................................................................................................................................................................39 Reference Circuit for LED Strapping Pin..........................................................................................................................40 Magnetics Specification .....................................................................................................................................................41 Reference Clock – Connection and Selection.................................................................................................................. 41 Package Information...........................................................................................................................................................43

Page 7

Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 6 M9999-082710-1.0 List of Figures Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................14 Figure 2. KSZ8021/31RNL RMII Interface (RMII – 25MHz Clock Mode) ............................................................................ 16 Figure 3. KSZ8021/31RNL RMII Interface (RMII – 50MHz Clock Mode) ............................................................................ 17 Figure 4. KSZ8021/31RNL and KSZ8041FTL RMII Back-to-Back Media Converter .......................................................... 18 Figure 5. Typical Straight Cable Connection .......................................................................................................................20 Figure 6. Typical Crossover Cable Connection ...................................................................................................................20 Figure 7. KSZ8021/31RNL Power and Ground Connections .............................................................................................. 23 Figure 8. RMII Timing – Data Received from RMII ..............................................................................................................35 Figure 9. RMII Timing – Data Input to RMII .........................................................................................................................35 Figure 10. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 36 Figure 11. MDC/MDIO Timing..............................................................................................................................................37 Figure 12. Reset Timing.......................................................................................................................................................38 Figure 13. Recommended Reset Circuit..............................................................................................................................39 Figure 14. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 39 Figure 15. Reference Circuits for LED Strapping Pin ..........................................................................................................40 Figure 16. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................... 41 Figure 17. 50MHz Oscillator Reference Clock Connection ................................................................................................. 42

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Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 7 M9999-082710-1.0 List of Tables Table 1. RMII Signal Description..........................................................................................................................................15 Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ......................................18 Table 3. MII Management Frame Format – for KSZ8021/31RNL........................................................................................ 19 Table 4. MDI/MDI-X Pin Definition .......................................................................................................................................20 Table 5. NAND Tree Test Pin Order – for KSZ8021/31RNL ............................................................................................... 21 Table 6. KSZ8021/31RNL Power Pin Description ............................................................................................................... 23 Table 7. RMII Timing Parameters – KSZ8021/31RNL (25MHz input to XI pin, 50MHz output from REF_CLK pin)........... 35 Table 8. RMII Timing Parameters – KSZ8021/31RNL (50MHz input to XI pin)................................................................... 35 Table 9. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ................................................................................. 36 Table 10. MDC/MDIO Timing Parameters ...........................................................................................................................37 Table 11. Reset Timing Parameters ....................................................................................................................................38 Table 12. Magnetics Selection Criteria ................................................................................................................................41 Table 13. Qualified Single Port 10/100 Magnetics...............................................................................................................41 Table 14. 25MHz Crystal / Reference Clock Selection Criteria ........................................................................................... 42 Table 15. 50MHz Oscillator / Reference Clock Selection Criteria ....................................................................................... 42

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Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 8 M9999-082710-1.0 Pin Configuration – KSZ8021RNL / KSZ8031RNL 24-Pin (4mm x 4mm) QFN

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Micrel, Inc. KSZ8021RNL / KSZ8031RNL August 2010 9 M9999-082710-1.0 Pin Description – KSZ8021RNL / KSZ8031RNL Pin Number Pin Name Type(1) Pin Function 1 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8021RNL / KSZ8031RNL) Decouple with 2.2uF and 0.1uF capacitors-to-ground. 2 VDDA_3.3 P 3.3V analog VDD. 3 RXM I/O Physical receive or transmit signal (- differential) 4 RXP I/O Physical receive or transmit signal (+ differential) 5 TXM I/O Physical transmit or receive signal (- differential) 6 TXP I/O Physical transmit or receive signal (+ differential) 7 XO O Crystal feedback – for 25 MHz crystal This pin is a no connect if oscillator or external clock source is used. 8 XI I RMII – 25MHz Mode: 25MHz +/-50ppm Crystal / Oscillator / External Clock Input RMII – 50MHz Mode: 50MHz +/-50ppm Oscillator / External Clock Input For unmanaged mode (power-up default setting), KSZ8021RNL takes in the 50MHz clock on this pin. KSZ8031RNL takes in the 25MHz crystal / clock on this pin. After power-up, both the KSZ8021RNL and KSZ8031RNL can be programmed via PHY register 1Fh bit [7] to either the 25MHz mode or 50MHz mode. See also REF_CLK (pin 16) description. 9 REXT I Set physical transmit output current Connect a 6.49KΩ resistor-to-ground on this pin. 10 MDIO I/O Management Interface (MII) Data I/O This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pull- up resistor. 11 MDC I Management Interface (MII) Clock Input This clock pin is synchronous to the MDIO data pin. 12 RXD1 Ipd/O RMII Receive Data Output[1](2) 13 RXD0 Ipu/O RMII Receive Data Output[0](2) 14 VDDIO P 3.3V, 2.5V or 1.8V digital VDD 15 CRS_DV / PHYAD[1:0] Ipd/O RMII Mode: Carrier Sense/Receive Data Valid Output / Config Mode: The pull-up/pull-down value is latched as PHYAD[1:0] at the de-assertion of reset. See “Strapping Options” section for details. 16 REF_CLK Ipd/O RMII – 25MHz Mode: This pin provides the 50MHz RMII reference clock output to the MAC. RMII – 50MHz Mode: This pin is a no connect. For unmanaged mode (power-up default setting), KSZ8021RNL is in RMII – 50MHz mode and does not use this pin. KSZ8031RNL is in RMII – 25MHz mode and outputs the 50MHz RMII reference clock on this pin. After power-up, both KSZ8021RNL and KSZ8031RNL can be programmed via PHY register 1Fh bit [7] to either 25MHz mode or 50MHz mode. See also XI (pin 8) description. 17 RXER Ipd/O RMII Receive Error Output 18 INTRP Ipu/Opu Interrupt Output: Programmable Interrupt Output This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pull- up resistor.

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