LD39200DPUR

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Features • Input voltage from 1.25 V to 6.0 V • Ultra low drop: 130 mV (typ.) at 2 A load • 1 % output accuracy at 25 °C, 2 % in full temperature range • High PSRR: 70 dB at 1 kHz • Reverse current protection • 2 A guaranteed output current • Available in fixed and adjustable output voltage version from 0.5 V with 100 mV step • Power Good • Internal current and thermal limit • Operating junction temperature range: -40 °C to 125 °C • DFN6 (3 x 3 mm) and DFN8 (4 x 4 mm) packages Applications • Telecom infrastructure • Medium power POL Description The LD39200 provides 2 A of maximum current with an input voltage range from 1.25 V to 6.0 V, and a typical dropout voltage of 130 mV. It is stable with ceramic capacitors on the output (10 µF). Typical power supply rejection ratio is 70 dB at 1 kHz and starts to roll off at 20 kHz. The enable logic control function puts the LD39200 in shutdown mode, reducing the total current consumption to 10 nA (typ.). Power Good flag is available on a dedicated pin. The device also includes reverse current protection, short-circuit constant current limit and thermal protection. Typical applications are for Telecom infrastructure and consumer. Maturity status link LD39200 2 A high PSRR ultra low drop linear regulator with reverse current protection LD39200 Datasheet DS10079 - Rev 3 - September 2018 For further information contact your local STMicroelectronics sales office. www.st.com

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1 Block diagram Figure 1. Block diagram VIN VOUT 500mV PMOS OPAMP VFB Bandgap reference R3 R4 RC filter R2 R1 VREF VFB PG EN Power good Enable Internal enable Reverse current protection 500mV AM13907V1 LD39200 Block diagram DS10079 - Rev 3 page 2/29

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2 Pin configuration and description Figure 2. Pin configuration (top view) AM13909V1 IN IN EN PG OUT OUT ADJ/SENSE GND OUT ADJ/SENSE GND IN EN PG Table 1. DFN6 (3 x 3 mm) package pin description Pin name Pin number Description IN 6 Input voltage GND 3 Ground EN 5 Enable pin. The device is in OFF state when this pin is pulled low ADJ/sense (1) 2 Adjustable pin on ADJ version can be connected to external resistor divider to set the output voltage. Output sense pin on the fixed version has to be connected to VOUT OUT 1 Output voltage PG 4 Power Good GND Exposed pad Exposed pad should be connected to GND 1. The output sense pin of the fixed version has to be connected to the output pin for proper operation. Table 2. DFN8 (4 x 4 mm) package pin description Pin name Pin number Description IN (1) 7, 8 Input voltage GND 4 Ground EN 6 Enable pin. The device is in OFF state when this pin is pulled low ADJ/sense (2) 3 Adjustable pin on ADJ version can be connected to external resistor divider to set the output voltage. Output sense pin on the fixed version has to be connected to VOUT OUT (3) 1, 2 Output voltage PG 5 Power Good GND Exposed pad Exposed pad should be connected to GND 1. Both of input pins have to be connected together on the board. 2. The output sense pin of the fixed version has to be connected to the OUT pin for proper operation. 3. Both of output pins have to be connected together on the board. LD39200 Pin configuration and description DS10079 - Rev 3 page 3/29

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3 Typical application Figure 3. LD39200 typical application schematic Adjustable version Fixed version AM13909V1 OUT GND IN EN ADJ ON OFF CIN R1 R2 COUTLD39200 CBYP (optional) OUT GND IN EN SENSE ON OFF CIN LD39200 COUT PG PG Note: R1 and R2 are calculated according to the following formula: R1 = R2 x (VOUT / VADJ - 1). Recommended value for CIN and COUT is 10 μF. LD39200 Typical application DS10079 - Rev 3 page 4/29

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4 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VIN Input supply voltage -0.3 to 7 V VADJ Adjustable voltage -0.3 to 2 V VOUT /VSENSE Output voltage/output sense voltage -0.3 to 7 V IOUT Output current Internally limited A EN Enable pin voltage -0.3 to 7 V PG Power Good pin voltage -0.3 to 7 V PD Power dissipation Internally limited W ESD Charge device model ±500 V Human body model ±2000 TJ-OP Operating junction temperature -40 to 125 °C TJ-MAX Maximum junction temperature 150 °C TSTG Storage temperature -55 to 150 °C Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Thermal data Symbol Parameter DFN6 (3 x 3 mm) DFN8 (4 x 4 mm) Unit RTHJC Junction-to-case thermal resistance 10 4 °C/W RTHJA Junction-to- ambient thermal resistance 55 40 LD39200 Maximum ratings DS10079 - Rev 3 page 5/29

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5 Electrical characteristics (TJ = 25 °C, VIN = VOUT+1 V; VOUT = VADJ; CIN = 10 µF; COUT = 10 µF; IOUT = 10 mA; VEN = VIN) Table 5. Electrical characteristics, adjustable version Symbol Parameter Test conditions Min. Typ. Max. Unit VIN Operating input voltage range 1.25 6.0 V VADJ Adjustable pin voltage 0.5 V Adjustable pin voltage accuracy TJ = 25 °C -1.0 1.0 % -40 °C < TJ < 125 °C -2.0 2.0 IADJ Adjustable pin current -40 °C < TJ < 125 °C 100 nA ∆VADJ%/ ∆VIN Static line regulation VOUT + 1 V < VIN < 6.0 V; TJ = 25 °C 0.01 %/V -40 °C < TJ < 125 °C 0.2 ∆VADJ%/ ∆IOUT Static load regulation 0 mA < IOUT < 2 A; TJ = 25 °C 0.1 %/A -40 °C < TJ < 125 °C 0.4 VDROP Dropout voltage (1) VIN = 1.4 V; IOUT = 1 A; -40 °C < TJ < 125 °C 120 250 mV VIN = 2.5 V; IOUT = 2 A; -40 °C < TJ < 125 °C 135 250 VIN = 5.3 V; IOUT = 2 A; -40 °C < TJ < 125 °C 110 250 eN Output noise voltage VOUT = VADJ ; f = 10 Hz to 100 kHz 45 µVRMS / VOUT eN Output noise voltage VIN = VOUT + 0.4 V, IOUT = 700 mA; CIN = COUT = 10 µF, R2 = 10 kΩ, R1 = (VOUT – 0.5) x 20 kΩ, Cbyp = 470 nF 24 µVRMS SVR Supply voltage rejection VOUT = 1.8 V; VIN = VOUT+0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 1 kHz 70 dB VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 100 kHz 50 VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 500 kHz 50 dB VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 1 MHz 40 LD39200 Electrical characteristics DS10079 - Rev 3 page 6/29

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Symbol Parameter Test conditions Min. Typ. Max. Unit IQ Quiescent current IOUT = 0 A 100 µA IOUT = 0 A; -40 °C < TJ < 125 °C 300 IOUT = 2 A; 1 mA IOUT = 2 A; -40 °C < TJ < 125 °C 3 Shutdown current Ven = 0, Vin = 6 V 10 nA ISC Short-circuit current VOUT = 0 V 3.5 A IMIN Minimum output current 0 A VEN Enable input logic low 1.25 V < VIN < 6.0 V -40 °C < TJ < 125 °C 0.5 V Enable input logic high 1.2 IEN Enable pin input current VEN = VIN; 1.25 < VIN < 6.0 V 10 nA PG Power Good output threshold Rising edge 0.92* Vout VFalling edge 0.8*Vout Power Good output voltage low Isink = 6 mA open drain output 0.4 TSHDN Thermal shutdown 170 °C Hysteresis 20 1. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value; this specification does not apply to nominal output voltages below 1.2 V. (TJ = 25 °C, VIN = VOUT+1 V; CIN = 10 µF; COUT = 10 µF; IOUT = 10 mA; VEN = VIN) Table 6. Electrical characteristics, fixed version Symbol Parameter Test conditions Min. Typ. Max. Unit VIN Operating input voltage range 1.25 6.0 V VOUT Output voltage accuracy TJ = 25 °C -1.0 1.0 % -40 °C < TJ < 125 °C -2.0 2.0 ∆VADJ%/ ∆VIN Static line regulation VOUT + 1 V < VIN < 6.0 V; TJ = 25 °C 0.01 %/V -40 °C < TJ < 125 °C 0.1 ∆VADJ%/ ∆IOUT Static load regulation 0 mA < IOUT < 2 A; TJ = 25 °C 0.05 %/A -40 °C < TJ < 125 °C 0.4 VDROP Dropout voltage VOUT = 3.3 V; IOUT = 2 A; -40 °C < TJ < 125 °C 130 250 mV eN Output noise voltage VOUT = 2.5 V; f = 10 Hz to 100 kHz 40 µVRMS /VOUT LD39200 Electrical characteristics DS10079 - Rev 3 page 7/29

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Symbol Parameter Test conditions Min. Typ. Max. Unit SVR Supply voltage rejection VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 1 kHz 70 dB VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 100 kHz 50 VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 500 kHz 50 VOUT = 1.8 V; VIN = VOUT + 0.5 V; COUT = 10 µF; IOUT = 10 mA; TJ = 25 °C; f = 1 MHz 40 IQ Quiescent current IOUT = 0 A 100 µA IOUT = 0 A; -40 °C < TJ < 125 °C 300 IOUT = 2 A; 1 mA IOUT = 2 A; -40 °C < TJ < 125 °C 3 Shutdown current Ven = 0, Vin = 6 V 50 nA ISC Short-circuit current VOUT = 0 V 3.5 A IMIN Minimum output current 0 A VEN Enable input logic low 1.25 V < VIN < 6.0 V -40 °C < TJ < 125 °C 0.5 V Enable input logic high 1.2 IEN Enable pin input current VEN = VIN; 1.25 < VIN < 6.0 V 10 nA PG Power Good output threshold Rising edge 0.92*VOUT VFalling edge 0.8*VOUT Power Good output voltage low Isink = 6 mA open drain output 0.4 TSHDN Thermal shutdown 170 °C Hysteresis 20 LD39200 Electrical characteristics DS10079 - Rev 3 page 8/29

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6 Application information 6.1 Thermal and short-circuit protections The LD39200 is self-protected from short-circuit conditions and overtemperature. When the output load is higher than the one supported by the device, the output current rises until the limit of typically 3.5 A is reached; at this point the current is kept constant even when the load impedance is zero. The thermal protection acts when the junction temperature reaches 170 °C. The IC enters the shutdown status. As soon as the junction temperature falls again below 150 °C the device starts working again. In order to calculate the maximum power the device can dissipate, keeping the junction temperature below TJ-OP , the following formula is used:PDMAX = 125− TAMB / RTHJ − A (1) 6.2 Output voltage setting for ADJ version In the adjustable version, the output voltage can be set from 0.5 V up to the input voltage minus the voltage drop across the pass transistor (dropout voltage), by connecting a resistor divider between the ADJ pin and the output, allowing remote voltage sensing. The resistor divider can be selected using the following equation:VOUT = VADJ 1 + R1/ R2 , witℎ VADJ = 0.5 V typ. (2) 6.3 Enable pin The LD39200 features an enable function. When the EN voltage is higher than 1.2 V the device is ON, and if it is lower than 0.5 V the device is OFF. In shutdown mode, the total current consumption is 10 nA (typ). The EN pin does not have an internal pull-up, therefore it cannot be left floating if it is not used. 6.4 Power Good pin (PG) Some applications require a flag showing that the output voltage is in the correct range. Power Good threshold depends on the output voltage. When the output voltage is higher than 0.92 * VOUT(nom), the PG pin goes to high impedance. If the output voltage is below 0.80 * VOUT(nom) the PG pin goes to low impedance. If the device works well, the PG pin is at high impedance. 6.5 Reverse current protection The device avoids the reverse current to flow from the output to the input during any operating condition (EN = 0 or EN = 1, VIN > VOUT + VDROP). During fast turn-on/off this function prevents a big current from flowing to the input. Moreover it is used to avoid the reverse current to flow from the output pin to the input one, when other power supplies, providing a voltage higher than the input voltage, are connected to the output pin. If a power supply, providing a voltage lower than LDO output voltage, is connected to OUT pin, LDO works in current protection, causing high power dissipation inside the device. When the device is disabled (EN = low) and VOUT > 0 V, a small current (few µA) is sunk from the OUT pin. LD39200 Application information DS10079 - Rev 3 page 9/29