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LFE2-70SE-5FN672C

hot LFE2-70SE-5FN672C

LFE2-70SE-5FN672C

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Part Number LFE2-70SE-5FN672C
Manufacturer Lattice Semiconductor Corporation
Description IC FPGA 500 I/O 672FBGA
Datasheet LFE2-70SE-5FN672C Datasheet
Package 672-BBGA
In Stock 1128 piece(s)
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LFE2-70SE-5FN672C Specifications

ManufacturerLattice Semiconductor Corporation
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet LFE2-70SE-5FN672C Datasheet
Package672-BBGA
SeriesECP2
Number of LABs/CLBs8500
Number of Logic Elements/Cells68000
Total RAM Bits1056768
Number of I/O500
Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case672-BBGA
Supplier Device Package672-FPBGA (27x27)

LFE2-70SE-5FN672C Datasheet

Page 1

Page 2

LatticeECP2/M Family Data Sheet DS1006 Version 04.1, September 2013

Page 3

www.latticesemi.com 1-1 DS1006 Introduction_02.0 July 2012 Data Sheet DS1006 © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Features  High Logic Density for System Integration • 6K to 95K LUTs • 90 to 583 I/Os  Embedded SERDES (LatticeECP2M Only) • Data Rates 250 Mbps to 3.125 Gbps • Up to 16 channels per device PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI and Serial RapidIO.  sysDSP™ Block • 3 to 42 blocks for high performance multiply and accumulate • Each block supports – One 36x36, four 18x18 or eight 9x9 multipliers  Flexible Memory Resources • 55Kbits to 5308Kbits sysMEM™ Embedded Block RAM (EBR) – 18Kbit block – Single, pseudo dual and true dual port – Byte Enable Mode support • 12K to 202Kbits distributed RAM – Single port and pseudo dual port  sysCLOCK Analog PLLs and DLLs • Two GPLLs and up to six SPLLs per device – Clock multiply, divide, phase & delay adjust – Dynamic PLL adjustment • Two general purpose DLLs per device  Pre-Engineered Source Synchronous I/O • DDR registers in I/O cells • Dedicated gearing logic • Source synchronous standards support – SPI4.2, SFI4 (DDR Mode), XGMII – High Speed ADC/DAC devices • Dedicated DDR and DDR2 memory support – DDR1: 400 (200MHz) / DDR2: 533 (266MHz) • Dedicated DQS support  Programmable sysI/O™ Buffer Supports Wide Range Of Interfaces • LVTTL and LVCMOS 33/25/18/15/12 • SSTL 3/2/18 I, II • HSTL15 I and HSTL18 I, II • PCI and Differential HSTL, SSTL • LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL  Flexible Device Configuration • 1149.1 Boundary Scan compliant • Dedicated bank for configuration I/Os • SPI boot flash interface • Dual boot images supported • TransFR™ I/O for simple field updates • Soft Error Detect macro embedded  Optional Bitstream Encryption (LatticeECP2/M “S” Versions Only)  System Level Support • ispTRACY™ internal logic analyzer capability • On-chip oscillator for initialization & general use • 1.2V power supply Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Device ECP2-6 ECP2-12 ECP2-20 ECP2-35 ECP2-50 ECP2-70 LUTs (K) 6 12 21 32 48 68 Distributed RAM (Kbits) 12 24 42 64 96 136 EBR SRAM (Kbits) 55 221 276 332 387 1032 EBR SRAM Blocks 3 12 15 18 21 60 sysDSP Blocks 3 6 7 8 18 22 18x18 Multipliers 12 24 28 32 72 88 GPLL + SPLL + DLL 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2 Maximum Available I/O 190 297 402 450 500 583 Packages and I/O Combinations 144-pin TQFP (20 x 20 mm) 90 93 208-pin PQFP (28 x 28 mm) 131 131 256-ball fpBGA (17 x 17 mm) 190 193 193 484-ball fpBGA (23 x 23 mm) 297 331 331 339 672-ball fpBGA (27 x 27 mm) 402 450 500 500 900-ball fpBGA (31 x 31 mm) 583 LatticeECP2/M Family Data Sheet Introduction

Page 4

1-2 Introduction LatticeECP2/M Family Data Sheet Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Introduction The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an economical FPGA fabric. This combination was achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configu- ration support, including encryption (“S” versions only) and dual boot capabilities. The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low trans- mission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization settings make SERDES suitable for chip to chip and small form factor backplane applications. Lattice Diamond® design software allows large complex designs to be efficiently implemented using the LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis tools. The Diamond software uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeECP2/M device. The Diamond design tool extracts the timing from the routing and back-annotates it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP2/M family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. Device ECP2M20 ECP2M35 ECP2M50 ECP2M70 ECP2M100 LUTs (K) 19 34 48 67 95 sysMEM Blocks (18kb) 66 114 225 246 288 Embedded Memory (Kbits) 1217 2101 4147 4534 5308 Distributed Memory (Kbits) 41 71 101 145 202 sysDSP Blocks 6 8 22 24 42 18x18 Multipliers 24 32 88 96 168 GPLL+SPLL+DLL 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2 Maximum Available I/O 304 410 410 436 520 Packages and SERDES / I/O Combinations 256-ball fpBGA (17 x 17 mm) 4 / 140 4 / 140 484-ball fpBGA (23 x 23 mm) 4 / 304 4 / 303 4 / 270 672-ball fpBGA (27 x 27 mm) 4 / 410 8 / 372 900-ball fpBGA (31 x 31 mm) 8 / 410 16 / 416 16 / 416 1152-ball fpBGA (35 x 35 mm) 16 / 436 16 / 520

Page 5

www.latticesemi.com 2-1 DS1006 Architecture_02.3 September 2013 Data Sheet DS1006 © 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. Architecture Overview Each LatticeECP2/M device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter- spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and rows of sys- DSP™ Digital Signal Processing blocks, as shown in Figure 2-1. In addition, the LatticeECP2M family contains SERDES Quads in one or more of the corners. Figure 2-2 shows the block diagram of ECP2M20 with one quad. There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and Programmable Functional Unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic and ROM functions. Both PFU and PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and efficiently. Logic Blocks are arranged in a two- dimensional array. Only one type of block is used per row. The LatticeECP2/M devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18K fast memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addition, LatticeECP2/M devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumulators, which are the building blocks for complex signal processing capabilities. The LatticeECP2M devices feature up to 16 embedded 3.125Gbps SERDES (Serializer / Deserializer) channels. Each SERDES channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. Each group of four SERDES channels along with its Physical Coding Sub-layer (PCS) block, creates a quad. The functionality of the SERDES/PCS Quads can be controlled by memory cells set during device configuration or by registers that are addressable during device operation. The registers in every quad can be programmed by a soft IP interface, referred to as the SERDES Client Interface (SCI). These quads (up to four) are located at the corners of the devices. Each PIC block encompasses two PIOs (PIO pairs) with their respective sysI/O buffers. The sysI/O buffers of the LatticeECP2/M devices are arranged in eight banks, allowing the implementation of a wide variety of I/O standards. In addition, a separate I/O bank is provided for the programming interfaces. PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic also includes pre-engineered support to aid in the implementation of high speed source synchronous standards such as SPI4.2, along with memory interfaces including DDR2. The LatticeECP2/M registers in PFU and sysI/O can be configured to be SET or RESET. After power up and the device is configured, it enters into user mode with these registers SET/RESET according to the configuration set- ting, allowing the device entering to a known state for predictable system function. Other blocks provided include PLLs, DLLs and configuration functions. The LatticeECP2/M architecture provides two General PLLs (GPLL) and up to six Standard PLLs (SPLL) per device. In addition, each LatticeECP2/M family member provides two DLLs per device. The GPLLs and DLLs blocks are located in pairs at the end of the bottom- most EBR row; the DLL block is located towards the edge of the device. The SPLL blocks are located at the end of the other EBR/DSP rows. The configuration block that supports features such as configuration bit-stream decryption, transparent updates and dual boot support is located toward the center of this EBR row. The Ball Grid Array (BGA) package devices in the LatticeECP2/M family supports a sysCONFIG™ port located in the corner between banks four and five, which allows for serial or parallel device configuration. In addition, every device in the family has a JTAG port. This family also provides an on-chip oscillator. The LatticeECP2/M devices use 1.2V as their core voltage. LatticeECP2/M Family Data Sheet Architecture

Page 6

2-2 Architecture LatticeECP2/M Family Data Sheet Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level) Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level) Programmable Function Units (PFUs) Flexible sysIO Buffers: LVCMOS, HSTL, SSTL, LVDS, and other standards sysDSP Blocks Multiply and Accumulate Support sysMEM Block RAM 18kbit Dual Port sysCLOCK PLLs and DLLs Frequency Synthesis and Clock Alignment Flexible routing optimized for speed, cost and routability Configuration logic, including dual boot and encryption. On-chip oscillator and soft-error detection. Configuration port Pre-engineered source synchronous support • DDR1/2 • SPI4.2 • ADC/DAC devices Flexible sysIO Buffers: LVCMOS, HSTL SSTL, LVDS Pre-Engineered Source Synchronous Support • DDR1/2 • SPI4.2 • ADC/DAC devices SERDES DSP Blocks Multiply & Accumulate Support On-Chip Oscillator Programmable Function Units (PFUs) Channel 3 Channel 2 Channel 1 Channel 0 sysMEM Block RAM 18kbit Dual Port Configuration Logic, Including dual boot and encryption, and soft-error detection Flexible Routing optimized for speed, cost & routability sysCLOCK GPLLs & GDLLs Frequency Synthesis & Clock Alignment Configuration Port sysCLOCK SPLLs

Page 7

2-3 Architecture LatticeECP2/M Family Data Sheet PFU Blocks The core of the LatticeECP2/M device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remain- der of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-3. All the interconnec- tions to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. Figure 2-3. PFU Diagram Slice Slice 0 through Slice 2 contain two LUT4s feeding two registers, whereas Slice 3 contains two LUT4s only. For PFUs, Slice 0 and Slice 2 can also be configured as distributed memory, a capability not available in the PFF. Table 2-1 shows the capability of the slices in both PFF and PFU blocks along with the operation modes they enable. In addition, each PFU contains some logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. There is control logic to perform set/reset functions (programmable as synchro- nous/asynchronous), clock select, chip-select and wider RAM/ROM functions. Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for positive/negative and edge triggered or level sensitive clocks. Table 2-1. Resources and Modes Available per Slice Slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or PFU). There are seven outputs: six to routing and one to carry-chain (to the adjacent PFU). Slice 3 has 13 input signals from routing and four signals to routing. Table 2-2 lists the signals associated with Slice 0 to Slice 2. Slice PFU BLock PFF Block Resources Modes Resources Modes Slice 0 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 1 2 LUT4s and 2 Registers Logic, Ripple, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 2 2 LUT4s and 2 Registers Logic, Ripple, RAM, ROM 2 LUT4s and 2 Registers Logic, Ripple, ROM Slice 3 2 LUT4s Logic, ROM 2 LUT4s Logic, ROM Slice 0 LUT4 & CARRY LUT4 & CARRY D D Slice 1 LUT4 & CARRY LUT4 & CARRY Slice 2 LUT4 & CARRY LUT4 & CARRY From Routing To Routing Slice 3 LUT4 LUT4 D D D D FF FF FF FF FF FF

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2-4 Architecture LatticeECP2/M Family Data Sheet Figure 2-4. Slice Diagram Table 2-2. Slice Signal Descriptions Function Type Signal Names Description Input Data signal A0, B0, C0, D0 Inputs to LUT4 Input Data signal A1, B1, C1, D1 Inputs to LUT4 Input Multi-purpose M0 Multipurpose Input Input Multi-purpose M1 Multipurpose Input Input Control signal CE Clock Enable Input Control signal LSR Local Set/Reset Input Control signal CLK System Clock Input Inter-PFU signal FC Fast Carry-in1 Input Inter-slice signal FXA Intermediate signal to generate LUT6 and LUT7 Input Inter-slice signal FXB Intermediate signal to generate LUT6 and LUT7 Output Data signals F0, F1 LUT4 output register bypass signals Output Data signals Q0, Q1 Register outputs Output Data signals OFX0 Output of a LUT5 MUX Output Data signals OFX1 Output of a LUT6, LUT7, LUT82 MUX depending on the slice Output Inter-PFU signal FCO Slice 2 of each PFU is the fast carry chain output1 1. See Figure 2-4 for connection details. 2. Requires two PFUs. LUT4 & CARRY* LUT4 & CARRY* SLICE A0 C0 D0 FF* OFX0 F0 Q0 A1 B1 C1 D1 CI CI CO CO CE CLK LSR FF* OFX1 F1 Q1 F/SUM F/SUM D D M1 FCI From Different Slice/PFU FCO To Different Slice/PFU LUT5 Mux M0 From Routing To Routing FXB FXA B0 For Slices 0 and 2, memory control signals are generated from Slice 1 as follows: WCK is CLK WRE is from LSR DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data WAD [A:D] is a 4bit address from slice 1 LUT input * Not in Slice 3

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2-5 Architecture LatticeECP2/M Family Data Sheet Modes of Operation Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM. Logic Mode In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16 possible input combinations. Any four input logic functions can be generated by programming this lookup table. Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four slices. Ripple Mode Ripple mode supports the efficient implementation of small arithmetic functions. In ripple mode, the following func- tions can be implemented by each slice: • Addition 2-bit • Subtraction 2-bit • Add/Subtract 2-bit using dynamic control • Up counter 2-bit • Down counter 2-bit • Up/Down counter with Async clear • Up/Down counter with preload (sync) • Ripple mode multiplier building block • Multiplier support • Comparator functions of A and B inputs – A greater-than-or-equal-to B – A not-equal-to B – A less-than-or-equal-to B Ripple Mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con- figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener- ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating Slices. RAM Mode In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed using each LUT block in Slice 0 and Slice 2 as a 16x1-bit memory. Slice 1 is used to provide memory address and control signals. A 16x2-bit pseudo dual port RAM (PDPR) memory is created by using one Slice as the read-write port and the other companion slice as the read-only port. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives. For more information about using RAM in LatticeECP2/M devices, please see the list of additional technical documentation at the end of this data sheet. Table 2-3. Number of Slices Required to Implement Distributed RAM SPR 16X4 PDPR 16X4 Number of slices 3 3 Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM

Page 10

2-6 Architecture LatticeECP2/M Family Data Sheet ROM Mode ROM mode uses the LUT logic; hence, Slices 0 through 3 can be used in ROM mode. Preloading is accomplished through the programming interface during PFU configuration. Routing There are many resources provided in the LatticeECP2/M devices to route signals individually or as buses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU). The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and x6 resources are buffered, allowing the routing of both short and long connections between PFUs. The LatticeECP2/M family has an enhanced routing architecture that produces a compact design. The Diamond design software takes the output of the synthesis tool and places and routes the design. Generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysCLOCK Phase Locked Loops (GPLL/SPLL) The sysCLOCK PLLs provide the ability to synthesize clock frequencies. All the devices in the LatticeECP2/M fam- ily support two General Purpose PLLs (GPLLs) which are full-featured PLLs. In addition, some of the larger devices have two to six Standard PLLs (SPLLs) that have a subset of GPLL functionality. General Purpose PLL (GPLL) The architecture of the GPLL is shown in Figure 2-5. A description of the GPLL functionality follows. CLKI is the reference frequency (generated either from the pin or from routing) for the PLL. CLKI feeds into the Input Clock Divider block. The CLKFB is the feedback signal (generated from CLKOP or from a user clock PIN/ logic). This signal feeds into the Feedback Divider. The Feedback Divider is used to multiply the reference fre- quency. The Delay Adjust Block adjusts either the delays of the reference or feedback signals. The Delay Adjust Block can either be programmed during configuration or can be adjusted dynamically. The setup, hold or clock-to-out times of the device can be improved by programming a delay in the feedback or input path of the PLL, which will advance or delay the output clock with reference to the input clock. Following the Delay Adjust Block, both the input path and feedback signals enter the Voltage Controlled Oscillator (VCO) block. In this block the difference between the input path and feedback signals is used to control the fre- quency and phase of the oscillator. A LOCK signal is generated by the VCO to indicate that the VCO has locked onto the input clock signal. In dynamic mode, the PLL may lose lock after a dynamic delay adjustment and not relock until the tLOCK parameter has been satisfied. LatticeECP2/M devices have two dedicated pins on the left and right edges of the device for connecting optional external capacitors to the VCO. This allows the PLLs to operate at a lower frequency. This is a shared resource that can only be used by one PLL (GPLL or SPLL) per side. The output of the VCO then enters the post-scalar divider. The post-scalar divider allows the VCO to operate at higher frequencies than the clock output (CLKOP), thereby increasing the frequency range. A secondary divider takes the CLKOP signal and uses it to derive lower frequency outputs (CLKOK). The Phase/Duty Select block adjusts the phase and duty cycle of the CLKOP signal and generates the CLKOS signal. The phase/duty cycle set- ting can be pre-programmed or dynamically adjusted. The primary output from the post scalar divider CLKOP along with the outputs from the secondary divider (CLKOK) and Phase/Duty select (CLKOS) are fed to the clock distribution network.

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