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LNBH25SPQR

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LNBH25SPQR

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Part Number LNBH25SPQR
Manufacturer STMicroelectronics
Description IC LNB CTRL STEP-UP I2C 24QFN
Datasheet LNBH25SPQR Datasheet
Package 24-VFQFN Exposed Pad
In Stock 6,806 piece(s)
Unit Price $ 0.9315 *
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # LNBH25SPQR (PMIC - Voltage Regulators - Special Purpose) is manufactured by STMicroelectronics and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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LNBH25SPQR Specifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Special Purpose
Datasheet LNBH25SPQRDatasheet
Package24-VFQFN Exposed Pad
Series-
ApplicationsConverter, Analog and Digital Satellite STB Receivers/SatTV
Voltage - Input8 V ~ 16 V
Number of Outputs1
Voltage - Output13V, 18V
Operating Temperature0°C ~ 85°C
Mounting TypeSurface Mount
Package / Case24-VFQFN Exposed Pad
Supplier Device Package24-QFN (4x4)

LNBH25SPQR Datasheet

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October 2016 DocID026736 Rev 3 1/37 This is information on a product in full production. www.st.com LNBH25S LNB supply and control IC with step-up and I²C interface Datasheet - production data Features  Complete interface between LNB and I²C bus  Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A)  Selectable output current limit by external resistor  Compliant with main satellite receiver output voltage specifications (15 programmable levels)  Accurate built-in 22 kHz tone generator suits widely accepted standards  22 kHz tone waveform integrity guaranteed at no-load condition  Low drop post regulator and high efficiency step-up PWM with integrated power NMOS allowing low power losses  LPM function (low power mode) to reduce dissipation  Overload and overtemperature internal protections with I²C diagnostic bits  LNB short-circuit dynamic protection  +/- 4 kV ESD tolerant on output power pins Applications  STB satellite receivers  TV satellite receivers  PC card satellite receivers Description Intended for analog and digital satellite receivers/Sat-TV and Sat-PC cards, the LNBH25S is a monolithic voltage regulator and interface IC, assembled in QFN24L (4x4 mm) specifically designed to provide 13/18 V power supply and 22 kHz tone signaling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count and low power dissipation together with a simple design and I²C standard interface. Table 1: Device summary Order code Package Packing LNBH25SPQR QFN24L (4x4) Tape and reel

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Contents LNBH25S 2/37 DocID026736 Rev 3 Contents 1 Block diagram .................................................................................. 6 2 Application information .................................................................. 7 2.1 DiSEqC data encoding (DSQIN pin) ................................................. 7 2.2 Data encoding by external 22 kHz tone TTL signal ........................... 7 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin ...................................................................................................... 8 2.4 LPM (low power mode) ..................................................................... 8 2.5 DiSEqC 2.0 implementation .............................................................. 8 2.6 Output current limit selection ............................................................. 9 2.7 Output voltage selection .................................................................... 9 2.8 Diagnostic and protection functions .................................................. 9 2.9 Surge protections and TVS diodes .................................................... 9 2.10 FLT (fault flag) ................................................................................. 10 2.11 VMON (output voltage diagnostic) .................................................. 10 2.12 TMON (22 kHz tone diagnostic) ...................................................... 10 2.13 TDET (22 kHz tone detection) ......................................................... 10 2.14 IMON (minimum output current diagnostic) ..................................... 10 2.15 PDO (overcurrent detection on output pull-down stage) ................. 11 2.16 Power-on I²C interface reset and undervoltage lockout .................. 11 2.17 PNG (input voltage minimum detection) .......................................... 11 2.18 ISW (inductor switching current limit) .............................................. 11 2.19 COMP (boost capacitors and inductor) ........................................... 11 2.20 OLF (overcurrent and short-circuit protection and diagnostic) ........ 12 2.21 OTF (thermal protection and diagnostic) ......................................... 12 3 Pin configuration ........................................................................... 13 4 Maximum ratings ........................................................................... 15 5 Typical application circuits ........................................................... 16 6 I²C bus interface ............................................................................ 19 6.1 Data validity..................................................................................... 19 6.2 Start and stop condition .................................................................. 19 6.3 Byte format ...................................................................................... 19 6.4 Acknowledge ................................................................................... 19

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LNBH25S Contents DocID026736 Rev 3 3/37 6.5 Transmission without acknowledge ................................................. 19 7 I²C interface protocol .................................................................... 21 7.1 Write mode transmission ................................................................. 21 7.2 Read mode transmission ................................................................ 21 7.3 Data registers .................................................................................. 23 7.4 Status registers ............................................................................... 26 8 Electrical characteristics .............................................................. 28 9 Package information ..................................................................... 33 9.1 QFN24L (4x4 mm) package information ......................................... 34 10 Revision history ............................................................................ 36

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List of tables LNBH25S 4/37 DocID026736 Rev 3 List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description ............................................................................................................................ 13 Table 3: Absolute maximum ratings ......................................................................................................... 15 Table 4: Thermal data ............................................................................................................................... 15 Table 5: DiSEqC 1.x bill of material .......................................................................................................... 16 Table 6: DiSEqC 2.x bill of material .......................................................................................................... 18 Table 7: Data 1 (read/write register. Register address = 0X2) ................................................................. 23 Table 8: Data 2 (read/write register. Register address = 0X3) ................................................................. 23 Table 9: Data 3 (read/write register. Register address = 0X4) ................................................................. 24 Table 10: Data 4 (read/write register. Register address = 0X5) ............................................................... 25 Table 11: Status 1 (read register. Register address = 0X0) ..................................................................... 26 Table 12: Status 2 (read register. Register address = 0X1) ..................................................................... 27 Table 13: Electrical characteristics ........................................................................................................... 28 Table 14: Output voltage selection table (data1 register, write mode) ..................................................... 30 Table 15: I²C electrical characteristics ...................................................................................................... 30 Table 16: Address pin characteristics ....................................................................................................... 31 Table 17: Output voltage diagnostic (VMON bit, status 1 register) characteristics .................................. 31 Table 18: Output current diagnostic (IMON bit, status 2 register) characteristics .................................... 31 Table 19: 22 kHz tone diagnostic (TMON bit, status 2 register) characteristics....................................... 32 Table 20: QFN24L (4x4 mm) mechanical data ......................................................................................... 35 Table 21: Document revision history ........................................................................................................ 36

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LNBH25S List of figures DocID026736 Rev 3 5/37 List of figures Figure 1: Block diagram .............................................................................................................................. 6 Figure 2: Tone enable and disable timing (using external waveform) ........................................................ 8 Figure 3: Tone enable and disable timing (using envelope signal) ............................................................ 8 Figure 4: Surge protection circuit .............................................................................................................. 10 Figure 5: Pin connection (top view) .......................................................................................................... 13 Figure 6: DiSEqC 1.x application circuit ................................................................................................... 16 Figure 7: DiSEqC 2.x application circuit ................................................................................................... 17 Figure 8: Data validity on the I²C bus ....................................................................................................... 20 Figure 9: Timing diagram of I²C bus ......................................................................................................... 20 Figure 10: Acknowledge on the I²C bus.................................................................................................... 20 Figure 11: Example of writing procedure starting with first data address 0X2 ......................................... 21 Figure 12: Example of reading procedure starting with first status address 0X0 ..................................... 22 Figure 13: QFN24L (4x4 mm) package outline ........................................................................................ 34 Figure 14: QFN24L (4x4 mm) recommended footprint ............................................................................. 35

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Block diagram LNBH25S 6/37 DocID026736 Rev 3 1 Block diagram Figure 1: Block diagram

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LNBH25S Application information DocID026736 Rev 3 7/37 2 Application information This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates voltages (VUP) which let the integrated LDO post-regulator (generating13 V/18 V LNB output voltages plus 22 kHz DiSEqC™ tone) work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP-VOUT = 1 V typ.). The LDO power dissipation can be reduced when 22 kHz tone output is disabled by setting the LPM bit to “1” see Section 2.4: "LPM (low power mode)". The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typ.). The step-up converter soft-start function reduces the inrush current during startup. SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. switch from 0 to 18 V. 2.1 DiSEqC data encoding (DSQIN pin) The internal 22 kHz tone generator is factory trimmed in accordance with DiSEqC standards, and can be active in 3 different ways: 1. By an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case I²C tone control bits have to be set: EXTM = TEN = 1. 2. By an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case I²C tone control bits must be set: EXTM = 0 and TEN = 1. 3. Through TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled high and EXTM bit is set to “0”. Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC data transmission, the LPM bit has to be set to “0” see Section 2.4: "LPM (low power mode)". 2.2 Data encoding by external 22 kHz tone TTL signal In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”. The DSQIN is a logic input pin, which activates the 22 kHz tone to the VOUT pin, by using the LNBH25S integrated tone generator. The output tone waveforms are internally controlled by the LNBH25S tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal to the DSQIN pin, the EXTM and TEN bits have to be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH25S activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired, refer to Figure 2: "Tone enable and disable timing (using external waveform)".

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Application information LNBH25S 8/37 DocID026736 Rev 3 Figure 2: Tone enable and disable timing (using external waveform) 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC envelope source is available, the internal 22 kHz generator can be activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and TEN = 1. In this manner, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high, the internal control circuit activates the 22 kHz tone output. The 22 kHz tone on the VOUT pin is active with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired, refer to Figure 3: "Tone enable and disable timing (using envelope signal)". Figure 3: Tone enable and disable timing (using envelope signal) 2.4 LPM (low power mode) In order to reduce the total power loss, the LNBH25S is provided with the LPM I²C bit that can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long time periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not requested (no 22 kHz tone output is present); the drop voltage across the integrated LDO regulator (VUP-VOUT) is reduced to 0.6 V typ. and, consequently, the power loss inside the LNBH25S linear regulator is reduced as well. For example: at 500 mA load, LPM=1 allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM bit to “0” before starting the 22 kHz DiSEqC data transmission; at this condition the drop voltage across the LDO is kept to 1 V typ. LPM=0 if the LPM function is not used. 2.5 DiSEqC 2.0 implementation The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing. The input pin (DETIN) has to be AC coupled to the DiSEqC bus, and extracted PWK data is available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus hardware requirements, an output RL filter is needed. In order to avoid 22 kHz waveform ~ 6 µs 15 µs ~ 60 µs DSQIN Tone output GIPG0907141158LM

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LNBH25S Application information DocID026736 Rev 3 9/37 distortion during tone transmission, the LNBH25S is provided with the BPSW pin to be connected to an external transistor, which allows the output RL filter to be bypassed in DiSEqC 2.x applications while in transmission mode. Before starting tone transmission, TEN bit has to be set to “1” and after ending tone transmission, TEN bit has to be set to “0”. 2.6 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation: with ISET=0 with ISET=1 see ISET bit description in Table 9: "Data 3 (read/write register. Register address = 0X4)", where RSEL is the resistor connected between ISEL and GND expressed in kΩ and ILIM(typ.) is the typical current limit threshold expressed in mA. ILIM can be set up to 1 A. 2.7 Output voltage selection The linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 bits of an internal data 1 register, see Section 7.3: "Data registers" for exact programmable values. Register writing is accessible via I²C bus. 2.8 Diagnostic and protection functions The LNBH25S has 8 diagnostic internal functions provided by I²C bus, by reading 8 bits on two status registers (in read mode). All the diagnostic bits are, in normal operation (that is no failure detected), set to low. Two diagnostic bits are dedicated to the overtemperature and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum load current (IMON), to external voltage source presence on the VOUT pin (PDO), to the input voltage power not good function (PNG) and to the 22 kHz tone presence on the DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is latched to “1” until relevant cause is removed and a new register reading operation is performed. 2.9 Surge protections and TVS diodes The LNBH25S device is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect the STB output circuits where the LNBH25S and other devices are electrically connected to the antenna cable. I LIM (typ.) = 13915 RSEL1.111 I LIM (typ.) = 6808 RSEL1.068

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June 24, 2020

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