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M27C1001-10C1

hot M27C1001-10C1

M27C1001-10C1

For Reference Only

Part Number M27C1001-10C1
Manufacturer STMicroelectronics
Description IC OTP 1MBIT 100NS 32PLCC
Datasheet M27C1001-10C1 Datasheet
Package 32-LCC (J-Lead)
In Stock 475 piece(s)
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M27C1001-10C1

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M27C1001-10C1 Specifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - Memory
Datasheet M27C1001-10C1 Datasheet
Package32-LCC (J-Lead)
Series-
Memory TypeNon-Volatile
Memory FormatEPROM
TechnologyEPROM - OTP
Memory Size1Mb (128K x 8)
Access Time100ns
Memory InterfaceParallel
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature0°C ~ 70°C (TA)
Mounting TypeSurface Mount
Package / Case32-LCC (J-Lead)
Supplier Device Package32-PLCC (11.35x13.89)

M27C1001-10C1 Datasheet

Page 1

Page 2

1/17June 2002 M27C1001 1 Mbit (128Kb x8) UV EPROM and OTP EPROM ■ 5V ± 10% SUPPLY VOLTAGE in READ OPERATION ■ ACCESS TIME: 35ns ■ LOW POWER CONSUMPTION: – Active Current 30mA at 5Mhz – Standby Current 100µA ■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V ■ PROGRAMMING TIME: 100µs/word ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 05h DESCRIPTION The M27C1001 is a 1 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for micro- processor systems requiring large programs and is organized as 131,072 words of 8 bits. The FDIP32W (window ceramic frit-seal package) and the LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C1001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. Figure 1. Logic Diagram AI00710B 17 A0-A16 P Q0-Q7 VPPVCC M27C1001 G E VSS 8 1 32 32 1 FDIP32W (F) PDIP32 (B) PLCC32 (C) TSOP32 (N) 8 x 20 mm LCCC32W (L)

Page 3

M27C1001 2/17 Figure 2B. LCC Connections AI00712 N C A8 A10 Q 5 17 A1 A0 Q0 Q 1 Q 2 Q 3 Q 4 A7 A4 A3 A2 A6 A5 9 P A9 1 A 1 6 A11 A13 A 1 2 Q7 32 V P P V C C M27C1001 A 1 5 A14 Q 6 G E 25 V S S Figure 2A. DIP Connections A1 A0 Q0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 Q7 A14 A11 G E Q5Q1 Q2 Q3VSS Q4 Q6 NC PA16 A12 VPP VCC A15 AI00711 M27C1001 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2C. TSOP Connections A1 A0 Q0 A7 A4 A3 A2 A6 A5 A13 A10 A8 A9 Q7 A14 A11 G E Q5 Q1 Q2 Q3 Q4 Q6 NC P A16 A12 VPP VCC A15 AI01151B M27C1001 (Normal) 8 1 9 16 17 24 25 32 VSS Table 1. Signal Names A0-A16 Address Inputs Q0-Q7 Data Outputs E Chip Enable G Output Enable P Program VPP Program Supply VCC Supply Voltage VSS Ground NC Not Connected Internally

Page 4

3/17 M27C1001 Table 2. Absolute Maximum Ratings (1) Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi- tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual- ity documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Note: X = VIH or VIL, VID = 12V ± 0.5V. Table 4. Electronic Signature Symbol Parameter Value Unit TA Ambient Operating Temperature (3) –40 to 125 °C TBIAS Temperature Under Bias –50 to 125 °C TSTG Storage Temperature –65 to 150 °C VIO (2) Input or Output Voltage (except A9) –2 to 7 V VCC Supply Voltage –2 to 7 V VA9 (2) A9 Voltage –2 to 13.5 V VPP Program Supply Voltage –2 to 14 V Mode E G P A9 VPP Q7-Q0 Read VIL VIL X X VCC or VSS Data Out Output Disable VIL VIH X X VCC or VSS Hi-Z Program VIL VIH VIL Pulse X VPP Data In Verify VIL VIL VIH X VPP Data Out Program Inhibit VIH X X X VPP Hi-Z Standby VIH X X X VCC or VSS Hi-Z Electronic Signature VIL VIL VIH VID VCC Codes Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 0 0 0 0 0 1 0 1 05h

Page 5

M27C1001 4/17 DEVICE OPERATION The operating modes of the M27C1001 are listed in the Operating Modes table. A single power sup- ply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C1001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. Assuming that the ad- dresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of tGLQV from the falling edge of G, assuming that E has been low and the addresses have been sta- ble for at least tAVQV-tGLQV. Standby Mode The M27C1001 has a standby mode which reduc- es the supply current from 30mA to 100µA. The M27C1001 is placed in the standby mode by ap- plying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high imped- ance state, independent of the G input. Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times ≤ 10ns ≤ 20ns Input Pulse Voltages 0 to 3V 0.4V to 2.4V Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V Figure 3. AC Testing Input Output Waveform AI01822 3V High Speed 0V 1.5V 2.4V Standard 0.4V 2.0V 0.8V Figure 4. AC Testing Load Circuit AI01823B 1.3V OUT CL CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance 3.3kΩ 1N914 DEVICE UNDER TEST Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Note: 1. Sampled only, not 100% tested. Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance VIN = 0V 6 pF COUT Output Capacitance VOUT = 0V 12 pF

Page 6

5/17 M27C1001 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA ICC Supply Current E = VIL, G = VIL, IOUT = 0mA, f = 5MHz 30 mA ICC1 Supply Current (Standby) TTL E = VIH 1 mA ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA IPP Program Current VPP = VCC 10 µA VIL Input Low Voltage –0.3 0.8 V VIH (2) Input High Voltage 2 VCC + 1 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage TTL IOH = –400µA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.7V V Symbol Alt Parameter Test Condition M27C1001 Unit -35 (3) -45 -60 -70 Min Max Min Max Min Max Min Max tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 35 45 60 70 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 35 45 60 70 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 25 25 30 35 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 25 0 25 0 30 0 30 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 25 0 25 0 30 0 30 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 0 0 ns Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the prima- ry device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device.

Page 7

M27C1001 6/17 Figure 5. Read Mode AC Waveforms AI00713B tAXQX tEHQZ A0-A16 E G Q0-Q7 tAVQV tGHQZ tGLQV tELQV VALID Hi-Z VALID Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70°C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Symbol Alt Parameter Test Condition M27C1001 Unit-80 -90 -10 -12/-15/ -20/-25 Min Max Min Max Min Max Min Max tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL 80 90 100 120 ns tELQV tCE Chip Enable Low to Output Valid G = VIL 80 90 100 120 ns tGLQV tOE Output Enable Low to Output Valid E = VIL 40 45 50 60 ns tEHQZ (2) tDF Chip Enable High to Output Hi-Z G = VIL 0 30 0 30 0 30 0 40 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z E = VIL 0 30 0 30 0 30 0 40 ns tAXQX tOH Address Transition to Output Transition E = VIL, G = VIL 0 0 0 0 ns System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three seg- ments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceram- ic capacitor be used on every device between VCC and VSS. This should be a high frequency capaci- tor of low inherent inductance and should be placed as close to the device as possible. In addi- tion, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devic- es. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces.

Page 8

7/17 M27C1001 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP. 2. Sampled only, not 100% tested. Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA ICC Supply Current 50 mA IPP Program Current E = VIL 50 mA VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1mA 0.4 V VOH Output High Voltage TTL IOH = –400µA 2.4 V VID A9 Voltage 11.5 12.5 V Symbol Alt Parameter Test Condition Min Max Unit tAVPL tAS Address Valid to Program Low 2 µs tQVPL tDS Input Valid to Program Low 2 µs tVPHPL tVPS VPP High to Program Low 2 µs tVCHPL tVCS VCC High to Program Low 2 µs tELPL tCES Chip Enable Low to Program Low 2 µs tPLPH tPW Program Pulse Width 95 105 µs tPHQX tDH Program High to Input Transition 2 µs tQXGL tOES Input Transition to Output Enable Low 2 µs tGLQV tOE Output Enable Low to Output Valid 100 ns tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns tGHAX tAH Output Enable High to Address Transition 0 ns Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C1001 are in the '1' state. Data is introduced by selectively program- ming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposition to ultravio- let light (UV EPROM). The M27C1001 is in the programming mode when VPP input is at 12.75V, E is at VIL and P is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the ad- dress and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V.

Page 9

M27C1001 8/17 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed, with a guaranteed margin, in a typical time of 13 seconds. Program- ming with PRESTO II involves in applying a se- quence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During pro- gramming and verify operation, a MARGIN MODE circuit is automatically activated in order to guar- antee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary mar- gin to each programmed cell. Program Inhibit Programming of multiple M27C1001s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including G of the parallel M27C1001 may be common. A TTL low level pulse applied to a M27C1001's P input, with E low and VPP at 12.75V, will program that M27C1001. A high level E input inhibits the other M27C1001s from being programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. Figure 6. Programming and Verify Modes AC Waveforms tAVPL VALID AI00714 A0-A16 Q0-Q7 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 7. Programming Flowchart AI00715C n = 0 Last Addr VERIFY P = 100µs Pulse ++n = 25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V YES NO YES NO YES NO

Page 10

9/17 M27C1001 Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C am- bient temperature range that is required when pro- gramming the M27C1001. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C1001, with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device out- puts by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C1001, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C1001 is such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluo- rescent lighting could erase a typical M27C1001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C1001 is to be exposed to these types of lighting conditions for extended pe- riods of time, it is suggested that opaque labels be put over the M27C1001 window to prevent unin- tentional erasure. The recommended erasure pro- cedure for the M27C1001 is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dos- age is approximately 15 to 20 minutes using an ul- traviolet lamp with 12000 µW/cm2 power rating. The M27C1001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure.

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Jorg*****rsen

November 26, 2019

Item sent as described. Showed up quickly. Worked as it said and would recommend again.

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August 6, 2019

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July 23, 2019

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July 23, 2019

Items arrived well pakaged, reasonable postage and as described. Top seller

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May 17, 2019

The order has arrived ahead of time, we appreciate it very much!! Thanks

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May 14, 2019

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May 10, 2019

Great price. Worked well for my needs.

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March 31, 2019

Very supportive of my small orders, but very glad easy to work with. Hard to see how it could be any more efficient!

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March 13, 2019

EXACTLY what I was looking for -- one piece with a low forward voltage drop to isolate some DC power sources. They work fantastic!

Walk*****avis

March 9, 2019

The fastest shipping I've seen yet

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