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MAX1297ACEG+T

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MAX1297ACEG+T

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Part Number MAX1297ACEG+T
Manufacturer Maxim Integrated
Description IC ADC 12BIT 265KSPS 24-QSOP
Datasheet MAX1297ACEG+T Datasheet
Package 24-SSOP (0.154", 3.90mm Width)
In Stock 7,200 piece(s)
Unit Price $ 9.3269 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # MAX1297ACEG+T (Data Acquisition - Analog to Digital Converters (ADC)) is manufactured by Maxim Integrated and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MAX1297ACEG+T Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Data Acquisition - Analog to Digital Converters (ADC)
Datasheet MAX1297ACEG+TDatasheet
Package24-SSOP (0.154", 3.90mm Width)
Series-
Number of Bits12
Sampling Rate (Per Second)265k
Number of Inputs1, 2
Input TypePseudo-Differential, Single Ended
Data InterfaceParallel
ConfigurationMUX-S/H-ADC
Ratio - S/H:ADC1:1
Number of A/D Converters1
ArchitectureSAR
Reference TypeExternal, Internal
Voltage - Supply, Analog2.7 V ~ 3.6 V
Voltage - Supply, Digital2.7 V ~ 3.6 V
Features-
Operating Temperature0°C ~ 70°C
Package / Case24-SSOP (0.154", 3.90mm Width)
Supplier Device Package24-QSOP
Mounting Type-

MAX1297ACEG+T Datasheet

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General Description The MAX1295/MAX1297 low-power, 12-bit analog-to- digital converters (ADCs) feature a successive-approxi- mation ADC, automatic power-down, fast wake-up (2µs), an on-chip clock, +2.5V internal reference, and a high-speed 12-bit parallel interface. They operate with a single +2.7V to +3.6V analog supply. Power consumption is only 5.4mW at the maximum sampling rate of 265ksps. Two software-selectable power-down modes enable the MAX1295/MAX1297 to be shut down between conversions; accessing the par- allel interface returns them to normal operation. Powering down between conversions can reduce sup- ply current below 10µA at lower sampling rates. Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differen- tial operation. In single-ended mode, the MAX1295 has six input channels and the MAX1297 has two (three input channels and one input channel, respectively, when in pseudo-differential mode). Excellent dynamic performance and low power, combined with ease of use and small package size, make these con- verters ideal for battery-powered and data-acquisition applications or for other circuits with demanding power- consumption and space requirements. The MAX1295/MAX1297 tri-states INT when CS goes high. Refer to MAX1265/MAX1267 if tri-stating INT is not desired. The MAX1295 is offered in a 28-pin QSOP package, while the MAX1297 comes in a 24-pin QSOP. For pin-compati- ble +5V, 12-bit versions, refer to the MAX1294/MAX1296 data sheet. Applications Industrial Control Systems Data Logging Energy Management Patient Monitoring Data-Acquisition Systems Touchscreens Features ♦ 12-Bit Resolution, ±0.5 LSB Linearity ♦ +3V Single-Supply Operation ♦ Internal +2.5V Reference ♦ Software-Configurable Analog Input Multiplexer 6-Channel Single-Ended/ 3-Channel Pseudo-Differential (MAX1295) 2-Channel Single-Ended/ 1-Channel Pseudo-Differential (MAX1297) ♦ Software-Configurable Unipolar/Bipolar Analog Inputs ♦ Low Current 1.9mA (265ksps) 1.0mA (100ksps) 400µA (10ksps) 2µA (Shutdown) ♦ Internal 3MHz Full-Power Bandwidth Track/Hold ♦ Parallel 12-Bit Interface ♦ Small Footprint 28-Pin QSOP (MAX1295) 24-Pin QSOP (MAX1297) M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface ________________________________________________________________ Maxim Integrated Products 1 19-1530; Rev 3; 12/02 EVALU ATION KIT AVAIL ABLE Ordering Information Pin Configurations Typical Operating Circuits appear at end of data sheet. 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D10 D11 VDD REF REFADJ GND CS COM CH0 CH1 CH2 CH3 CH4 CH5 CLK WR RD INT D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 QSOP TOP VIEW MAX1295 Pin Configurations continued at end of data sheet. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. PART TEMP RANGE PIN-PACKAGE INL (LSB) MAX1295ACEI 0°C to +70°C 28 QSOP ±0.5 MAX1295BCEI 0°C to +70°C 28 QSOP ±1 MAX1295AEEI -40°C to +85°C 28 QSOP ±0.5 MAX1295BEEI -40°C to +85°C 28 QSOP ±1 MAX1297ACEG 0°C to +70°C 24 QSOP ±0.5 MAX1297BCEG 0°C to +70°C 24 QSOP ±1 MAX1297AEEG -40°C to +85°C 24 QSOP ±0.5 MAX1297BEEG -40°C to +85°C 24 QSOP ±1

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to GND..............................................................-0.3V to +6V CH0–CH5, COM to GND............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0–D11, INT) to GND.......-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW 28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW Operating Temperature Ranges MAX1295_C_ _ /MAX1297_C_ _ ........................0°C to +70°C MAX1295_E_ _ /MAX1297_E_ _ ......................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C External acquisition or external clock mode Internal acquisition/internal clock mode MAX129_A External acquisition/internal clock mode External clock mode -3dB rolloff SINAD > 68dB fIN = 125kHz (Note 4) fIN1 = 49kHz, fIN2 = 52kHz MAX129_B No missing codes over temperature CONDITIONS ns50Aperture Delay ns625tACQTrack/Hold Acquisition Time 3.2 3.6 4.1 2.5 3.0 3.5 µs 3.3 tCONVConversion Time (Note 5) MHz3Full-Power Bandwidth kHz250Full-Linear Bandwidth dB-78Channel-to-Channel Crosstalk dB76IMDIntermodulation Distortion dB80SFDRSpurious-Free Dynamic Range dB Total Harmonic Distortion (including 5th-order harmonic) -78THD ±0.5 INLRelative Accuracy (Note 2) Bits12RESResolution dB67 70SINADSignal-to-Noise Plus Distortion LSB±0.2 Channel-to-Channel Offset Matching ppm/°C±2.0Gain Temperature Coefficient LSB ±1 LSB±1DNLDifferential Nonlinearity LSB±4Offset Error LSB±4Gain Error (Note 3) UNITSMIN TYP MAXSYMBOLPARAMETER Internal acquisition/internal clock mode External acquisition or external clock mode <200 ps <50 Aperture Jitter MHz0.1 4.8fCLKExternal Clock Frequency %30 70Duty Cycle DC ACCURACY (Note 1) DYNAMIC SPECIFICATIONS (fIN(sine-wave) = 50kHz, VIN = 2.5VP-P, 265ksps, external fCLK = 4.8MHz, bipolar input mode) CONVERSION RATE

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) CONDITIONS UNITSMIN TYP MAXSYMBOLPARAMETER 0 to 0.5mA output load To power down the internal reference For small adjustments On/off-leakage-current, VIN = 0 or VDD Unipolar, VCOM = 0 Bipolar, VCOM = VREF / 2 V1.0 VDD + 50mV VREFREF Input Voltage Range µF4.7 10Capacitive Bypass at REF µF0.01 1Capacitive Bypass at REFADJ mV/mA0.2Load Regulation (Note 7) VVDD - 1REFADJ High Threshold mV±100REFADJ Input Range mA15REF Short-Circuit Current V2.49 2.5 2.51REF Output Voltage pF12CINInput Capacitance µA±0.01 ±1Multiplexer Leakage Current V Analog Input Voltage Range Single-Ended and Differential (Note 6) 0 VREF -VREF/2 +VREF/2 VIN CS = VDD ISOURCE = 1mA ISINK = 1.6mA VIN = 0 or VDD VREF = 2.5V, fSAMPLE = 265ksps µA±0.1 ±1ILEAKAGEThree-State Leakage Current VVDD - 0.5VOHOutput Voltage High V0.4VOLOutput Voltage Low pF15CINInput Capacitance µA±0.1 ±1IINInput Leakage Current mV200VHYSInput Hysteresis V0.8VILInput Voltage Low V2.0VIHInput Voltage High µA 200 300 IREFREF Input Current CS = VDD V2.7 3.6VDDAnalog Supply Voltage pF15COUTThree-State Output Capacitance Internal reference 2.5 2.8 ppm/°C±20TCREFREF Temperature Coefficient Shutdown mode 2 External reference 1.9 2.3 0.9 1.2Positive Supply Current Shutdown mode 2 10 µA Power-Supply Rejection PSR VDD = 2.7V to 3.6V, full-scale input ±0.4 ±0.9 mV IDD 0.5 0.8 mA Operating mode, fSAMPLE = 265ksps Internal reference External reference Standby mode CONVERSION RATE (continued)ANALOG INPUTS INTERNAL REFERENCE EXTERNAL REFERENCE AT REF DIGITAL INPUTS AND OUTPUTS POWER REQUIREMENTS

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 4 _______________________________________________________________________________________ tTR 20 70 nsCLOAD = 20pF, Figure 1RD Rise to Output Disable WR to CLK Fall Setup Time tCWS 40 ns nsCLK Pulse Width High nsCLK Period tCH 40 RD Fall to Output Data Valid tDO 20 70 ns RD Fall to INT High Delay tINT1 100 ns CS Fall to Output Data Valid tDO2 110 ns CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 tCP 208 CLK Pulse Width Low tCL 40 ns Data Valid to WR Rise Time tDS 40 ns WR Rise to Data Valid Hold Time tDH 0 ns CLK Fall to WR Hold Time tCWH 40 ns CS to CLK or WR Setup Time tCSWS 60 ns CLK or WR to CS Hold Time tCSWH 0 ns CS Pulse Width tCS 100 ns WR Pulse Width (Note 8) tWR 60 ns tTC 20 100 nsCLOAD = 20pF, Figure 1 PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS CS Rise to Output Disable Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 3: Offset nulled. Note 4: On channel is grounded; sine wave applied to off channels. Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD. Note 7: External load should not change during conversion for specified accuracy. Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion. TIMING CHARACTERISTICS (VDD = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) 6kΩ 3kΩ DOUT DOUT VDD a) HIGH-Z TO VOH AND VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL CLOAD 20pF CLOAD 20pF Figure 1. Load Circuits for Enable/Disable Times

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 5 -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 20001000 3000 4000 5000 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE M A X 1 2 9 5 /7 to c0 1 DIGITAL OUTPUT CODE IN L (L S B ) -0.5 -0.2 -0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 20001000 3000 4000 5000 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE M A X 1 2 9 5 /7 to c0 2 DIGITAL OUTPUT CODE D N L (L S B ) 1.80 1.90 1.85 2.00 1.95 2.05 2.10 2.7 3.0 3.3 3.6 SUPPLY CURRENT vs. SUPPLY VOLTAGE M A X 1 2 9 5 /7 t o c0 3 VDD (V) I D D ( m A ) RL = ∞ CODE = 101010100000 1.6 1.8 1.7 2.0 1.9 2.1 2.2 -40 10-15 35 60 85 SUPPLY CURRENT vs. TEMPERATURE M A X 1 2 9 5 /7 t o c0 4 TEMPERATURE (°C) I D D ( m A ) RL = ∞ CODE = 101010100000 880 890 910 900 920 930 STANDBY CURRENT vs. SUPPLY VOLTAGE M A X 1 2 9 5 /7 t o c0 5 VDD (V) S TA N D B Y I D D ( µA ) 2.7 3.33.0 3.6 880 890 910 900 920 930 STANDBY CURRENT vs. TEMPERATURE M A X 1 2 9 5 /7 t o c0 6 TEMPERATURE (°C) S TA N D B Y I D D ( µA ) -40 10-15 35 8560 0.50 1.00 0.75 1.25 1.50 2.7 3.0 3.3 3.6 POWER-DOWN CURRENT vs. SUPPLY VOLTAGE M A X 1 2 9 5 /7 t o c0 7 VDD (V) P O W ER -D O W N I D D ( µA ) 0.8 0.9 1.0 1.1 1.2 POWER-DOWN CURRENT vs. TEMPERATURE M A X 1 2 9 5 /7 t o c0 8 TEMPERATURE (°C) P O W ER -D O W N I D D ( µA ) -40 35-15 10 60 85 Typical Operating Characteristics (VDD = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) 0.1 1k 100k101 100 10k 1M SUPPLY CURRENT vs. SAMPLE FREQUENCY M A X 1 2 9 5 /7 to c0 2 a fSAMPLE (Hz) I D D ( µA ) 0 10 100 1000 10,000 WITH EXTERNAL REFERENCE WITH INTERNAL REFERENCE

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 6 _______________________________________________________________________________________ Typical Operating Characteristics (continued) (VDD = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25°C, unless otherwise noted.) M A X 1 2 9 5 /7 to c1 0 V R EF ( m A ) 85 2.48 2.49 2.51 2.50 2.52 2.53 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE TEMPERATURE (°C) -40 603510-15 -2.5 -2.0 -1.0 -1.5 -0.5 0 OFFSET ERROR vs. SUPPLY VOLTAGE M A X 1 2 9 5 /7 t o c1 1 VDD (V) O FF S ET E R R O R ( LS B ) 2.7 3.33.0 3.6 -2.5 -1.5 -2.0 -0.5 -1.0 0 0.5 -40 10-15 35 60 85 OFFSET ERROR vs. TEMPERATURE M A X 1 2 9 5 /7 t o c1 2 TEMPERATURE (°C) O FF S ET E R R O R ( LS B ) -3.0 -1.0 -2.0 0 1.0 2.7 3.33.0 3.6 GAIN ERROR vs. SUPPLY VOLTAGE M A X 1 2 9 5 /7 t o c1 3 VDD (V) G A IN E R R O R ( LS B ) -2.0 -1.5 -0.5 -1.0 0 0.5 GAIN ERROR vs. TEMPERATURE M A X 1 2 9 5 /7 t o c1 4 TEMPERATURE (°C) G A IN E R R O R ( LS B ) -40 10-15 35 60 85 M A X 1 2 9 5 /7 to c0 9 V R EF (V ) 3.6 2.48 2.49 2.51 2.50 2.52 2.53 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE VDD (V) 2.7 3.33.0 -140 -120 -100 -80 -60 -40 -20 0 20 0 200 400 600 800 1000 FFT PLOT M A X 1 2 9 5 /7 to c1 5 FREQUENCY (kHz) A M P LI TU D E (d B ) VDD = 3V fIN = 50kHz fSAMPLE = 250ksps

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 7 Pin Description D01010 INT1111 RD1212 WR1313 CLK1414 D466 D377 D288 D199 D555 D644 1 D733 D822 D91 Three-State Digital I/O Line (D0) INT goes low when the conversion is complete and output data is ready. Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the data bus. Active-Low Write Select. When CS is low in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conver- sion cycle. When CS is low in external acquisition mode, the first rising edge on WR ends acquisition and starts a conversion. Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock. In internal clock mode, connect this pin to either VDD or GND. Three-State Digital I/O Line (D4) Three-State Digital I/O Line (D3) Three-State Digital I/O Line (D2) Three-State Digital I/O Line (D1) Three-State Digital I/O Line (D5) Three-State Digital I/O Line (D6) Three-State Digital I/O Line (D7) Three-State Digital Output (D8) Three-State Digital Output (D9) GND1923 REFADJ2024 CH2—19 CH11620 CH01721 COM1822 CH3—18 CH4—17 CH5—16 CS1515 Analog and Digital Ground Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01µF capacitor. When using an external reference, connect REFADJ to VDD to disable the internal bandgap reference. Analog Input Channel 2 Analog Input Channel 1 Analog Input Channel 0 Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and must be stable to ±0.5 LSB during conversion. Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high impedance. PIN MAX1297MAX1295 NAME FUNCTION

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface 8 _______________________________________________________________________________________ Pin Description (continued) PIN MAX1297 REF2125 MAX1295 NAME Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to GND when using the internal reference. FUNCTION 26 22 VDD Analog +2.7V to +3.6V Power Supply. Bypass with a 0.1µF capacitor to GND. 27 23 D11 Three-State Digital Output (D11) 28 24 D10 Three-State Digital Output (D10) _______________Detailed Description Converter Operation The MAX1295/MAX1297 ADCs use a successive- approximation (SAR) conversion technique and an input track/hold (T/H) stage to convert an analog input signal to a 12-bit digital output. This output format provides an easy interface to standard microprocessors (µPs). Figure 2 shows the simplified internal architecture of the MAX1295/MAX1297. Single-Ended and Pseudo-Differential Operation The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuit in Figure 3. In single-ended mode, IN+ is internally switched to channels CH0–CH5 for the MAX1295 (Figure 3a) and to CH0–CH1 for the MAX1297 (Figure 3b), while IN- is switched to COM (Table 2). In differen- tial mode, IN+ and IN- are selected from analog input pairs (Table 3) and are internally switched to either of T/H THREE-STATE, BIDIRECTIONAL I/O INTERFACE 12 17kΩ 12 SUCCESSIVE- APPROXIMATION REGISTER CHARGE REDISTRIBUTION 12-BIT DAC CLOCK ANALOG INPUT MULTIPLEXER CONTROL LOGIC & LATCHES REF REFADJ 1.22V REFERENCE D0–D11 12-BIT DATA BUS (CH5) (CH4) (CH3) (CH2) CH1 CH0 COM CLK CS WR RD INT ( ) ARE FOR MAX1295 ONLY. VDD GND MAX1295 MAX1297 AV = 2.05 COMP Figure 2. Simplified Functional Diagram of 6-/2-Channel MAX1295/MAX1297

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M A X 1 2 9 5 /M A X 1 2 9 7 265ksps, +3V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface _______________________________________________________________________________________ 9 BIT PD1, PD0 0 D7, D6 PD1 and PD0 select the various clock and power-down modes. Full Power-Down Mode. Clock mode is unaffected. D5 ACQMOD ACQMOD = 0: Internal Acquisition Mode ACQMOD = 1: External Acquisition Mode NAME FUNCTIONAL DESCRIPTION 0 10 Standby Power-Down Mode. Clock mode is unaffected. 0 11 Normal Operation Mode. External clock mode selected. 1 Normal Operation Mode. Internal clock mode selected. D4 SGL/DIF SGL/DIF = 0: Pseudo-Differential Analog Input Mode SGL/DIF = 1: Single-Ended Analog Input Mode In single-ended mode, input signals are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2, 4). D3 UNI/BIP UNI/BIP = 0: Bipolar Mode UNI/BIP = 1: Unipolar Mode In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. D2, D1, D0 A2, A1, A0 Address bits A2, A1, A0 select which of the 6/2 (MAX1295/MAX1297) channels is to be converted (Tables 2, 3). Table 1. Control-Byte Functional Description the analog inputs. This configuration is pseudo-differ- ential in that only the signal at IN+ is sampled. The return side (IN-) must remain stable within ±0.5 LSB (±0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from IN- (the selected input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplex- er switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node ZERO at the comparator’s positive input. The capacitive digital- to-analog converter (DAC) adjusts during the remain- Figure 3a. MAX1295 Simplified Input Structure Figure 3b. MAX1297 Simplified Input Structure CH0 CH1 CH2 CH3 CH4 CH5 COM CSWITCH TRACK T/H SWITCH RIN 800Ω CHOLD HOLD 12-BIT CAPACITIVE DAC VREF ZERO COMPARATOR – + 12pF SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3, AND CH4/CH5 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX CH0 CH1 COM CSWITCH TRACK T/H SWITCH RIN 800Ω CHOLD HOLD 12-BIT CAPACITIVE DAC VREF ZERO COMPARATOR – + 12pF SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR CH0/CH1 AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. INPUT MUX

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Har*****Pal

August 7, 2020

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July 4, 2020

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CRCW06035R10JNEC CRCW06035R10JNEC Vishay Dale, RES SMD 5.1 OHM 5% 1/10W 0603, 0603 (1608 Metric), - View
FW-38-05-G-D-500-120 FW-38-05-G-D-500-120 Samtec Inc., .050'' BOARD SPACERS, -, - View
DWM-12-59-G-S-500 DWM-12-59-G-S-500 Samtec Inc., .050" BOARD SPACERS, -, - View
ACC22DKMI-S1243 ACC22DKMI-S1243 Sullins Connector Solutions, CONN EDGE DUAL FMALE 44POS 0.100, -, - View
V72C15E150BL3 V72C15E150BL3 Vicor Corporation, CONVERTER MOD DC/DC 15V 150W, Quarter Brick, - View
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MAX1297ACEG+T

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