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MAX16025TE+T

hot MAX16025TE+T

MAX16025TE+T

For Reference Only

Part Number MAX16025TE+T
Manufacturer Maxim Integrated
Description IC SUPERVISORY CIRC DL 16TQFN
Datasheet MAX16025TE+T Datasheet
Package 16-WQFN Exposed Pad
In Stock 4412 piece(s)
Unit Price $ 2.5582 *
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MAX16025TE+T Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet MAX16025TE+T Datasheet
Package16-WQFN Exposed Pad
Series-
TypeSequencer
Number of Voltages Monitored2
OutputOpen Drain or Open Collector
ResetActive Low
Reset Timeout140 ms/Adjustable Minimum
Voltage - Threshold9 Selectable Threshold Combinations
Operating Temperature-40°C ~ 125°C (TA)
Mounting TypeSurface Mount
Package / Case16-WQFN Exposed Pad
Supplier Device Package16-TQFN (4x4)

MAX16025TE+T Datasheet

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General Description The MAX16025–MAX16030 are dual-/triple-/quad-volt- age monitors and sequencers that are offered in a small TQFN package. These devices offer enormous design flexibility as they allow fixed and adjustable thresholds to be selected through logic inputs and pro- vide sequence timing through small external capaci- tors. These versatile devices are ideal for use in a wide variety of multivoltage applications. As the voltage at each monitored input exceeds its respective threshold, its corresponding output goes high after a propagation delay or a capacitor-set time delay. When a voltage falls below its threshold, its respective output goes low after a propagation delay. Each detector circuit also includes its own enable input, allowing the power-good outputs to be shut off inde- pendently. The independent output for each detector is available with push-pull or open-drain configuration with the open-drain version capable of supporting volt- ages up to 28V, thereby allowing them to interface to shutdown and enable inputs of various DC-DC regula- tors. Each detector can operate independently as four separate supervisory circuits or can be daisy-chained to provide controlled power-supply sequencing. The MAX16025–MAX16030 also include a reset func- tion that deasserts only after all of the independently monitored voltages exceed their threshold. The reset timeout is internally fixed or can be adjusted externally. These devices are offered in a 4mm x 4mm TQFN package and are fully specified from -40°C to +125°C. Applications Multivoltage Systems DC-DC Supplies Servers/Workstations Storage Systems Networking/Telecommunication Equipment Features  2.2V to 28V Operating Voltage Range  Fixed Thresholds for 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V Systems  1.5% Accurate Adjustable Threshold Monitors Voltages Down to 0.5V  2.7% Accurate Fixed Thresholds Over Temperature  Fixed (140ms min)/Capacitor-Adjustable Delay Timing  Independent Open-Drain/Push-Pull Outputs  Enable Inputs for Each Monitored Voltage  9 Logic-Selectable Threshold Options  Manual Reset and Tolerance Select (5%/10%) Inputs  Small, 4mm x 4mm TQFN Package  Fully Specified from -40°C to +125°C M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits ________________________________________________________________ Maxim Integrated Products 1 TOP VIEW + 23 24 22 21 8 7 9 IN 1 IN 3 IN 4 TO L 10 V C C O U T1 O U T3 O U T4 R ES ET TH 0 1 2 CDLY3 4 5 6 1718 16 14 13 CDLY2 CDLY1 EN3 EN2 EN1 GND MAX16029 MAX16030 IN 2 O U T2 3 15 CDLY4 20 11 EN4CRESET 19 12 TH1MR THIN QFN (4mm x 4mm) Pin Configurations Ordering Information 19-0525; Rev 3; 1/07 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. +Denotes lead-free package. *For tape and reel, add a “T” after the “+.” All tape and reel orders are available in 2.5k increments. EVALU ATION KIT AVAIL ABLE PART* TEMP RANGE PIN- PACKAGE PKG CODE MAX16025TE+ -40°C to +125°C 16 TQFN T1644-4 MAX16026TE+ -40°C to +125°C 16 TQFN T1644-4 MAX16027TP+ -40°C to +125°C 20 TQFN T2044-3 MAX16028TP+ -40°C to +125°C 20 TQFN T2044-3 MAX16029TG+ -40°C to +125°C 24 TQFN T2444-4 MAX16030TG+ -40°C to +125°C 24 TQFN T2444-4 Selector Guide PART MONITORED VOLTAGES INDEPENDENT OUTPUTS RESET OUTPUT MAX16025 2 2 (Open-drain) Open-drain MAX16026 2 2 (Push-pull) Push-pull MAX16027 3 3 (Open-drain) Open-drain MAX16028 3 3 (Push-pull) Push-pull MAX16029 4 4 (Open-drain) Open-drain MAX16030 4 4 (Push-pull) Push-pull Pin Configurations continued at end of data sheet.

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = 2.2V to 28V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (All voltages referenced to GND.) VCC.........................................................................-0.3V to +30V EN1–EN4 ....................................................-0.3V to (VCC + 0.3V) OUT1–OUT4 (push-pull).............................-0.3V to (VCC + 0.3V) OUT1–OUT4 (open-drain) ......................................-0.3V to +30V RESET (push-pull) ......................................-0.3V to (VCC + 0.3V) RESET (open-drain) ..................................................-0.3V to 30V IN1–IN4.......................................................-0.3V to (VCC + 0.3V) MR, TOL, TH1, TH0 ....................................-0.3V to (VCC + 0.3V) CDLY1–CDLY4 .........................................................-0.3V to +6V CRESET......................................................-0.3V to (VCC + 0.3V) Input/Output Current (all pins)..........................................±20mA Continuous Power Dissipation (TA = +70°C) 16-Pin TQFN (derate 25mW/°C above +70°C) ...........2000mW 20-Pin TQFN (derate 25.6mW/°C above +70°C) ........2051mW 24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SUPPLY Operating Voltage Range VCC (Note 2) 2.2 28.0 V Undervoltage Lockout UVLO (Note 2) 1.8 1.9 2.0 V Undervoltage-Lockout Hysteresis UVLOHYST VCC falling 50 mV VCC = 3.3V 40 75 VCC = 12V 47 75VCC Supply Current ICC All OUT_ and RESET at logic-high (IN_ current excluded) VCC = 28V 52 80 µA INPUTS (IN_) 3.3V threshold, TOL = GND 2.970 3.052 3.135 3.3V threshold, TOL = VCC 2.805 2.888 2.970 2.5V threshold, TOL = GND 2.250 2.313 2.375 2.5V threshold, TOL = VCC 2.125 2.187 2.250 1.8V threshold, TOL = GND 1.620 1.665 1.710 1.8V threshold, TOL = VCC 1.530 1.575 1.620 1.5V threshold, TOL = GND 1.350 1.387 1.425 1.5V threshold, TOL = VCC 1.275 1.312 1.350 1.2V threshold, TOL = GND 1.080 1.110 1.140 IN_ Thresholds (IN_ Falling) VTH 1.2V threshold, TOL = VCC 1.020 1.050 1.080 V TOL = GND 0.492 0.5 0.508Adjustable Threshold (IN_ Falling) VTH TOL = VCC 0.463 0.472 0.481 V IN_ Hysteresis (IN_ Rising) VHYST 0.5 % IN_ Input Resistance Fixed threshold 500 918 kΩ IN_ Input Current IL Adjustable threshold only (VIN_ = 1V) -100 +100 nA

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.2V to 28V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CRESET AND CDLY_ CRESET Threshold VTH-RESET CRESET rising, VCC = 3.3V 0.465 0.5 0.535 V CRESET Charge Current ICH-RESET VCC = 3.3V 380 500 620 nA CDLY_ Threshold VTH-CDLY CDLY_ rising, VCC = 3.3V 0.95 1 1.05 V CDLY_ Charge Current ICH-CDLY VCC = 3.3V 200 250 300 nA DIGITAL LOGIC INPUTS (EN_, MR, TOL, TH1, TH0) Input Low Voltage VIL 0.4 V Input High Voltage VIH 1.4 V TH1, TH0 Logic-Input Floating 0.6 V TOL, TH1, TH0 Logic-Input Current VTOL, VTH1, VTH0 = GND or VCC -1 +1 µA EN_ Input Leakage Current VEN_ = VCC or GND -100 +100 nA MR Internal Pullup Current VCC = 3.3V 250 535 820 nA OUTPUTS (OUT_, RESET) VCC ≥ 1.2V, ISINK = 90µA 0.3 VCC ≥ 2.25V, ISINK = 0.5mA 0.3 Output Low Voltage (Open-Drain or Push-Pull) VOL VCC ≥ 4.5V, ISINK = 1mA 0.35 V VCC ≥ 3V, ISOURCE = 500µA 0.8 x VCC Output High Voltage (Push-Pull) VOH VCC ≥ 4.5V, ISOURCE = 800µA 0.8 x VCC V Output Leakage Current (Open- Drain) ILKG Output not asserted low, VOUT = 28V 1 µA CRESET = VCC, VCC = 3.3V 140 190 260 Reset Timeout Period tRP CRESET open 0.030 ms TIMING tDELAY+ IN_ rising, CDLY_ open 35 IN_ to OUT_ Propagation Delay tDELAY- IN_ falling, CDLY_ open 20 µs IN_ to RESET Propagation Delay tRST-DELAY IN_ falling 35 µs MR Minimum Input Pulse Width (Note 3) 2 µs EN_ or MR Glitch Rejection 280 ns tOFF From device enabled to device disabled 3 EN_ to OUT_ Delay tON From device disabled to device enabled (CDLY_ open) 30 µs MR to RESET Delay MR falling 3 µs Note 1: Devices are production tested at TA = +25°C. Limits over temperature are guaranteed by design. Note 2: Operating below the UVLO causes all outputs to go low. The outputs are guaranteed to be in the correct state for VCC down to 1.2V. Note 3: In order to guarantee an assertion, the minimum input pulse width must be greater than 2µs.

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 4 _______________________________________________________________________________________ Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE M A X 1 6 0 2 5 t o c0 1 SUPPLY VOLTAGE (V) S U P P LY C U R R EN T (μ A ) 26221814106 35 40 45 50 55 60 30 2 30 MAX16026 SUPPLY CURRENT vs. TEMPERATURE M A X 1 6 0 2 5 t o c0 2 TEMPERATURE (°C) S U P P LY C U R R EN T (μ A ) 1109580655035205-10-25 35 40 45 50 55 60 30 -40 125 MAX16026VCC = 28V VCC = 12V VCC = 3.3V NORMALIZED ADJUSTABLE THRESHOLD vs. TEMPERATURE M A X 1 6 0 2 5 t o c0 3 TEMPERATURE (°C) N O R M A LI ZE D T H R ES H O LD 1109565 80-10 5 20 35 50-25 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 0.990 -40 125 TOL = VCC TOL = GND ADJUSTABLE THRESHOLD NORMALIZED ADJUSTABLE THRESHOLD vs. TEMPERATURE M A X 1 6 0 2 5 t o c0 4 TEMPERATURE (°C) N O R M A LI ZE D T H R ES H O LD 1109565 80-10 5 20 35 50-25 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 0.990 -40 125 TOL = VCC TOL = GND 3.3V THRESHOLD OUT_ DELAY vs. CCDLY_ M A X 1 6 0 2 5 t o c0 5 CCDLY_ (nF) O U T_ D EL A Y ( m s) 900800600 700200 300 400 500100 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0 0 1000 RESET TIMEOUT PERIOD vs. CCRESET M A X 1 6 0 2 5 t o c0 6 CCRESET (nF) R ES ET T IM EO U T P ER IO D ( m s) 900800600 700200 300 400 500100 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 0 1000 FIXED RESET TIMEOUT PERIOD vs. TEMPERATURE M A X 1 6 0 2 5 t o c0 7 TEMPERATURE (°C) FI X ED R ES ET T IM EO U T P ER IO D ( m s) 1109565 80-10 5 20 35 50-25 186 187 188 189 190 191 192 193 194 195 185 -40 125 CRESET = VCC OUT_ LOW VOLTAGE vs. SINK CURRENT M A X 1 6 0 2 5 t o c0 8 SINK CURRENT (mA) V O U T_ ( V ) 654321 0.2 0.4 0.6 0.8 1.0 0 0 7 OUT_ HIGH VOLTAGE vs. SOURCE CURRENT M A X 1 6 0 2 5 t o c0 9 SOURCE CURRENT (mA) V O U T_ ( V ) 0.90.80.70.60.50.40.30.20.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0 1.0 PUSH-PULL VERSIONS

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits _______________________________________________________________________________________ 5 RESET OUTPUT LOW VOLTAGE vs. SINK CURRENT M A X 1 6 0 2 5 t o c1 0 SINK CURRENT (mA) R ES ET O U TP U T LO W V O LT A G E (V ) 653 421 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0 7 RESET OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT M A X 1 6 0 2 5 t o c1 1 SOURCE CURRENT (mA) R ES ET O U TP U T H IG H V O LT A G E (V ) 0.90.80.70.60.50.40.30.20.1 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0 1.0 PUSH-PULL VERSIONS ENABLE TURN-OFF MAX16025 toc12 4μs/div EN_ OUT_ RESET CRESET = VCC CDLY_ = OPEN ENABLE TURN-ON MAX16025 toc13 40ms/div EN_ OUT_ RESET CRESET = VCC CDLY_ = OPEN RESET TIMEOUT DELAY MAX16025 toc14 100ms/div IN_ OUT_ RESET CRESET = VCC CDLY_ = OPEN MR FALLING vs. RESET MAX16025 toc15 4μs/div RESET CRESET = VCC CDLY_ = OPEN MR MR RISING vs. RESET MAX16025 toc16 40ms/div RESET CRESET = VCC CDLY_ = OPEN MR MAXIMUM TRANSIENT DURATION vs. THRESHOLD OVERDRIVE M A X 1 6 0 2 5 t o c1 7 THRESHOLD OVERDRIVE (mV) M A X IM U M T R A N S IE N T D U R A TI O N ( μ s) 10010 10 20 30 40 50 60 70 80 90 100 0 1 1000 OUTPUT ASSERTED ABOVE THIS LINE Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.)

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 6 _______________________________________________________________________________________ Pin Description PIN MAX16025/ MAX16026 MAX16027/ MAX16028 MAX16029/ MAX16030 NAME FUNCTION 1 1 1 VCC Supply Voltage Input. Connect a 2.2V to 28V supply voltage to power the device. All outputs are low when VCC is below the UVLO. For noisy systems, bypass VCC to GND with a 0.1µF capacitor. 2 2 2 IN1 Monitored Input 1. When the voltage at IN1 exceeds its threshold, OUT1 goes high after the capacitor-adjustable delay period. When the voltage at IN1 falls below its threshold, OUT1 goes low after a propagation delay. 3 3 3 IN2 Monitored Input 2. When the voltage at IN2 exceeds its threshold, OUT2 goes high after the capacitor-adjustable delay period. When the voltage at IN2 falls below its threshold, OUT2 goes low after a propagation delay. — 4 4 IN3 Monitored Input 3. When the voltage at IN3 exceeds its threshold, OUT3 goes high after the capacitor-adjustable delay period. When the voltage at IN3 falls below its threshold, OUT3 goes low after a propagation delay. — — 5 IN4 Monitored Input 4. When the voltage at IN4 exceeds its threshold, OUT4 goes high after the capacitor-adjustable delay period. When the voltage at IN4 falls below its threshold, OUT4 goes low after a propagation delay. 4 5 6 TOL Threshold Tolerance Input. Connect TOL to GND to select thresholds 5% below nominal. Connect TOL to VCC to select thresholds 10% below nominal. 5 6 7 GND Ground 6 7 8 EN1 Active-High Logic-Enable Input 1. Driving EN1 low causes OUT1 to go low regardless of the input voltage. Drive EN1 high to enable the monitoring comparator. 7 8 9 EN2 Active-High Logic-Enable Input 2. Driving EN2 low causes OUT2 to go low regardless of the input voltage. Drive EN2 high to enable the monitoring comparator. — 9 10 EN3 Active-High Logic-Enable Input 3. Driving EN3 low causes OUT3 to go low regardless of the input voltage. Drive EN3 high to enable the monitoring comparator. — — 11 EN4 Active-High Logic-Enable Input 4. Driving EN4 low causes OUT4 to go low regardless of the input voltage. Drive EN4 high to enable the monitoring comparator. 8 10 12 TH1 Threshold Select Input 1. Connect TH1 to VCC or GND, or leave it open to select the input-voltage threshold option in conjunction with TH0 (see Table 2). 9 11 13 TH0 Threshold Select Input 0. Connect TH0 to VCC or GND, or leave it open to select the input-voltage threshold option in conjunction with TH1 (see Table 2). — — 14 OUT4 Output 4. When the voltage at IN4 is below its threshold or EN4 goes low, OUT4 goes low. — 12 15 OUT3 Output 3. When the voltage at IN3 is below its threshold or EN3 goes low, OUT3 goes low. 10 13 16 OUT2 Output 2. When the voltage at IN2 is below its threshold or EN2 goes low, OUT2 goes low.

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits _______________________________________________________________________________________ 7 Pin Description (continued) PIN MAX16025/ MAX16026 MAX16027/ MAX16028 MAX16029/ MAX16030 NAME FUNCTION 11 14 17 OUT1 Output 1. When the voltage at IN1 is below its threshold or EN1 goes low, OUT1 goes low. 12 15 18 RESET Active-Low Reset Output. RESET asserts low when any of the monitored voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is asserted. RESET remains asserted for the reset timeout period after all of the monitored voltages exceed their respective threshold, all EN_ are high, all OUT_ are high, and MR is deasserted. 13 16 19 MR Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout period after MR is deasserted (as long as all OUT_ are high). 14 17 20 CRESET Capacitor-Adjustable Reset Delay Input. Connect an external capacitor from CRESET to GND to set the reset timeout period or connect to VCC for the default 140ms minimum reset timeout period. Leave CRESET open for internal propagation delay. — — 21 CDLY4 Capacitor-Adjustable Delay Input 4. Connect an external capacitor from CDLY4 to GND to set the IN4 to OUT4 (and EN4 to OUT4) delay period. Leave CDLY4 open for internal propagation delay. — 18 22 CDLY3 Capacitor-Adjustable Delay Input 3. Connect an external capacitor from CDLY3 to GND to set the IN3 to OUT3 (and EN3 to OUT3) delay period. Leave CDLY3 open for internal propagation delay. 15 19 23 CDLY2 Capacitor-Adjustable Delay Input 2. Connect an external capacitor from CDLY2 to GND to set the IN2 to OUT2 (and EN2 to OUT2) delay period. Leave CDLY2 open for internal propagation delay. 16 20 24 CDLY1 Capacitor-Adjustable Delay Input 1. Connect an external capacitor from CDLY1 to GND to set the IN1 to OUT1 (and EN1 to OUT1) delay period. Leave CDLY1 open for internal propagation delay. — — — EP Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane. Table 1. Output State* EN_ IN_ OUT_ Low VIN_ < VTH Low High VIN_ < VTH Low Low VIN_ > VTH Low OUT_ = high (MAX16026/MAX16028/ MAX16030) High VIN_ > VTH OUT_ = high impedance (MAX16025/MAX16027/ MAX16029) Table 2. Input-Voltage Threshold Selector TH1/TH0 LOGIC IN1 (ALL VERSIONS) (V) IN2 (ALL VERSIONS) (V) IN3 (MAX16027/ MAX16028) (V) IN4 (MAX16029/ MAX16030) (V) Low/Low 3.3 2.5 1.8 1.5 Low/High 3.3 1.8 Adj Adj Low/Open 3.3 1.5 Adj Adj High/Low 3.3 1.2 1.8 2.5 High/High 2.5 1.8 Adj Adj High/Open 3.3 Adj 2.5 Adj Open/Low 3.3 Adj Adj Adj Open/High 2.5 Adj Adj Adj Open/Open Adj Adj Adj Adj *When VCC falls below the UVLO, all outputs go low regardless of the state of EN_ and VIN_. The outputs are guaranteed to be in the correct state for VCC down to 1.2V.

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 8 _______________________________________________________________________________________ LOGIC 1V 250nA OUT1 OUT2 OUT3 OUT4 RESET EN1EN2EN3EN4TH1TH0 IN1 IN2 IN3 IN4 GND TOL DRIVER DRIVER DRIVER DRIVER DELAY DELAY DELAY DELAY VCC CDLY1 CDLY2 CDLY3 CDLY4 CRESET MR REFERENCE THRESHOLD SELECT LOGIC RESET DELAY LOGIC DRIVER MAX16029 MAX16030 Figure 1. MAX16029/MAX16030 Simplified Functional Diagram

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits _______________________________________________________________________________________ 9 Detailed Description The MAX16025–MAX16030 are low-voltage, accurate, dual-/triple-/quad-voltage microprocessor (µP) supervi- sors in a small TQFN package. These devices provide supervisory and sequencing functions for complex mul- tivoltage systems. The MAX16025/MAX16026 monitor two voltages, the MAX16027/MAX16028 monitor three voltages, and the MAX16029/MAX16030 monitor four voltages. The MAX16025–MAX16030 offer independent outputs and enable functions for each monitored voltage. This configuration allows the device to operate as four sepa- rate supervisory circuits or be daisy-chained together to allow controlled sequencing of power supplies during power-up initialization. When all of the monitored volt- ages exceed their respective thresholds, an indepen- dent reset output deasserts to allow the system processor to operate. These devices offer enormous flexibility as there are nine threshold options that are selected through two threshold-select logic inputs. Each monitor circuit also offers an independent enable input to allow both digital and analog control of each monitor output. A tolerance select input allows these devices to be used in systems requiring 5% or 10% power-supply tolerances. In addi- tion, the time delays and reset timeout can be adjusted using small capacitors. There is also a fixed 140ms minimum reset timeout feature. Figure 2. Timing Diagram (CDLY_ Open) VCC VTH VTH t < tON VUVLO tON tRP tDELAY- tDELAY+ tRST_DELAY tOFF tRP tRP tON IN_ EN_ OUT_ RESET

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Applications Information Tolerance The MAX16025–MAX16030 feature a pin-selectable threshold tolerance. Connect TOL to GND to select the thresholds 5% below the nominal value. Connect TOL to VCC to select the threshold tolerance 10% below the nominal voltage. Do not leave TOL unconnected. Adjustable Input These devices offer several monitoring options with both fixed and/or adjustable reset thresholds (see Table 2). For the adjustable threshold inputs, the threshold voltage (VTH) at each adjustable IN_ input is typically 0.5V (TOL = GND) or 0.472V (TOL = VCC). To monitor a voltage VINTH, connect a resistive divider net- work to the circuit as shown in Figure 3 and use the fol- lowing equation to calculate the threshold voltage: Choosing the proper external resistors is a balance between accuracy and power use. The input to the volt- age monitor is a high-impedance input with a small 100nA leakage current. This leakage current con- tributes to the overall error of the threshold voltage where the output is asserted. This induced error is pro- portional to the value of the resistors used to set the threshold. With lower value resistors, this error is reduced, but the amount of power consumed in the resistors increases. The following equation is provided to help estimate the value of the resistors based on the amount of accept- able error: where eA is the fraction of the maximum acceptable absolute resistive divider error attributable to the input leakage current (use 0.01 for ±1%), VINTH is the volt- age at which the output (OUT_) should assert, and IL is the worst-case IN_ leakage current (see the Electrical Characteristics). Calculate R2 as follows: Unused Inputs Connect any unused IN_ and EN_ inputs to VCC. OUT_ Output An OUT_ goes low when its respective IN_ input voltage drops below its specified threshold or when its EN_ goes low (see Table 1). OUT_ goes high when EN_ is high and VIN_ is above its threshold after a time delay. The MAX16025/MAX16027/MAX16029 feature open-drain, outputs while the MAX16026/MAX16028/MAX16030 have push-pull outputs. Open-drain outputs require an external pullup resistor to any voltage from 0 to 28V. RESET Output RESET asserts low when any of the monitored voltages (IN_) falls below its respective threshold, any EN_ goes low, or MR is asserted. RESET remains asserted for the reset timeout period after all of the monitored voltages exceed their respective threshold, all EN_ are high, all OUT_ are high, and MR is deasserted. The MAX16025/ MAX16027/MAX16029 have an open-drain, active-low reset output, while the MAX16026/MAX16028/ MAX16030 have a push-pull, active-low reset output. Open-drain RESET requires an external pullup resistor to any voltage from 0 to 28V. Adjustable Reset Timeout Period (CRESET) All of these parts offer an internally fixed reset timeout (140ms min) by connecting CRESET to VCC. The reset timeout can also be adjusted by connecting a capaci- tor from CRESET to GND. When the voltage at CRESET reaches 0.5V, RESET goes high. When RESET goes high, CRESET is immediately held low. R V R V V TH INTH TH 2 1 = × − R e V I A INTH L 1 = × V V R R INTH TH= × + ⎛ ⎝ ⎜ ⎞ ⎠ ⎟1 1 2 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 10 ______________________________________________________________________________________ IN_ VTH VINTH R1 = R2 x ( )VINTH VTH R1 R2 MAX16025– MAX16030 -1 Figure 3. Setting the Adjustable Input

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Calculate the reset timeout period as follows: where VTH-RESET is 0.5V, ICH-RESET is 0.5µA, tRP is in seconds, and CCRESET is in Farads. To ensure timing accuracy and proper operation, minimize leakage at CCRESET. Adjustable Delay (CDLY_) When VIN rises above VTH with EN_ high, the internal 250nA current source begins charging an external capacitor connected from CDLY_ to GND. When the voltage at CDLY_ reaches 1V, OUT_ goes high. When OUT_ goes high, CDLY_ is immediately held low. Adjust the delay (tDELAY) from when VIN rises above VTH (with EN_ high) to OUT_ going high according to the equation: where VTH-CDLY is 1V, ICH-CDLY is 0.25µA, CCDLY is in Farads, tDELAY is in seconds, and tDELAY+ is the inter- nal propagation delay of the device. To ensure timing accuracy and proper operation, minimize leakage at CDLY. Manual-Reset Input (MR) Many µP-based products require manual-reset capabil- ity, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic-low on MR asserts RESET low. RESET remains asserted while MR is low and during the reset timeout period (140ms fixed or capacitor adjustable) after MR returns high. The MR input has a 500nA internal pullup, so it can be left unconnected, if not used. MR can be driven with TTL or CMOS logic levels, or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual-reset function. External debounce circuitry is not required. If MR is driven from long cables or if the device is used in a noisy environ- ment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. Pullup Resistor Values The exact value of the pullup resistors for the open- drain outputs is not critical, but some consideration should be made to ensure the proper logic levels when the device is sinking current. For example, if VCC = 2.25V and the pullup voltage is 28V, keep the sink current less than 0.5mA as shown in the Electrical Characteristics table. As a result, the pullup resistor should be greater than 56kΩ. For a 12V pullup, the resistor should be larger than 24kΩ. Note that the ability to sink current is dependent on the VCC supply voltage. Power-Supply Bypassing The device operates with a VCC supply voltage from 2.2V to 28V. When VCC falls below the UVLO threshold, all the outputs go low and stay low until VCC falls below 1.2V. For noisy systems or fast rising transients on VCC, connect a 0.1µF ceramic capacitor from VCC to GND as close to the device as possible to provide better noise and transient immunity. Ensuring Valid Output with VCC Down to 0V (MAX16026/MAX16028/MAX16030 Only) When VCC falls below 1.2V, the ability for the output to sink current decreases. In order to ensure a valid out- put as VCC falls to 0V, connect a 100kΩ resistor from OUT/RESET to GND. Typical Application Circuits Figures 4 and 5 show typical applications for the MAX16025–MAX16030. In high-power applications, using an n-channel device reduces the loss across the MOSFETs as it offers a lower drain-to-source on-resis- tance. However, an n-channel MOSFET requires a suffi- cient VGS voltage to fully enhance it for a low RDS_ON. The application in Figure 4 shows the MAX16027 con- figured in a multiple-output sequencing application. Figure 5 shows the MAX16029 in a power-supply sequencing application using n-channel MOSFETs. t V I CDELAY TH CDLY CH CDLY CDLY= × + × − − −35 10 6 t V I CRP TH RESET CH RESET CRESET= × + × − − −35 10 6 M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits ______________________________________________________________________________________ 11

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 12 ______________________________________________________________________________________ Figure 4. Sequencing Multiple-Voltage System Figure 5. Multiple-Voltage Sequencing Using n-Channel FETs EN1 VCC MR CDLY1 CDLY2 CDLY3 CRESET GND TOL TH0 TH1 OUT1 EN2 IN2 OUT2 EN3 IN3 +3.3V OUT3 IN1 EN DC-DC OUT +3.3V IN MAX16027 +12V BUS EN DC-DC OUT +2.5V IN EN DC-DC OUT +1.8V IN RESET SYSTEM RESET VCC EN1 EN4 CDLY1 CDLY2 CDLY3 CDLY4 CRESET GND TOL TH0 TH1 IN2OUT1 OUT2 IN3 OUT3 IN4 +3.3V OUT4 IN1 12V BUS 1.5V 1.8V 2.5V 3.3V MAX16029 MR RESET SYSTEM RESET TO LOADS EN3 EN2

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits ______________________________________________________________________________________ 13 + TOP VIEW 19 20 18 17 7 6 8 IN 1 IN 3 TO L 9 V C C O U T1 O U T3 TH 0 R ES ET 1 2 CDLY3 4 5 15 14 12 11 CDLY2 CDLY1 EN3 EN2 EN1 GND MAX16027 MAX16028 IN 2 O U T2 3 13 CRESET 16 10 TH1MR THIN QFN (4mm x 4mm) 15 16 + 14 13 6 5 7 IN 1 TO L 8 V C C O U T1 TH 0 R ES ET 1 2 CRESET 4 12 11 9 CDLY2 CDLY1 TH1 EN2 EN1 GND MAX16025 MAX16026 IN 2 O U T2 3 10 MR THIN QFN (4mm x 4mm) Pin Configurations (continued) Chip Information PROCESS: BICMOS TRANSISTOR COUNT: 3642

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M A X 1 6 0 2 5 – M A X 1 6 0 3 0 Dual-/Triple-/Quad-Voltage, Capacitor- Adjustable, Sequencing/Supervisory Circuits 14 ______________________________________________________________________________________ Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 2 4 L Q F N T H IN .E P S PACKAGE OUTLINE, 21-0139 2 1 E 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm

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