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MAX3671ETN+T

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MAX3671ETN+T

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Part Number MAX3671ETN+T
Manufacturer Microsemi Corporation
Description IC SYNTHESIZER FREQ 56-TQFN
Datasheet MAX3671ETN+T Datasheet
Package 56-WFQFN Exposed Pad
In Stock 375 piece(s)
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Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # MAX3671ETN+T (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by Microsemi Corporation and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MAX3671ETN+T Specifications

ManufacturerMicrosemi Corporation
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet MAX3671ETN+TDatasheet
Package56-WFQFN Exposed Pad
Series-
TypeFrequency Synthesizer
PLLYes with Bypass
InputLVPECL
OutputLVPECL
Number of Circuits1
Ratio - Input:Output2:9
Differential - Input:OutputYes/Yes
Frequency - Max312.5MHz
Divider/MultiplierYes/No
Voltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case56-WFQFN Exposed Pad
Supplier Device Package56-TQFN-EP (7x7)

MAX3671ETN+T Datasheet

Page 1

Page 2

General Description The MAX3671 is a low-jitter frequency synthesizer that accepts two reference clock inputs and generates nine phase-aligned outputs. The device features 40kHz jitter transfer bandwidth, 0.3psRMS (12kHz to 20MHz) inte- grated phase jitter, and best-in-class power-supply noise rejection (PSNR), making it ideal for jitter clean- up, frequency translation, and clock distribution in Gigabit Ethernet applications. The MAX3671 operates from a single +3.3V supply and typically consumes 400mW. The IC is available in an 8mm x 8mm, 56-pin TQFN package, and operates from -40°C to +85°C. Applications Gigabit Ethernet Routers and Switches Frequency Translation Jitter Cleanup Clock Distribution Features ♦ Two Reference Clock Inputs: LVPECL ♦ Nine Phase-Aligned Clock Outputs: LVPECL ♦ Input Frequencies: 62.5MHz,125MHz, 250MHz, 312.5MHz ♦ Output Frequencies: 62.5MHz, 125MHz, 156.25MHz, 250MHz, 312.5MHz ♦ Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz) ♦ Clock Failure Indicator for Both Reference Clocks ♦ External Feedback Provides Zero-Delay Capability ♦ Low Output Skew: 20ps Typical M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference ________________________________________________________________ Maxim Integrated Products 1 Ordering Information 19-4437; Rev 0; 2/09 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALU ATION KIT AVAIL ABLE PART TEMP RANGE PIN-PACKAGE MAX3671ETN+ -40°C to +85°C 56 TQFN-EP* SIGNAL QUALIFIER AND LOCK DETECT POWER-ON RESET (POR) IN0FAIL IN1FAIL LOCK REFCLK0 REFCLK0 FB_INFB_SEL FB_IN REFCLK1 REFCLK1 MR 0 1 1 0DIV M DMSEL_CLK DA DB PFD CP DIV N DIV A DIV B VCO 2.5GHz62.5MHz OUTA2 OUTA2 OUTA1 OUTA1 OUTA3 OUTA3 OUTA0 OUTB_EN OUTA0 OUTA_ENPLL_BYPASS 1 0 1 0 OUTB3 OUTB3 OUTB2 OUTB2 OUTB4 OUTB4 OUTB1 OUTB1 OUTB0 OUTB0 CPLL 0.1μF CREG 0.22μF MAX3671 Functional Diagram +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Pin Configuration and Typical Application Circuits appear at end of data sheet.

Page 3

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage Range (VCC, VCC_VCO)..............-0.3V to +4.0V LVPECL Output Current (OUTA[3:0], , OUTB[4:0], ) .............................-56mA All Other Pins..............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW Operating Junction Temperature (TJ)................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C OUTB[ : ]4 0OUTA[ : ]3 0 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current ICC LVPECL outputs unterminated 120 175 mA POWER-ON RESET VCC Rising (Note 1) 2.55 V VCC Falling (Note 1) 2.45 V LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPASS, FB_SEL) Input High Voltage VIH 2.0 V Input Low Voltage VIL 0.8 V Input High Current IIH VIN = VCC 75 μA Input Low Current IIL VIN = GND -75 μA LVCMOS/LVTTL OUTPUTS (IN0FAIL, IN1FAIL, LOCK) Output High Voltage VOH IOH = -8mA 2.4 V Output Low Voltage VOL IOL = +8mA 0.4 V LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2) Input High Voltage VIH VCC - 0.7 V Input Low Voltage VIL VCC - 2.0 V Input Bias Voltage VCMI VCC - 1.8 VCC - 1.34 V Differential-Input Swing 0.15 1.9 VP-P Differential-Input Impedance > 40 k Common-Mode Input Impedance > 14 k Input Capacitance 1.5 pF Input Current VIH = VCC - 0.7V, VIL = VCC - 2.0V -100 +100 μA Input Inrush Current When Power is Off (Steady State) IDC (Notes 3, 4) 8 mA Input Inrush Current Overshoot When Power is Off IOVERSHOOT (Notes 3, 4) 6 mA

Page 4

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1) Reference Clock Frequency fREF Table 1 MHz Reference Clock Frequency Tolerance -200 +200 ppm Reference Clock Duty Cycle 40 60 % Reference Clock Amplitude Detection Assert Threshold VDT Differential swing (Notes 5, 6) 200 mVP-P LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 7) Output High Voltage VOH VCC - 1.13 VCC - 0.98 VCC - 0.83 V Output Low Voltage VOL VCC - 1.85 VCC - 1.70 VCC - 1.55 V Differential-Output Swing 1.1 1.45 1.8 VP-P Output Current When Disabled VO = VCC - 2.0V to VCC - 0.7V 130 μA Output Frequency fOUT Tables 2, 3 MHz Output Rise/Fall Time tR, tF 20% to 80% (Note 8) 150 500 ps PLL_BYPASS = 0 48 52 Output Duty Cycle PLL_BYPASS = 1 (Note 9) 45 55 % Within output bank 20 Output-to-Output Skew tSKEW All outputs 40 ps OTHER AC ELECTRICAL SPECIFICATIONS PLL Jitter Transfer Bandwidth 40 kHz Jitter Peaking 0.1 dB PFD Compare Frequency 62.5 MHz VCO Center Frequency 2.5 GHz Random Jitter Generation Integrated 12kHz to 20MHz (Notes 5, 8) 0.3 1.0 psRMS Determinisitic Jitter Caused by Power-Supply Noise (Note 10) 5 psP-P Frequency Difference Between Reference Clock and VCO Within Which the PLL is Considered in Lock 500 ppm Frequency Difference Between Reference Clock and VCO at Which the PLL is Considered Out-of-Lock 800 ppm PLL Lock Time tLOCK Figure 2 600 μs

Page 5

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference 4 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Master Reset (MR) Minimum Pulse Width 100 ns Propagation Delay from Input to FB_IN FB_SEL = 1 (Notes 8, 11) -120 +120 ps Propagation Delay from Input to Any Output PLL_BYPASS = 1 1.0 ns Note 1: During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the Power- On-Reset (POR) section for more information. Note 2: LVPECL inputs can be AC- or DC-coupled. Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with VCC pins connected to GND. See Figure 1. Note 4: Measured with LVPECL input (VIH, VIL) as specified. Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%). Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4. Note 7: LVPECL outputs terminated 50Ω to VTT = VCC - 2V. Note 8: Guaranteed by design and characterization. Note 9: Measured with 50% duty cycle at reference clock input. Note 10: Measured with 50mVP-P sinusoidal noise on the power supply, fNOISE = 100kHz. Note 11: Measured with fREFCLKx = fFB_IN and matched slew rates.

Page 6

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference _______________________________________________________________________________________ 5 t INRUSH CURRENT (mA) IDC IOVERSHOOT Figure 1. LVPECL Input Inrush Current REFCLK0 REFCLK1 OUTxx IN0FAIL IN1FAIL LOCK HIGH SEL_CLK LOW VCC POWER-ON-RESET (~ 20μs) HIGH tLOCK (~ 600μs) PLL LOCKED TO REFCLK0 Figure 2. Power-Up, PLL Locks to REFCLK0

Page 7

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference 6 _______________________________________________________________________________________ Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) PHASE NOISE AT 62.5MHz M A X 3 6 7 1 t o c0 1 OFFSET FREQUENCY (Hz) P H A S E N O IS E (d B c/ H z) 10M1M100k10k1k -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -160 100 100M RANDOM JITTER = 0.41psRMS INTEGRATED 12kHz TO 20MHz PHASE NOISE AT 125MHz M A X 3 6 7 1 t o c0 2 OFFSET FREQUENCY (Hz) P H A S E N O IS E (d B c/ H z) 10M1M100k10k1k -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -160 100 100M RANDOM JITTER = 0.29psRMS INTEGRATED 12kHz TO 20MHz PHASE NOISE AT 156.25MHz M A X 3 6 7 1 t o c0 3 OFFSET FREQUENCY (Hz) P H A S E N O IS E (d B c/ H z) 10M1M100k10k1k -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -160 100 100M RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz PHASE NOISE AT 250MHz M A X 3 6 7 1 t o c0 4 OFFSET FREQUENCY (Hz) P H A S E N O IS E (d B c/ H z) 10M1M100k10k1k -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -160 100 100M RANDOM JITTER = 0.27psRMS INTEGRATED 12kHz TO 20MHz PHASE NOISE AT 312.5MHz M A X 3 6 7 1 t o c0 5 OFFSET FREQUENCY (Hz) P H A S E N O IS E (d B c/ H z) 10M1M100k10k1k -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -160 100 100M RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz JITTER TRANSFER M A X 3 6 7 1 t o c0 6 JITTER FREQUENCY (Hz) JI TT ER T R A N S FE R ( dB ) 100k10k -25 -20 -15 -10 -5 0 5 -30 1k 1M DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz MAX3671 toc07 800ps/div 200mV/div DIFFERENTIAL OUTPUT WAVEFORM AT 312.5MHz MAX3671 toc08 400ps/div 200mV/div REFERENCE CLOCK AMPLITUDE DETECTION ASSERT THRESHOLD vs. INPUT FREQUENCY M A X 3 6 7 1 t o c0 9 REFERENCE CLOCK INPUT FREQUENCY (MHz) A S S ER T TH R ES H O LD ( m V P -P ) 300250200150100 120 140 160 180 200 220 240 260 280 300 100 50 350 INPUT RISE/FALL TIME = 550ps INPUT RISE/FALL TIME = 270ps

Page 8

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference _______________________________________________________________________________________ 7 SUPPLY CURRENT vs. TEMPERATURE M A X 3 6 7 1 t o c1 0 TEMPERATURE (°C) S U P P LY C U R R EN T (m A ) 603510-15 50 100 150 200 250 300 350 400 450 500 0 -40 85 ALL OUTPUTS ENABLED AND TERMINATED ALL OUTPUTS ENABLED AND UNTERMINATED JITTER HISTOGRAM WITH SUPPLY NOISE (SUPPLY NOISE = 50mVP-P, 100kHz) MAX3671 toc11 2ps/div DJ = 5psP-P DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE AMPLITUDE M A X 3 6 7 1 t o c1 2 SUPPLY NOISE AMPLITUDE (mVP-P) D ET ER M IN IS TI C J IT TE R ( ps P -P ) 25020050 100 150 5 10 15 20 25 30 35 40 0 0 300 fNOISE = 100kHz fNOISE = 200kHz fNOISE = 1MHz SPURS CAUSED BY POWER-SUPPLY NOISE vs. SUPPLY NOISE FREQUENCY M A X 3 6 7 1 t o c1 3 SUPPLY NOISE FREQUENCY (Hz) S P U R P O W ER ( dB c) 1M100k -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 10k 10M fOUT = 125MHz SUPPLY NOISE = 100mVP-P SUPPLY NOISE = 50mVP-P DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE FREQUENCY M A X 3 6 7 1 t o c1 4 SUPPLY NOISE FREQUENCY (Hz) D ET ER M IN IS TI C J IT TE R ( ps P -P ) 1M100k 5 10 15 20 25 30 35 40 0 10k 10M SUPPLY NOISE = 100mVP-P SUPPLY NOISE = 50mVP-P POWER-ON-RESET MAX3671 toc15 200μs/div VCC OUTxx LOCK MASTER RESET MAX3671 toc16 40μs/div MR OUTxx LOCK REFERENCE CLOCK FAILURE DETECTION MAX3671 toc17 2ms/div REFCLK1 IN1FAIL LOCK Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.)

Page 9

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference 8 _______________________________________________________________________________________ Pin Description PIN NAME FUNCTION 1 IN0FAIL REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). 2 RSVD1 Reserved. Leave pin open. 3 RSVD2 Reserved. Connect to GND. 4 REFCLK0 5 REFCLK0 Reference Clock Input 0, Differential LVPECL 6 DM Four-Level Control Input for Reference Clock Input Divider. See Table 1. 7, 22, 30, 41, 49, 52 VCC Power Supply. Connect to +3.3V. 8, 14, 23, 29, 42, 48, 53 GND Supply Ground 9 MR Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal operation. Has internal 90k pullup to VCC. Connect low to reset the device. A reset is not required at power-up. If the output divider settings are changed on the fly, a reset is required to phase align the outputs. This input has a 100ns minimum pulse width and is asynchronous to the reference clock. While in reset, all clock outputs are held to logic- low. See Table 6. 10 REFCLK1 11 REFCLK1 Reference Clock Input 1, Differential LVPECL 12 SEL_CLK Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0 as the reference clock. Has internal 90k pulldown to GND. Connect high to select REFCLK1 as the reference clock. 13 VCC_VCO Power Supply for VCO. Connect to +3.3V. 15 CPLL Connection for PLL Filter Capacitor. Connect a 0.1μF capacitor between this pin and GND. 16 CREG Connection for VCO Regulator Capacitor. Connect a 0.22μF capacitor between this pin and GND. 17 FB_SEL External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has internal 90k pulldown to GND. 18 FB_IN 19 FB_IN External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer configuration. 20 OUTB0 21 OUTB0 Clock Output B0, Differential LVPECL 24 OUTB1 25 OUTB1 Clock Output B1, Differential LVPECL 26 OUTB2 27 OUTB2 Clock Output B2, Differential LVPECL 28 DB Four-Level Control Input for B-Group Output Divider. See Table 3. 31 OUTB3 32 OUTB3 Clock Output B3, Differential LVPECL 33 OUTB4 34 OUTB4 Clock Output B4, Differential LVPECL 35 OUTB_EN Three-Level Control Input for B-Group Output Enable. See Table 5. 36 OUTA_EN Three-Level Control Input for A-Group Output Enable. See Table 4.

Page 10

M A X 3 6 7 1 Low-Jitter Frequency Synthesizer with Selectable Input Reference _______________________________________________________________________________________ 9 Pin Description (continued) Detailed Description The MAX3671 integrates two differential LVPECL refer- ence inputs with a 2:1 mux, a PLL with configurable dividers, nine differential LVPECL clock outputs, and a selectable external feedback input for zero-delay buffer applications (see the Functional Diagram). The two reference clock inputs are continuously moni- tored for clock failure by the internal PLL and associat- ed logic. If the primary clock fails, the user can switch over to the secondary clock using the 2:1 mux. The PLL accepts reference input frequencies of 62.5, 125, 250, or 312.5MHz and generates output frequen- cies of 62.5, 125, 156.25, 250, or 312.5MHz. The nine clock outputs are organized into two groups (A and B). Each group has a configurable frequency divider and output-enable control. Phase-Locked Loop (PLL) The PLL contains a phase-frequency detector (PFD), charge pump (CP) with a lowpass filter, and voltage- controlled oscillator (VCO). The PFD compares the divided reference frequency to the divided VCO output at 62.5MHz, and generates a control signal to keep the VCO phase and frequency locked to the selected refer- ence clock. Using a high-frequency VCO (2.5GHz) and low-loop bandwidth (40kHz), the MAX3671 attenuates reference clock jitter while maintaining lock and gener- ates low-jitter clock outputs at multiple frequencies. Typical jitter generation is 0.3psRMS (integrated 12kHz to 20MHz). To minimize supply noise-induced jitter, the VCO sup- ply (VCC_VCO) is isolated from the core logic and out- put buffer supplies. Additionally, the MAX3671 uses an internal low-dropout (LDO) regulator to attenuate noise from the power supply. This allows the device to achieve excellent power-supply noise rejection, signifi- cantly reducing the impact on jitter generation. Clock Failure Conditions The MAX3671 clock failure detection is performed using the combination of amplitude qualification and PLL frequency and phase-error qualification. The failure status is indicated for REFCLK0 and REFCLK1 at PIN NAME FUNCTION 37 OUTA3 38 OUTA3 Clock Output A3, Differential LVPECL 39 OUTA2 40 OUTA2 Clock Output A2, Differential LVPECL 43 DA Four-Level Control Input for A-Group Output Divider. See Table 2. 44 OUTA1 45 OUTA1 Clock Output A1, Differential LVPECL 46 OUTA0 47 OUTA0 Clock Output A0, Differential LVPECL 50 PLL_BYPASS PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has internal 90k pulldown to GND. Connect high to bypass the PLL, connecting the selected reference clock directly to the clock outputs. In this mode, the clock qualification function is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled by shorting the CREG pin to GND. 51 RSVD3 Reserved. Connect to VCC. 54 RSVD4 Reserved. Leave pin open. 55 LOCK PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked. 56 IN1FAIL REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). — EP Exposed Pad. Connect to supply ground for proper electrical and thermal performance.

MAX3671ETN+T Reviews

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Aitan*****hington

August 16, 2020

Superb pricing and super fast delivery.

Roni*****bbard

August 16, 2020

Very good, fast shipping, super reliable seller.

Alann*****ggins

August 12, 2020

Used it on my system it works perfect as I need.

Van B*****ishnan

August 10, 2020

Great communication with sales. A pleasure to do business with you.

Wya*****Pall

August 9, 2020

Great Seller, Great Item, the quality is great, Highly Recommended.

Delil*****lison

August 2, 2020

High level customer service, and quick response.

Kynl*****ewman

July 30, 2020

happy with the IC and received with perfect packaging, good comunication with seller thanks.

Forres*****chandran

July 19, 2020

I wanted something that would handle voltage spikes. Worked perfectly. I plan to use four more.

Alan*****rphy

July 13, 2020

So far all the items still work. I'm using these for some home made solar panels and they're doing great.

Ange***** Brady

July 3, 2020

Best way to locate what I need, on a fast and efficient shipping! Keep up the good work!

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