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MAX5253AEAP+T

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MAX5253AEAP+T

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Part Number MAX5253AEAP+T
Manufacturer Maxim Integrated
Description IC DAC 12BIT QUAD 3V 20-SSOP
Datasheet MAX5253AEAP+T Datasheet
Package 20-SSOP (0.209", 5.30mm Width)
In Stock 1,378 piece(s)
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Lead Time Can Ship Immediately
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Part Number # MAX5253AEAP+T (Data Acquisition - Digital to Analog Converters (DAC)) is manufactured by Maxim Integrated and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MAX5253AEAP+T Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet MAX5253AEAP+TDatasheet
Package20-SSOP (0.209", 5.30mm Width)
Series-
Number of Bits12
Number of D/A Converters4
Settling Time16µs (Typ)
Output TypeVoltage - Buffered
Differential OutputNo
Data InterfaceSPI
Reference TypeExternal
Voltage - Supply, Analog3 V ~ 3.6 V
Voltage - Supply, Digital3 V ~ 3.6 V
INL/DNL (LSB)±0.25, ±1 (Max)
ArchitectureR-2R
Operating Temperature-40°C ~ 85°C
Package / Case20-SSOP (0.209", 5.30mm Width)
Supplier Device Package20-SSOP
Mounting Type-

MAX5253AEAP+T Datasheet

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For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. __________________General Description The MAX5253 combines four low-power, voltage-output, 12-bit digital-to-analog converters (DACs) and four pre- cision output amplifiers in a space-saving, 20-pin pack- age. In addition to the four voltage outputs, each amplifier’s negative input is also available to the user. This facilitates specific gain configurations, remote sensing, and high output drive capacity, making the MAX5253 ideal for industrial-process-control applica- tions. Other features include software shutdown, hard- ware shutdown lockout, an active-low reset which clears all registers and DACs to zero, a user-programmable logic output, and a serial-data output. Each DAC has a double-buffered input organized as an input register followed by a DAC register. A 16-bit serial word loads data into each input/DAC register. The serial interface is compatible with SPI™/QSPI™ and MICROWIRE™. It allows the input and DAC registers to be updated independently or simultaneously with a sin- gle software command. The DAC registers can be simultaneously updated through the 3-wire serial inter- face. All logic inputs are TTL/CMOS-logic compatible. ________________________Applications Industrial Process Controls Automatic Test Equipment Digital Offset and Gain Adjustment Motion Control Remote Industrial Controls Microprocessor-Controlled Systems ______________________________Features  Four 12-Bit DACs with Configurable Output Amplifiers  +3.0V to +3.6V Single-Supply Operation  Low Supply Current: 0.82mA Normal Operation 3µA Shutdown Mode  Reference Inputs are High Impedance in Shutdown  Available in 20-Pin SSOP  Power-On Reset Clears all Registers and DACs to Zero  SPI/QSPI and MICROWIRE Compatible  Simultaneous or Independent Control of DACs Through 3-Wire Serial Interface  User-Programmable Digital Output M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface ________________________________________________________________ Maxim Integrated Products 1 MAX5253 OUTA FBA FBB FBC FBD DAC A DAC B DAC C DAC D REFAB DAC A REGISTER A DECODE CONTROL INPUT REGISTER A DAC B REGISTER B INPUT REGISTER B DAC C REGISTER C INPUT REGISTER C DAC D REGISTER D INPUT REGISTER D 16-BIT SHIFT REGISTER SR CONTROL LOGIC OUTPUT CS DIN SCLK OUTB OUTC OUTD DOUT PDLCL VDDAGNDDGND UPO REFCD _________________________________________________________________________Functional Diagram 19-1123; Rev 1; 10/02 PART MAX5253ACPP MAX5253BCPP 0°C to +70°C 0°C to +70°C TEMP RANGE PIN-PACKAGE 20 Plastic DIP 20 Plastic DIP _________________Ordering Information Ordering Information continued at end of data sheet. Pin Configuration appears at end of data sheet. INL (LSB) ±1/2 ±1 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAX5253ACAP MAX5253BCAP 0°C to +70°C 0°C to +70°C 20 SSOP 20 SSOP ±1/2 ±1

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M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to AGND...............................................................-0.3V, +6V VDD to DGND ..............................................................-0.3V, +6V AGND to DGND..................................................................±0.3V REFAB, REFCD to AGND...........................-0.3V to (VDD + 0.3V) OUT_, FB_ to AGND...................................-0.3V to (VDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V DOUT, UPO to DGND ................................-0.3V to (VDD + 0.3V) Continuous Current into Any Pin.......................................±20mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 8.00mW/°C above +70°C) .................640mW SSOP (derate 8.00mW/°C above +70°C) ......................640mW CERDIP (derate 11.11mW/°C above +70°C).................889mW Operating Temperature Ranges MAX5253_C_P ......................................................0°C to +70°C MAX5253_E_P ...................................................-40°C to +85°C MAX5253BMJP................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Code-dependent, minimum at code 555 hex VDD = +3.0V to +3.6V (Note 1) Guaranteed monotonic CONDITIONS kΩ8RREFReference Input Resistance V0 VDD - 1.4VREFReference Input Range LSB±0.35 ±1.0INLIntegral Nonlinearity mVOffset Error ±1.0 ±6.0 LSB±4.0GEGain Error µV/VPSRRPower-Supply Rejection Ratio 300 ±0.25 ±0.5 Bits12NResolution ppm/°C1Gain-Error Tempco LSBGEGain Error ±4.0 ppm/°C6Offset-Error Tempco LSB±1.0INL Integral Nonlinearity (Note 1) LSB±1.0DNLDifferential Nonlinearity ±6.0 mVVOSOffset Error UNITSMIN TYP MAXSYMBOLPARAMETER MAX5253BC/E STATIC PERFORMANCE—ANALOG SECTION MATCHING PERFORMANCE (TA = +25°C) REFERENCE INPUT MAX5253AC/E MAX5253BMJP ±2.0

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M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) (Note 4) (Note 3) CS = VDD, DIN = 100kHz VREF = 0.67VP-P Rail-to-Rail® (Note 2) To ±1/2LSB, VSTEP = 1.25V VIN = 0V or VDD VREF = 1VP-P at 25kHz ISINK = 2mA ISOURCE = 2mA CONDITIONS mA0.82 0.98IDDSupply Current V3.0 3.6VDDSupply Voltage nV-s5Digital Crosstalk nV-s5Digital Feedthrough µs20 Start-Up Time Exiting Shutdown Mode µA0 0.1Current into FB_ V0 to VDDOutput Voltage Swing µs16Output Settling Time V/µs0.6SRVoltage Output Slew Rate V0.13 0.4VOLOutput Low Voltage VVDD - 0.5VOHOutput High Voltage kHz650Reference -3dB Bandwidth pF8CINInput Capacitance µA0.01 ±0.1IINInput Leakage Current V0.8VILInput Low Voltage dB72SINAD Signal-to-Noise Plus Distortion Ratio V2.0VIHInput High Voltage UNITSMIN TYP MAXSYMBOLPARAMETER Input code = all 0s, VREF = 1.6VP-P at 1kHz dB-84Reference Feedthrough (Note 4) µA3 20Supply Current in Shutdown µA0.01 ±1Reference Current in Shutdown Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration. Note 2: Accuracy is better than 0.5LSB for VOUT = 6mV to VDD - 80mV, guaranteed by PSR test on endpoints. Note 3: Remains operational with supply voltage as low as +2.7V. Note 4: RL = ∞, digital inputs at DGND or VDD. RL = ∞ µA0.01 ±1 OUT_ Leakage Current in Shutdown MULTIPLYING-MODE PERFORMANCE DIGITAL INPUTS DIGITAL OUTPUTS DYNAMIC PERFORMANCE POWER SUPPLIES Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

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0 -4 -8 -12 -16 -20 100 560k 1.12M 1.68M 2.24M 2.8M M A X 5 2 5 3 -0 6 R E L A T IV E O U T P U T ( d B ) REFERENCE VOLTAGE INPUT FREQUENCY RESPONSE FREQUENCY (Hz) REFAB SWEPT 0.67VP-P RL = 5kΩ CL = 100pF IN L (L S B ) -5 0 0.5 1.0 1.5 2.0 REFERENCE VOLTAGE (V) M A X 5 2 5 3 -0 1 2.5 1 0 -1 -2 -3 -4 INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE RL = 5kΩ 1000 950 900 850 800 750 700 650 600 550 500 -55 -40 -20 0 20 40 60 80 125100 M A X 5 2 5 3 -0 4 S U P P L Y C U R R E N T ( µA ) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (°C) CODE = FFF HEX __________________________________________Typical Operating Characteristics (VDD = +3.3V, TA = +25°C, unless otherwise noted.) M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface 4 _______________________________________________________________________________________ TIMING CHARACTERISTICS (VDD = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD =1.25V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. Output buffer connected in unity-gain configuration (Figure 9).) CONDITIONS tD02 SCLK Fall to DOUT Valid Propagation Delay tD01 SCLK Rise to DOUT Valid Propagation Delay ns100tCPSCLK Clock Period ns0tDHDIN Hold Time ns40tDSDIN Setup Time ns0tCSHSCLK Rise to CS Rise Hold Time ns40tCSSCS Fall to SCLK Rise Setup Time ns40tCHSCLK Pulse Width High ns40tCLSCLK Pulse Width Low UNITSMIN TYP MAXSYMBOLPARAMETER ns100tCSWCS Pulse Width High ns40tCS1CS Rise to SCLK Rise Hold Time ns40tCS0SCLK Rise to CS Fall Delay CL = 200pF CL = 200pF 120 120 ns ns

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M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface _______________________________________________________________________________________ 5 2.7 2.8 3.02.9 3.1 3.2 3.3 3.4 3.6 SUPPLY CURRENT vs. SUPPLY VOLTAGE M A X 52 53 -0 5 SUPPLY VOLTAGE (V) S U P P L Y C U R R E N T ( µA ) 3.5 1000 950 900 850 800 750 700 600 650 500 550 CODE = FFF HEX 0 -10 0.01 0.1 1 10 100 FULL-SCALE ERROR vs. LOAD -7 M A X 5 2 5 3 -0 3 LOAD (kΩ) FU L L -S C A L E E R R O R ( L S B ) -3 -4 -5 -6 -8 -9 -2 -1 ____________________________Typical Operating Characteristics (continued) (VDD = +3.3V, TA = +25°C, unless otherwise noted.) 0.50 0 0.1 1 10 100 TOTAL HARMONIC DISTORTION PLUS NOISE vs. LOAD 0.05 0.10 0.15 0.20 0.25 0.30 M A X 5 2 5 3 -0 2 FREQUENCY (kHz) T H D + N O IS E ( % ) 0.35 0.40 0.45 DAC CODE = ALL 1s REFAB = 1VP-P RL = 5kΩ CL = 100pF -100 0.5 1.6 3.8 OUTPUT FFT PLOT -60 0 M A X 5 2 5 3 -1 0 FREQUENCY (kHz) S IG N A L A M P L IT U D E ( d B ) 2.7 4.9 6.0 -20 -40 -80 VREF = 1kHz, 0.006V TO 1.6V RL = 5kΩ CL = 100pF -100 0.5 1.2 2.6 REFERENCE FEEDTHROUGH AT 1kHz -60 0 M A X 5 2 5 3 -1 1 FREQUENCY (kHz) S IG N A L A M P L IT U D E ( d B ) 1.9 3.3 4.0 -20 -40 -80 REFAB INPUT SIGNAL VREF = 1.6VP-P AT 1kHz RL = 5kΩ CL = 100pF OUTA FEEDTHROUGH

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10µs/div MAJOR-CARRY TRANSITION MAX5253-07 OUTB, AC-COUPLED 50mV/div CS 5V/div VREF = 1.25V, RL = 5kΩ, CL = 100pF 2µs/div OUTA, AC-COUPLED 10mV/div DIGITAL FEEDTHROUGH (SCLK = 100kHz) MAX5253-08 SCLK, 2V/div CS = PDL = CL = 3.3V, DIN = 0V DAC A CODE SET TO 800 HEX VREF = 1.25V, RL = 5kΩ, CL = 100pF DAC A CODE SWITCHING FROM 00B HEX TO FFF HEX DAC B CODE SET TO 800 HEX 10µs/div GND OUTB, AC COUPLED 10mV/div ANALOG CROSSTALK MAX5253-12 OUTA, 500mV/div VREF = 1.25V, RL = 5kΩ, CL = 100pF SWITCHING FROM CODE 000 HEX TO FB4 HEX OUTPUT AMPLIFIER GAIN = +2.6 10µs/div DYNAMIC RESPONSE MAX5253-13 OUTA, 500mV/div VREF = 1.25V, RL = 5kΩ, CL = 100pF M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface 6 _______________________________________________________________________________________ ____________________________Typical Operating Characteristics (continued) (VDD = +3.3V, TA = +25°C, unless otherwise noted.)

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M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface _______________________________________________________________________________________ 7 ______________________________________________________________Pin Description Serial-Data InputDIN9 Serial Clock InputSCLK10 Digital GroundDGND11 Serial-Data OutputDOUT12 User-Programmable Logic OutputUPO13 DAC B Output Amplifier FeedbackFBB5 Reference Voltage Input for DAC A and DAC BREFAB6 Clears All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.CL7 Chip-Select Input. Active low.CS8 DAC B Output VoltageOUTB4 DAC A Output VoltageOUTA3 PIN DAC A Output Amplifier FeedbackFBA2 Analog GroundAGND1 FUNCTIONNAME Power-Down Lockout. Active low. Locks out software shutdown if low.PDL14 Reference Voltage Input for DAC C and DAC DREFCD15 DAC C Output Amplifier FeedbackFBC16 DAC C Output VoltageOUTC17 DAC D Output VoltageOUTD18 DAC D Output Amplifier FeedbackFBD19 Positive Power SupplyVDD20

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M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface 8 _______________________________________________________________________________________ _______________Detailed Description The MAX5253 contains four 12-bit, voltage-output digi- tal-to-analog converters (DACs) that are easily addressed using a simple 3-wire serial interface. It includes a 16-bit data-in/data-out shift register, and each DAC has a doubled-buffered input composed of an input register and a DAC register (see Functional Diagram). In addition to the four voltage outputs, each amplifier’s negative input is available to the user. The DACs are inverted R-2R ladder networks that con- vert 12-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltage inputs. DACs A and B share the REFAB reference input, while DACs C and D share the REFCD reference input. The two reference inputs allow different full-scale output voltage ranges for each pair of DACs. Figure 1 shows a simplified circuit diagram of one of the four DACs. Reference Inputs The two reference inputs accept positive DC and AC signals. The voltage at each reference input sets the full-scale output voltage for its two corresponding DACs. The reference input voltage range is 0V to (VDD - 1.4V). The output voltages (VOUT_) are represented by a digitally programmable voltage source as: VOUT_ = (VREF x NB / 4096 ) x Gain where NB is the numeric value of the DAC’s binary input code (0 to 4095), VREF is the reference voltage, and Gain is the externally set voltage gain. The impedance at each reference input is code-depen- dent, ranging from a low value of 10kΩ when both DACs connected to the reference have an input code of 555 hex, to a high value exceeding several gigohms (leakage current) with an input code of 000 hex. Because the input impedance at the reference pins is code- dependent, load regulation of the reference source is important. The REFAB and REFCD reference inputs have a 10kΩ guaranteed minimum input impedance. When the two reference inputs are driven from the same source, the effective minimum impedance is 5kΩ. Driving the REFAB and REFCD pins separately improves reference accuracy. In shutdown mode, the MAX5253’s REFAB and REFCD inputs enter a high-impedance state with a typical input leakage current of 0.01µA. The reference input capacitance is also code depen- dent and typically ranges from 20pF with an input code of all 0s to 100pF with an input code of all 1s. Output Amplifiers All MAX5253 DAC outputs are internally buffered by pre- cision amplifiers with a typical slew rate of 0.6V/µs. Access to the inverting input of each output amplifier provides the user greater flexibility in output gain setting/ signal conditioning (see the Applications Information sec- tion). With a full-scale transition at the MAX5253 output, the typical settling time to ±1/2LSB is 16µs when loaded with 5kΩ in parallel with 100pF (loads less than 2kΩ degrade performance). The MAX5253 output amplifier’s output dynamic responses and settling performances are shown in the Typical Operating Characteristics. Shutdown Mode The MAX5253 features a software-programmable shut- down that reduces supply current to a typical value of 3µA. The power-down lockout (PDL) pin must be high to enable the shutdown mode. Writing 1100XXXXXXXXXXXX as the input-control word puts the MAX5253 in shutdown mode (Table 1). OUT_ FB_ SHOWN FOR ALL 1s ON DAC D0 D9 D10 D11 2R 2R 2R 2R 2R R R R REF_ AGND Figure 1. Simplified DAC Circuit Diagram

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In shutdown mode, the MAX5253 output amplifiers and the reference inputs enter a high-impedance state. The serial interface remains active. Data in the input regis- ters is retained in shutdown, allowing the MAX5253 to recall the output states prior to entering shutdown. Exit shutdown mode by either recalling the previous config- uration or by updating the DACs with new data. When powering up the device or bringing it out of shutdown, allow 20µs for the outputs to stabilize. Serial-Interface Configurations The MAX5253’s 3-wire serial interface is compatible with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3). The serial input word consists of two address bits and two control bits followed by 12 data bits (MSB first), as shown in Figure 4. The 4-bit address/ control code determines the MAX5253’s response out- lined in Table 1. The connection between DOUT and the serial-interface port is not necessary, but may be used for data echo. Data held in the MAX5253’s shift register can be shifted out of DOUT and returned to the microprocessor (µP) for data verification. The MAX5253’s digital inputs are double buffered. Depending on the command issued through the serial interface, the input register(s) can be loaded without affecting the DAC register(s), the DAC register(s) can be loaded directly, or all four DAC registers can be updated simultaneously from the input registers (Table 1). Serial-Interface Description The MAX5253 requires 16 bits of serial data. Table 1 lists the serial-interface programming commands. For certain commands, the 12 data bits are “don’t cares.” Data is sent MSB first and can be sent in two 8-bit packets or one 16-bit word (CS must remain low until 16 bits are transferred). The serial data is composed of two DAC address bits (A1, A0) and two control bits (C1,C0), followed by the 12 data bits D11…D0 (Figure 4). The 4-bit address/control code determines: • The register(s) to be updated • The clock edge on which data is to be clocked out through the serial-data output (DOUT) • The state of the user-programmable logic output (UPO) • If the part is to go into shutdown mode (assuming PDL is high) • How the part is configured when exiting shutdown mode M A X 5 2 5 3 +3V, Quad, 12-Bit Voltage-Output DAC with Serial Interface _______________________________________________________________________________________ 9 SCLK DIN DOUT* CS SK SO SI* I/O MAX5253 MICROWIRE PORT *THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253, BUT CAN BE USED FOR READBACK PURPOSES. Figure 2. Connections for MICROWIRE DOUT* DIN SCLK CS MISO* MOSI SCK I/O SPI/QSPI PORT SS +3.3V CPOL = 0, CPHA = 0 *THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5253, BUT CAN BE USED FOR READBACK PURPOSES. MAX5253 Figure 3. Connections for SPI/QSPI Figure 4. Serial-Data Format MSB ..................................................................................LSB 16 Bits of Serial Data Address Bits Control Bits Data Bits MSB.............................................LSB A1 A0 C1 C0 D11................................................D0 12 Data Bits 4 Address/ Control Bits

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