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Part Number MAX542BCSD+
Manufacturer Maxim Integrated
Description IC DAC 16BIT SER VOUT 5V 14-SOIC
Datasheet MAX542BCSD+ Datasheet
Package 14-SOIC (0.154", 3.90mm Width)
In Stock 658 piece(s)
Unit Price $ 15.1342 *
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MAX542BCSD+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital to Analog Converters (DAC)
Datasheet MAX542BCSD+Datasheet
Package14-SOIC (0.154", 3.90mm Width)
Number of Bits16
Number of D/A Converters1
Settling Time1µs (Typ)
Output TypeVoltage - Unbuffered
Differential OutputNo
Data InterfaceSPI
Reference TypeExternal
Voltage - Supply, Analog5V
Voltage - Supply, Digital5V
INL/DNL (LSB)±0.5, ±0.5
Operating Temperature0°C ~ 70°C
Package / Case14-SOIC (0.154", 3.90mm Width)
Supplier Device Package14-SOIC
Mounting Type-

MAX542BCSD+ Datasheet

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General Description The MAX541/MAX542 are serial-input, voltage-output, 16-bit digital-to-analog converters (DACs) that operate from a single +5V supply. They provide 16-bit perfor- mance (±1LSB INL and DNL) over temperature without any adjustments. The DAC output is unbuffered, result- ing in a low supply current of 0.3mA and a low offset error of 1LSB. The DAC output range is 0V to VREF. For bipolar opera- tion, matched scaling resistors are provided in the MAX542 for use with an external precision op amp (such as the MAX400), generating a ±VREF output swing. The MAX542 also includes Kelvin-sense con- nections for the reference and analog ground pins to reduce layout sensitivity. A 16-bit serial word is used to load data into the DAC latch. The 10MHz, 3-wire serial interface is compatible with SPI™/QSPI™/MICROWIRE™, and it also interfaces directly with optocouplers for applications requiring isola- tion. A power-on reset circuit clears the DAC output to 0V (unipolar mode) when power is initially applied. The MAX541 is available in 8-pin plastic DIP and SO packages. The MAX542 is available in 14-pin plastic DIP and SO packages. Applications High-Resolution Offset and Gain Adjustment Industrial Process Control Automated Test Equipment Data-Acquisition Systems Features  Full 16-Bit Performance Without Adjustments  +5V Single-Supply Operation  Low Power: 1.5mW  1µs Settling Time  Unbuffered Voltage Output Directly Drives 60kΩ Loads  SPI/QSPI/MICROWIRE-Compatible Serial Interface  Power-On Reset Circuit Clears DAC Output to 0V (unipolar mode)  Schmitt Trigger Inputs for Direct Optocoupler Interface M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs ________________________________________________________________ Maxim Integrated Products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VDD INV DGND LDACAGNDS AGNDF OUT RFB TOP VIEW MAX542 DIN N.C. SCLKCS REFF REFS DIP/SO DINREF SCLKCS 1 2 8 7 VDD DGNDAGND OUT MAX541 3 4 6 5 DIP/SO General Description 16-BIT DAC 16-BIT DATA LATCH SERIAL INPUT REGISTER CONTROL LOGIC MAX542 REFF REFS CS LDAC DIN SCLK AGNDS AGNDF OUT INV RFB VDD DGND RFB RINV Functional Diagrams 19-1082; Rev 2; 12/99 PART MAX541ACPA MAX541BCPA MAX541ACSA 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE 8 Plastic DIP 8 Plastic DIP 8 SO Ordering Information For free samples & the latest literature:, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. MAX541BCSA 0°C to +70°C 8 SO INL (LSB) ±1 ±2 ±1 ±2 Ordering Information continued at end of data sheet. MAX541CCPA 0°C to +70°C 8 Plastic DIP ±4 MAX541CCSA 0°C to +70°C 8 SO ±4 Functional Diagrams continued at end of data sheet.

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to DGND ...........................................................-0.3V to +6V CS, SCLK, DIN, LDAC to DGND ..............................-0.3V to +6V REF, REFF, REFS to AGND ........................-0.3V to (VDD + 0.3V) AGND, AGNDF, AGNDS to DGND........................-0.3V to +0.3V OUT, INV to AGND, DGND ......................................-0.3V to VDD RFB to AGND, DGND..................................................-6V to +6V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70°C) 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW 8-Pin SO (derate 5.88mW/°C above +70°C) .................471mW 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ...800mW 14-Pin SO (derate 8.33mW/°C above +70°C) ...............667mW 14-Pin Ceramic SB (derate 10.00mW/°C above +70°C ..800mW Operating Temperature Ranges MAX541 _C_ A/MAX542_C_D. .............................0°C to +70°C MAX541 _E_ A/MAX542_E_D............................-40°C to +85°C MAX542CMJD.................................................-55°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C MAX542, bipolar mode Unipolar mode (Note 3) 4.75V ≤ VDD ≤ 5.25V MAX542 TA = TMIN to TMAX TA = +25°C Ratio error TA = +25°C TA = TMIN to TMAX VDD = 5V TA = +25°C RFB/RINV TA = TMIN to TMAX (Note 2) CONDITIONS kΩ 9.0 RREF Reference Input Resistance (Note 4) 11.5 V2.0 3.0VREFReference Input Range PSRPower-Supply Rejection LSB±1.0 ppm/°C±0.5BZSTCBipolar Zero Tempco LSB ±10 ±0.015 Bipolar Resistor Matching 1.0 ROUTDAC Output Resistance kΩ6.25 ±0.5 ±1.0 Bits16NResolution ppm/°C±0.1Gain-Error Tempco LSB ±10 Gain Error (Note 1) ±5 ppm/°C±0.05ZSTCZero-Code Tempco LSB±0.5 ±2.0INLIntegral Nonlinearity ±0.5 ±4.0 ±1 ±2 Zero-Code Offset Error UNITSMIN TYP MAXSYMBOLPARAMETER ZSE LSB MAX54_A MAX54_B TA = TMIN to TMAX ±20 Bipolar Zero Offset Error CL = 10pF (Note 5) 25 V/µsSRVoltage-Output Slew Rate DYNAMIC PERFORMANCE—ANALOG SECTION (RL = ∞, unipolar mode) to ±1/2LSB of FS, CL = 10pF 1 µsOutput Settling Time Guaranteed monotonic LSB±0.5 ±1.0DNLDifferential Nonlinearity MAX54_C STATIC PERFORMANCE—ANALOG SECTION (RL = ∞) REFERENCE INPUT MAX542 MAX542 %

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.) TIMING CHARACTERISTICS (VDD = +5V ±5%, VREF = +2.5V, AGND = DGND = 0, CMOS inputs, TA = TMIN to TMAX, unless otherwise noted.) Note 1: Gain Error tested at VREF = 2.0V, 2.5V, and 3.0V. Note 2: ROUT tolerance is typically ±20%. Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance. Note 4: Reference input resistance is code dependent, minimum at 8555 hex. Note 5: Slew-rate value is measured from 0% to 63%. Note 6: Guaranteed by design. Not production tested. Code = 0000 hex; CS = VDD; LDAC = 0; SCLK, DIN = 0 to VDD levels Major-carry transition VIN = 0 Code = 0000 hex, VREF = 1Vp-p at 100kHz Code = 0000 hex Code = FFFF hex (Note 6) CONDITIONS mW1.5PDPower Dissipation mA0.3 1.1IDDPositive Supply Current V4.75 5.25VDDPositive Supply Range V0.40VHHysteresis Voltage pF10CINInput Capacitance mVp-p1 nVs10 nVs10DAC Glitch Impulse Digital Feedthrough µA±1IINInput Current V0.8VILInput Low Voltage V2.4VIHInput High Voltage Reference Feedthrough dB92SNRSignal-to-Noise Ratio 75 pF 120 CINReference Input Capacitance UNITSMIN TYP MAXSYMBOLPARAMETER MAX542 (Note 6) MAX542 (Note 6) CONDITIONS µs20 VDD High to CS Low (power-up delay) ns45tCLSCLK Pulse Width Low ns45tCH MHz10fCLKSCLK Frequency SCLK Pulse Width High ns50tLDACSCS High to LDAC Low Setup ns50tLDACLDAC Pulse Width ns0tDHDIN to SCLK High Hold ns40tDSDIN to SCLK High Setup ns45tCSS0CS Low to SCLK High Setup ns45tCSS1CS High to SCLK High Setup ns30tCSH0SCLK High to CS Low Hold ns45tCSH1SCLK High to CS High Hold UNITSMIN TYP MAXSYMBOLPARAMETER Code = FFFF hex MHz1BWReference -3dB Bandwidth DYNAMIC PERFORMANCE—REFERENCE SECTION STATIC PERFORMANCE—DIGITAL INPUTS POWER SUPPLY

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs 4 _______________________________________________________________________________________ __________________________________________Typical Operating Characteristics (VDD = 5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -40 -20 0 20 40 60 80 100 M A X 54 2- 01 S U P P LY C U R R EN T (m A ) SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (°C) 0.35 0.34 0.33 0.32 0.31 0.30 0.29 0.28 0 1 2 3 4 5 6 M A X 54 2- 02 S U P P LY C U R R EN T (m A ) SUPPLY CURRENT vs. REFERENCE VOLTAGE REFERENCE VOLTAGE (V) 1.0 0.6 0.2 0 -0.2 -0.6 0.8 0.4 -0.4 -0.8 -1.0 -60 -20 20 60 100 140 M A X 54 2- 03 ZE R O -C O D E O FF S ET E R R O R ( LS B ) ZERO-CODE OFFSET ERROR vs. TEMPERATURE TEMPERATURE (°C) 1.0 0.6 0.2 0 -0.2 -0.6 0.8 0.4 -0.4 -0.8 -1.0 -60 -20 20 60 100 140 M A X 54 2- 04 IN L (L S B ) INTEGRAL NONLINEARITY vs. TEMPERATURE TEMPERATURE (°C) +INL -INL 1.00 0.50 0.25 0.75 0 -0.25 -0.50 -0.75 -1.00 0 10k 20k 30k 40k 50k 60k 70k M A X 54 2- 07 IN L (L S B ) INTEGRAL NONLINEARITY vs. CODE DAC CODE 1.0 0.6 0.2 0 -0.2 -0.6 0.8 0.4 -0.4 -0.8 -1.0 -60 -20 20 60 100 140 M A X 54 2- 05 D N L (L S B ) DIFFERENTIAL NONLINEARITY vs. TEMPERATURE TEMPERATURE (°C) +DNL -DNL 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -60 -20 20 60 100 140 M A X 5 4 2 -0 6 G A IN E R R O R ( LS B ) GAIN ERROR vs. TEMPERATURE TEMPERATURE (°C) 0.25 0.75 0.50 1.00 0 -0.25 -0.50 -0.75 -1.00 0 10k 20k 30k 40k 50k 60k 70k M A X 54 2- 08 D N L (L S B ) DIFFERENTIAL NONLINEARITY vs. CODE DAC CODE 200 160 120 80 40 0 0 10k 20k 30k 40k 50k 60k 70k M A X 54 2- 09 R EF ER EN C E C U R R EN T (µ A ) REFERENCE CURRENT vs. CODE DAC CODE

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs _______________________________________________________________________________________ 5 M A X 5 4 2 -1 0 FULL-SCALE STEP RESPONSE (fSCLK = 10MHz) 2µs/div OUT 500mV/div CL = 10pF RL = ∞ 1µs/div M A X 5 4 2 -1 0 A FULL-SCALE STEP RESPONSE (fSCLK = 20MHz) 2µs/div OUT 500mV/div 400ns/div CL = 10pF RL = ∞ M A X 5 4 2 -1 1 MAJOR-CARRY OUTPUT GLITCH 2µs/div CS (5V/div) OUT (AC-COUPLED, 100mV/div) M A X 5 4 2 -1 2 DIGITAL FEEDTHROUGH 2µs/div SCLK 5V/div OUT (AC-COUPLED, 50mV/div) CODE = 0000 hex Typical Operating Characteristics (continued) (VDD = +5V, VREF = +2.5V, TA = +25°C, unless otherwise noted.) Pin Descriptions +5V Supply VoltageVDD8 Digital GroundDGND7 Serial Data InputDIN6 Serial Clock Input. Duty cycle must be between 40% and 60%.SCLK5 Chip-Select InputCS4 Voltage Reference Input. Connect to external +2.5V reference.REF3 Analog GroundAGND2 DAC Output VoltageOUT1 FUNCTIONNAMEPIN MAX541

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs 6 _______________________________________________________________________________________ ________________________________________________Pin Descriptions (continued) tCSHO tCHtCSSO tCL tDH tDS tCSH1 tCSS1 tLDACS tLDAC CS SCLK DIN LDAC* *MAX542 ONLY D15 D14 D0 Figure 1. Timing Diagram +5V Supply VoltageVDD Digital GroundDGND12 LDAC Input. A falling edge updates the internal DAC latch.LDAC11 Serial Data InputDIN10 No Connection. Not internally connected.N.C.9 Serial Clock Input. Duty cycle must be between 40% and 60%.SCLK8 Chip-Select InputCS7 Voltage Reference Input (force). Connect REFF to external +2.5V reference.REFF6 Voltage Reference Input (sense). Connect REFS to external +2.5V reference.REFS5 Analog Ground (sense)AGNDS4 Analog Ground (force)AGNDF3 DAC Output VoltageOUT2 Feedback Resistor. Connect to external op amp’s output in bipolar mode.RFB1 FUNCTIONNAMEPIN Junction of internal scaling resistors. Connect to external op amp’s inverting input in bipolar mode. INV13 14 MAX542

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs _______________________________________________________________________________________ 7 Detailed Description The MAX541/MAX542 voltage-output, 16-bit digital-to- analog converters (DACs) offer full 16-bit performance with less than 1LSB integral linearity error and less than 1LSB differential linearity error, thus ensuring monoton- ic performance. Serial data transfer minimizes the num- ber of package pins required. The MAX541/MAX542 are composed of two matched DAC sections, with a 12-bit inverted R-2R DAC forming the 12 LSBs and the 4 MSBs derived from 15 identically matched resistors. This architecture allows the lowest glitch energy to be transferred to the DAC output on major-carry transitions. It also lowers the DAC output impedance by a factor of eight compared to a standard R-2R ladder, allowing unbuffered operation in medium- load applications. The MAX542 provides matched bipolar offset resistors, which connect to an external op amp for bipolar output swings (Figure 2b). For optimum performance, the MAX542 also provides a set of Kelvin connections to the voltage-reference and analog-ground inputs. MAX542 MAX400 AGNDFDGND (GND) VDD REFF REFS RINV RFB RFB INV OUT LDAC SCLK DIN CS AGNDS 0.1µF +5V EXTERNAL OP AMP MC68XXXX PCS0 MOSI SCLK IC1 BIPOLAR OUT +5V -5V 0.1µF +2.5V 10µF Figure 2b. Typical Operating Circuit—Bipolar Output MAX541/MAX542 MAX495 DGND ( ) ARE FOR MAX542 ONLY (GND) VDD (REFS)REF (REFF) OUT SCLK DIN CS AGND_ 0.1µF 0.1µF +5V +2.5V EXTERNAL OP AMP MC68XXXX PCS0 MOSI SCLK UNIPOLAR OUT (LDAC) 10µF Figure 2a. Typical Operating Circuit—Unipolar Output

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs 8 _______________________________________________________________________________________ Digital Interface The MAX541/MAX542’s digital interface is a standard 3-wire connection compatible with SPI/QSPI/ MICROWIRE interfaces. The chip-select input (CS) frames the serial data loading at the data-input pin (DIN). Immediately following CS’s high-to-low transition, the data is shifted synchronously and latched into the input register on the rising edge of the serial clock input (SCLK). After 16 data bits have been loaded into the serial input register, it transfers its contents to the DAC latch on CS’s low-to-high transition (Figure 3a). Note that if CS is not kept low during the entire 16 SCLK cycles, data will be corrupted. In this case, reload the DAC latch with a new 16-bit word. Alternatively, for the MAX542, LDAC allows the DAC latch to update asynchronously by pulling LDAC low after CS goes high (Figure 3b). Hold LDAC high during the data-loading sequence. External Reference The MAX541/MAX542 operate with external voltage ref- erences from 2V to 3V. The reference voltage deter- mines the DAC’s full-scale output voltage. Kelvin connections are provided with the MAX542 for optimum performance. Power-On Reset The MAX541/MAX542 have a power-on reset circuit to set the DAC’s output to 0V in unipolar mode when VDD is first applied. This ensures that unwanted DAC output voltages will not occur immediately following a system power-up, such as after a loss of power. In bipolar mode, the DAC output is set to -VREF. CS SCLK DIN MSB LSB D15 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC UPDATED D14 D13 D12 D11 D10 D9 CS SCLK DIN LDAC MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC UPDATED Figure 3a. MAX541/MAX542 3-Wire Interface Timing Diagram (LDAC = DGND for MAX542) Figure 3b. MAX542 4-Wire Interface Timing Diagram

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M A X 5 4 1 /M A X 5 4 2 +5V, Serial-Input, Voltage-Output, 16-Bit DACs _______________________________________________________________________________________ 9 Applications Information Reference and Analog Ground Inputs The MAX541/MAX542 operate with external voltage ref- erences from 2V to 3V, and maintain 16-bit performance if certain guidelines are followed when selecting and applying the reference. Ideally, the reference’s temperature coeff ic ient should be less than 0.4ppm/°C to maintain 16-bit accuracy to within 1LSB over the 0°C to +70°C commercial temperature range. Since this converter is designed as an inverted R-2R voltage-mode DAC, the input resistance seen by the volt- age reference is code-dependent. The worst-case input- resistance variation is from 11.5kΩ (at code 8555 hex) to 200kΩ (at code 0000 hex). The maximum change in load current for a 2.5V reference is 2.5V / 11.5k Ω = 217µA; therefore, the required load regulation is 7ppm/mA for a maximum error of 0.1LSB. This implies a reference output impedance of less than 18mΩ. In addition, the impedance of the signal path from the voltage reference to the reference input must be kept low because it contributes directly to the load-regulation error. The requirement for a low-impedance voltage reference is met with capacitor bypassing at the reference inputs and ground. A 0.1µF ceramic capacitor with short leads between REFF and AGNDF (MAX542), or REF and AGND (MAX541), provides high-frequency bypassing. A surface-mount ceramic chip capacitor is preferred because it has the lowest inductance. An additional 10µF between REFF and AGNDF (MAX542), or REF and AGND (MAX541), provides low-frequency bypass- ing. A low-ESR tantalum, film, or organic semiconductor capacitor works well. Leaded capacitors are accept- able because impedance is not as critical at lower fre- quencies. The circuit can benefit from even larger bypassing capacitors, depending on the stability of the external reference with capacitive loading. If separate force and sense lines are not used, tie the appropriate force and sense pins together close to the package. AGND must also be low impedance, as load-regulation errors will be introduced by excessive AGND resis- tance. As in all high-resolution, high-accuracy applica- tions, separate analog and digital ground planes yield the best results. Tie DGND to AGND at the AGND pin to form the “star” ground for the DAC system. Always refer remote DAC loads to this system ground for the best possible performance. Unbuffered Operation Unbuffered operation reduces power consumption as well as offset error contributed by the external output buffer. The R-2R DAC output is available directly at OUT, allowing 16-bit performance from +VREF to AGND without degradation at zero scale. The DAC’s output impedance is also low enough to drive medium loads (RL > 60kΩ) without degradation of INL or DNL; only the gain error is increased by externally loading the DAC output. External Output Buffer Amplifier The requirements on the external output buffer amplifier change whether the DAC is used in the unipolar or bipolar mode of operation. In unipolar mode, the output amplifier is used in a voltage-follower connection. In bipolar mode (MAX542 only), the amplifier operates with the internal scaling resistors (Figure 2b). In each mode, the DAC’s output resistance is constant and is independent of input code; however, the output amplifi- er’s input impedance should still be as high as possible to minimize gain errors. The DAC’s output capacitance is also independent of input code, thus simplifying sta- bility requirements on the external amplifier. In bipolar mode, a precision amplifier operating with dual power supplies (such as the MAX400) provides the ±VREF output range. In single-supply applications, precision amplifiers with input common-mode ranges including AGND are available; however, their output swings do not normally include the negative rail (AGND) without significant degradation of performance. A single-supply op amp, such as the MAX495, is suit- able if the application does not use codes near zero. Since the LSBs for a 16-bit DAC are extremely small (38.15µV for VREF = 2.5V), pay close attention to the external amplifier’s input specification. The input offset voltage can degrade the zero-scale error and might require an output offset trim to maintain full accuracy if the offset voltage is greater than 1/2LSB. Similarly, the input bias current multiplied by the DAC output resis- tance (typically 6.25kΩ) contributes to the zero-scale error. Temperature effects also must be taken into con- sideration. Over the 0°C to +70°C commercial tempera- ture range, the offset voltage temperature coefficient (referenced to +25°C) must be less than 0.42µV/°C to add less than 1/2LSB of zero-scale error. The external amplifier’s input resistance forms a resistive divider with the DAC output resistance, which results in a gain error.

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November 11, 2020

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