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MAX8564AEUB+

hot MAX8564AEUB+

MAX8564AEUB+

For Reference Only

Part Number MAX8564AEUB+
Manufacturer Maxim Integrated
Description IC REG CTRLR DUAL POS ADJ 10UMAX
Datasheet MAX8564AEUB+ Datasheet
Package 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
In Stock 9524 piece(s)
Unit Price $ 3.89 *
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MAX8564AEUB+ Specifications

ManufacturerMaxim Integrated
CategoryIntegrated Circuits (ICs) - PMIC - Voltage Regulators - Linear Regulator Controllers
Datasheet MAX8564AEUB+ Datasheet
Package10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
Series-
TypePositive Adjustable
Number of Outputs2
Current - Supply660µA
Voltage - Input5V, 12V
Operating Temperature-40°C ~ 85°C
Package / Case10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
Supplier Device Package10-uMAX

MAX8564AEUB+ Datasheet

Page 1

Page 2

General Description The MAX8563/MAX8564/MAX8564A ultra-low-output dual and triple LDO controllers allow flexible and inexpensive point-of-load voltage conversion in motherboards, desknotes, notebooks, and other applications. These parts feature a 0.5V reference voltage with ±1% accuracy providing tight regulation of the output volt- age. The MAX8563 has three n-channel MOSFET con- troller outputs, and the MAX8564/MAX8564A has two controller outputs. Each controller output is adjustable from 0.5V to 3.3V when VDD = 12V and between 0.5V and 1.8V when VDD = 5V. Each output is independently enabled and asserts a POK signal when the output reaches 94% of the set value. Each output is protected against a soft short-circuit condition by an undervoltage comparator that disables the output when it drops to under 80% of the set voltage for more than 50µs. For a catastrophic short condition, the regulators are shut down immediately if the output drops below 60% of the set voltage. The MAX8563 is available in a 16-pin QSOP package, and the MAX8564/MAX8564A are available in a 10-pin µMAX® package. Applications Features ♦ MAX8563: 3 Outputs ♦ MAX8564/MAX8564A: 2 Outputs ♦ ±1% Feedback Regulation ♦ Adjustable Output Voltage Down to 0.5V ♦ Can Use Ceramic Output Capacitors ♦ Wide Supply Voltage Range Permits Operation from 5V or 12V Rails ♦ Individual Enable Control and POK Signal Allows Sequencing ♦ Overload Protection Against Soft Short-Circuit Condition ♦ Undervoltage Short-Circuit Protection ♦ Drive n-Channel MOSFETs M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers ________________________________________________________________ Maxim Integrated Products 1 Ordering Information 19-3290; Rev 2; 6/06 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALU ATION KIT AVAIL ABLE PART TEMP RANGE PIN- PACKAGE PKG CODE MAX8563EEE -40°C to +85°C 16 QSOP E16-1 MAX8564EUB -40°C to +85°C 10 µMAX U10-2 MAX8564AEUB+ -40°C to +85°C 10 µMAX U10-2 OFF ON OFF ON OFF ON DRV1 FB1 EN1 POK1 GND N.C. DRV3 FB3 VDD DRV2 FB2 EN2 POK2 N.C. POK3 EN3 MAX8563 1.8V ±5% IN C1 C5 R2 R1 C4 OUT1 1.5V/1.5A R3 Q1 POK1 3.3V ±5% IN OUT3 2.5V/2A* C9 C10 C8 Q3 R8 R7 R9 R6 R5 R4 C6 C2 C3 C7 Q2 OUT2 1.05V/3A POK2 POK3 5V OR 12VIN 1.2V ±5% IN *2.5V OUTPUT ONLY WITH VDD = 12V Typical Operating Circuit Pin Configurations appear at end of data sheet. µMAX is a registered trademark of Maxim Integrated Products, Inc. +Denotes lead-free package.Motherboards Dual/Triple Power Supplies Desknotes and Notebooks Graphic Cards Ultra-Low-Dropout Voltage Regulators Low-Voltage DSP, µP, and Microcontroller Power Supplies

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M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VDD to GND............................................................-0.3V to +14V DRV1, DRV2, DRV3, EN1, EN2, EN3 to GND............................................-0.3V to (VDD + 0.3V) FB1, FB2, FB3, POK1, POK2, POK3 to GND ...........-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) ........444.4mW 16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C PARAMETER CONDITIONS MIN TYP MAX UNITS GENERAL VDD Voltage Range 4.5 13.2 V VDD Undervoltage-Lockout Threshold Rising, 200mV hysteresis (typ) 3.56 3.76 4.00 V VEN_ = VDD = 12V (MAX8563) 930 1600 VDD Quiescent Current VEN_ = VDD = 12V (MAX8564/MAX8564A) 660 1200 µA VDD Shutdown Current EN1 = EN2 = EN3 = GND, VDD = 12V 25 µA LDOs TA = 0°C to +85°C 0.494 0.5 0.504 FB_ Accuracy TA = -40°C to +85°C 0.489 0.509 V TA = +25°C -100 +100 FB_ Input Bias Current TA = +85°C -8 nA MAX8563, MAX8564 100 DRV_ Soft-Start Charging Current MAX8564A 10 µA TA = 0°C to +85°C 4 DRV_ Max Sourcing Current VFB_ = 0.45V TA = -40°C to +85°C 3 7 mA TA = 0°C to +85°C 3 DRV_ Max Sinking Current VFB_ = 0.6V TA = -40°C to +85°C 1.8 7 mA VDD = 5V, VFB_ = 0.46V 4.7 DRV_ Max Voltage VDD = 13.2V, VFB_ = 0.46V 8.0 10.9 V FB_ Slow Short-Circuit Threshold Measured at FB_ (falling) 400 mV FB_ Fast Short-Circuit Threshold Measured at FB_ (falling) 300 mV Slow Short-Circuit Timer 50 µs FB_ to DRV_ Transconductance 0.115 0.24 0.460 Mho LOGIC EN_ Input Low Level 0.7 V EN_ Input High Level 1.3 V TA = +25°C -0.1 +0.1 EN_ Input Leakage Current VEN_ = 0 and VDD, VDD = 13.2V TA = +85°C 0.001 µA

Page 4

M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS POK_ Threshold Falling Measured at FB_ (falling) 425 440 455 mV POK_ Threshold Rising at Startup Measured at FB_ (rising) 455 470 485 mV POK_ Output Low Level Sinking 1mA, VDD = 4.5V, VFB_ = 0.4V 0.1 V TA = +25°C 0.1 POK_ Output High Leakage VDD = 5.5V TA = +85°C 0.001 µA Note 1: Specifications are production tested at TA = +25°C. Maximum and minimum specifications over temperature are guaranteed by design. Typical Operating Characteristics (Circuit of Figure 1, TA = +25°C.) OUTPUT VOLTAGE vs. INPUT VOLTAGE M A X 8 5 6 3 t o c0 1 INPUT VOLTAGE (V) O U TP U T V O LT A G E (V ) 1.91.81.71.61.51.41.31.21.1 1.1 1.2 1.3 1.4 1.5 1.6 1.0 1.0 2.0 VDD = 5V VOUT1 VOUT2 OUTPUT VOLTAGE vs. INPUT VOLTAGE M A X 8 5 6 3 t o c0 2 INPUT VOLTAGE (V) O U TP U T V O LT A G E (V ) 3.41.4 2.2 2.61.8 3.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 1.0 1.0 VDD = 12V VOUT3 VOUT1 VOUT2 OUTPUT VOLTAGE vs. OUTPUT CURRENT M A X 8 5 6 3 t o c0 3 OUTPUT CURRENT (A) O U TP U T V O LT A G E (V ) 2.52.01.51.00.5 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 1.0 0 3.0 VDD = 12V VOUT3 VOUT1 VOUT2 FEEDBACK VOLTAGE vs. TEMPERATURE M A X 8 5 6 3 t o c0 4 TEMPERATURE (°C) FE ED B A C K V O LT A G E (V ) 603510-15 0.4988 0.4990 0.4992 0.4994 0.4996 0.4998 0.5000 0.4986 -40 85 VDD = 5V VDD = 12V PSRR vs. FREQUENCY M A X 8 5 6 3 t o c0 5 FREQUENCY (Hz) P S R R ( dB ) 10k1k 10 30 40 20 50 60 70 80 90 100 0 100 100k VOUT1 = 1.5V VIN1 = 2V LOAD = 1.25Ω VDD = 12V LOAD TRANSIENT MAX8563 toc06 IOUT2 VDRV2 VIN2 VOUT2 20mV/div AC-COUPLED 2V/div 200mV/div AC-COUPLED 2A/div 0 10μs/div 0 VDD = 12V FIGURE 1, C7 = 100μF 6TPE100MI

Page 5

M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers 4 _______________________________________________________________________________________ Typical Operating Characteristics (continued) (Circuit of Figure 1, TA = +25°C.) POWER-ON SEQUENCING WITH VDD MAX8563 toc07 VDD VPOK1 VIN1 VOUT1 2V/div 2V/div 2V/div 20V/div 20ms/div 0 0 0 0 POWER-ON SEQUENCING WITH VIN MAX8563 toc08 VDD VPOK1 VOUT1 VIN1 2V/div 2V/div 2V/div 20V/div 10ms/div 0 0 0 0 ENABLE CONFIGURED AS SHOWN IN FIGURE 4 RD = 100kΩ, RE = 4kΩ ENABLE-ON SEQUENCING MAX8563 toc09 VIN1 VPOK1 VOUT1 EN1 2V/div 2V/div 2V/div 2V/div 20ms/div 0 0 0 0 SHORT-CIRCUIT PROTECTION MAX8563 toc10 IOUT1 VDRV1 VOUT1 5A/div 2V/div 1V/div 20μs/div 0 0 0

Page 6

M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers _______________________________________________________________________________________ 5 VDD VDD VL 0.5V POK COMPARATOR GM LDO CONTROLLER 1 LDO CONTROLLER 2 LDO CONTROLLER 3 0.5V REF VL UVLO VDD EN1 POK1 GND EN2 POK2 EN3 POK3 FB3 DRV3 DRV2 FB1 FB2 DRV1 MAX8563 MAX8564 MAX8564A Functional Diagram Pin Description NAME PIN MAX8563 MAX8564/ MAX8564A FUNCTION 1 DRV1 DRV1 Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1. DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. 2 FB1 FB1 Feed b ack Inp ut for Outp ut 1. C onnect to the center of a r esi stor - d i vi d er b etw een outp ut 1 and GN D to set the outp ut vol tag e of outp ut 1. The feed b ack r eg ul ati on vol tag e i s 0.500V . S ee the Outp ut V ol tag e S etti ng secti on. 3 EN1 EN1 Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the output. Connect to VDD for always-on operation. 4 POK1 POK1 Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the nominal regulated voltage. 5 GND GND Ground — POK2 Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the nominal regulated voltage.6 N.C. — No Internal Connection

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M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers 6 _______________________________________________________________________________________ Pin Description (continued) NAME PIN MAX8563 MAX8564/ MAX8564A FUNCTION — EN2 Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the output. Connect to VDD for always-on operation. 7 DRV3 — O utp ut 3 n- M O S FE T D r i ve. D r i ves the g ate of an exter nal n- channel M O S FE T to r eg ul ate outp ut 3. DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. — FB2 Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. 8 FB3 — Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. — DRV2 O utp ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n- channel M OS FE T to r eg ul ate outp ut 2. DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section.9 EN3 — Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the output. Connect to VDD for always-on operation. — VDD +5V or +12V Supply Input. Connect to external +5V or +12V supply rail. Bypass with a 0.1µF ceramic or larger capacitor. 10 POK3 — Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is 12% below the nominal regulated voltage. 11 N.C. — No Internal Connection 12 POK2 — Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the nominal regulated voltage. 13 EN2 — Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the output. Connect to a VDD for always-on operation. 14 FB2 — Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. 15 DRV2 — O utp ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n- channel M OS FE T to r eg ul ate outp ut 2. DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. 16 VDD — +5V or +12V Supply Input. Connect to an external +5V or +12V supply rail. Bypass with a 0.1µF ceramic or larger capacitor.

Page 8

M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers _______________________________________________________________________________________ 7 Typical Application Circuits MAX8563: Triple Output OFF ON OFF ON OFF ON DRV1 FB1 EN1 POK1 GND N.C. DRV3 FB3 VDD DRV2 FB2 EN2 POK2 N.C. POK3 EN3 MAX8563 1.8V ±5% IN C1 C5 R2 R1 C4 OUT1 1.5V/1.5A R3 Q1 POK1 3.3V ±5% IN OUT3 2.5V/2A* C9 C10 C8 Q3 R8 R7 R9 R6 R5 R4 C6 C2 C3 C7 Q2 OUT2 1.05V/3A POK2 POK3 5V OR 12VIN 1.2V ±5% IN *2.5V OUTPUT ONLY WITH VDD = 12V Figure 1. MAX8563 Typical Application Circuit

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M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers 8 _______________________________________________________________________________________ Typical Application Circuits (continued) MAX8564/MAX8564A: Dual Output Figure 2. MAX8564/MAX8564A Typical Application Circuit MAX8563 External Component List COMPONENTS QTY DESCRIPTION C1, C3, C8 3 2.2µF, 10V X5R ceramic capacitors (optional 100µF, 18mΩ, 6.3V aluminum electrolytic, Sanyo GTPE100MI in parallel) C2 1 0.1µF, 16V X7R ceramic capacitor C4, C7, C9 3 100µF, 18mΩ, 6.3V aluminum electrolytic capacitors Sanyo GTPE100MI C5, C6, C10 3 1µF, 16V X7R ceramic capacitors Q1/Q2 (dual) 1 Dual n-channel MOSFETs, 30V, 18mΩ Vishay Si4922DY Q3 1 n-channel MOSFET, 30V, 50mΩ Fairchild Semiconductor FDD6630A R1 1 665Ω ±1% resistor R2 1 620Ω ±5% resistor R3 1 332Ω ±1% resistor R4 1 390Ω ±5% resistor R5 1 182Ω ±1% resistor R6 1 165Ω ±1% resistor R7 1 910Ω ±5% resistor R8 1 1kΩ ±1% resistor R9 1 249Ω ±1% resistor MAX8564/MAX8564A External Component List COMPONENTS QTY DESCRIPTION C11 1 0.1µF, 16V X7R ceramic capacitor C12, C14 2 100µF, 18mΩ, 6.3V aluminum electrolytic capacitors Sanyo GTPE100MI C15, C17 2 2.2µF, 10V X5R ceramic capacitors (optional 100µF, 18mΩ, 6.3V aluminum electrolytic, Sanyo GTPE100MI in parallel) C18, C20 2 1µF, 16V X7R ceramic capacitors Q4/Q5 (dual) 1 Dual n-channel MOSFETs, 30V, 18mΩ Vishay Si4922DY R13 1 165Ω ±1% resistor R14 1 182Ω ±1% resistor R15 1 390Ω ±5% resistor R16 1 665Ω ±1% resistor R17 1 332Ω ±1% resistor R18 1 620Ω ±5% resistor OFF ON OFF ON DRV1 FB1 EN1 POK1 GND VDD DRV2 FB2 EN2 POK2 MAX8564 MAX8564A 1.8V ±5% IN C15 C20 R18 R16 C14 OUT1 1.5V/1.5A R17 Q4 POK1 R13 R14 R15 C18 C11 C17 C12 Q5 OUT2 1.05V/3A POK2 5V OR 12VIN 1.2V ±5% IN

Page 10

Detailed Description The MAX8563/MAX8564/MAX8564A triple and dual LDO controllers allow flexible and inexpensive voltage conversion by controlling the gate of an external n-MOSFET in a source-follower configuration. The MAX8563/MAX8564/MAX8564A consist of multiple identical LDO controllers. Each LDO controller features an enable input (EN_) and a power-OK output (POK_). The MAX8563/MAX8564/MAX8564A also include a 0.5V reference, an internal regulator, and an undervoltage lockout (UVLO). The transconductance amplifier mea- sures the feedback voltage on FB_ and compares it to an internal 0.5V reference connected to the positive input. If the voltage on FB_ is lower than 0.5V, the cur- rent output on the gate-drive output DRV_ is increased. If the voltage on FB_ is higher than 0.5V, the current out- put on the gate-drive output is decreased. Bias Voltage (VDD), UVLO, and Soft-Start The MAX8563/MAX8564/MAX8564A bias current for internal circuitry is supplied by VDD. The VDD voltage range is from 4.5V to 13.2V. If VDD drops below 3.76V (typ), the MAX8563/MAX8564/MAX8564A assume that the supply and reference voltages are too low and acti- vate the UVLO circuitry. During UVLO, the internal regu- lator (VL) and the internal bandgap reference are forced off, DRV_ is pulled to GND, and POK_ is pulled low. Before any internal startup circuitry is activated, VDD must be above the UVLO threshold. After UVLO indicates that VDD is high enough, the internal VL regulator, the internal bandgap reference, and the bias currents are activated. If EN_ is logic-high after the internal reference and bias currents are activated, then the corresponding DRV_ out- put initiates operation in soft-start mode. Once the voltage on FB_ reaches 94% of the regulation threshold, the full output current of the LDO controller is permitted. When an LDO is activated, the respective DRV_ is pulled up from GND with a typical soft-start current of DRV soft- start. The soft-start current limits the slew of the output voltage and limits the initial spike of current that the drain of the external n-MOSFET receives. The size of the com- pensation capacitor (CC) limits the slew rate (see Figure 3). This output voltage slew rate is equal to (DRV_soft- start /CC)mV/ms, where CC is in µF. The maximum startup drain current is the ratio of COUT to CC multiplied by the soft-start current. Input Voltage (Drain Voltage of the External n-MOSFET) The minimum input voltage to the drain of the n-MOSFET is a function of the desired output voltage and the dropout voltage of the n-MOSFET. Details on calculating this value are covered in the Power MOSFET Selection section. The maximum input voltage to the drain of the n-MOSFET is a function of the breakdown voltage and the thermal conditions during operation. The breakdown voltage from drain to source is normally provided in the MOSFET data sheet. The theoretical maximum input voltage is the set output voltage plus the breakdown voltage. The thermal constraint is usually the largest concern when discussing maximum input voltage. Details on calculating this value are covered in the Power MOSFET Selection section. The MOSFET package and thermal relief on the board are the largest contributors to removing heat from the n-MOSFET. Since output voltage is normally set and maximum output current is fixed, the input voltage becomes the only variable that determines the maxi- mum power dissipated. Thus, the maximum input volt- age is limited by the power capability of the n-MOSFET, if it is less than the breakdown voltage, which is most often the case. Ensure input capacitors handle the maximum input voltage. During a power-up sequence where VDD and EN_ rise before the input to the drain of the n-MOSFET, the MAX8563/MAX8564/MAX8564A drive DRV_ high but the output does not rise. As DRV_ rails and VFB_ is still below 80% of the regulation voltage, the MAX8563/MAX8564/ MAX8564A assume that an output short-circuit fault is present and shut down that regulator. To avoid this error condition, connect a resistor-divider from VDD to IN_ with the middle node connected to the respective EN_ (see Figure 4). Use the following equations to calculate the resistor values. When VIN_ is off or at a low-voltage state: When VIN_ is on or at a high-voltage state: 0 7. _ _> + ⎛ ⎝⎜ ⎞ ⎠⎟ × ( ) +−R R R V V VE E D DD IN IN M A X 8 5 6 3 /M A X 8 5 6 4 /M A X 8 5 6 4 A ±1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers _______________________________________________________________________________________ 9 DRV_ MAX8563 MAX8564 MAX8564A VIN_ CC RC COUT OUT1 Q1 Figure 3. Soft-Start and Compensation Schematic

MAX8564AEUB+ Reviews

Average User Rating
5 / 5 (126)
★ ★ ★ ★ ★
5 ★
113
4 ★
13
3 ★
0
2 ★
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0

Ali***** Rush

February 24, 2020

Super easy to replace and labelled terminals made it a quick replacement.

Aydi*****nitez

January 29, 2020

This was a useful assortment of product that filled in a parts gap that I had on my electronic workbench. Thank you.

Monse*****Goodwin

November 29, 2019

No complaints. Works perfectly every single one of them! great quality! No bent pins either!

Dann*****rris

November 21, 2019

It gives you a good quality product, with a great variety.. I will for sure order this set again when i start to run low

Dus***** Kerr

October 12, 2019

Excellent shopping cart process, various of products for selection and order fulfillment a good service quality. I rely on them heavily.

Ang*****Gross

September 15, 2019

I took time to note down but perfect after several months of use

Nola*****veri

August 27, 2019

Worked as advertised and good price. Can you imagine buying these at local store it would cost way to much.

Domin*****rghese

August 9, 2019

Fast delivery, good quality, 100% satisfacted

Jav*****Logan

August 9, 2019

Thousands of in stock parts with low cost shipping and standard quality.

Jazl*****ughes

July 23, 2019

Well packed, good item, capacitors both within 2.5% tolerance!

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hotMAX8564AEUB+ MAX864EEE+ Maxim Integrated, IC REG SWTCHD CAP INV DL 16QSOP, 16-SSOP (0.154", 3.90mm Width), - View
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