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MC33660EF

hotMC33660EF

MC33660EF

For Reference Only

Part Number MC33660EF
Manufacturer NXP
Description IC SRL LINK BUS INTERFACE 8SOIC
Datasheet MC33660EFDatasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 919 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Apr 11 - Apr 16 (Choose Expedited Shipping)
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MC33660EF

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MC33660EFSpecifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Interface - Specialized
Datasheet MC33660EFDatasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
ApplicationsAutomotive
InterfaceSerial Link Bus Interface
Voltage - Supply8 V ~ 18 V
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC
Mounting TypeSurface Mount

MC33660EFDatasheet

Page 1

Page 2

Document Number: MC33660 Rev 6.0, 7/2016 NXP Semiconductors Technical DataISO K line serial link interface The 33660 is a serial link bus interface device designed to provide bi-directional half-duplex communication interfacing in automotive diagnostic applications. It is designed to interface between the vehicle’s on-board microcontroller, and systems off-board the vehicle via the special ISO K line. The 33660 is designed to meet the Diagnostic Systems ISO9141 specification. The device’s K line bus driver’s output is fully protected against bus shorts and over-temperature conditions. The 33660 derives its robustness to temperature and voltage extremes by being built on a SMARTMOS process, incorporating CMOS logic, bipolar/MOS analog circuitry, and DMOS power FETs. Although the 33660 was principally designed for automotive applications, it is suited for other serial communication applications. It is parametrically specified over an ambient temperature range of -40 ºC ≤ TA ≤ 125 ºC and 8.0 V ≤ VBB ≤ 18 V supply. The economical SO-8 surface-mount plastic package makes the 33660 very cost effective. Features • Operates over a wide supply voltage of 8.0 V to 18 V • Operating temperature of -40 °C to 125 °C • Interfaces directly to standard CMOS microprocessors • ISO K line pin protected against shorts to battery • Thermal shutdown with hysteresis • ISO K line pin capable of high currents • ISO K line can be driven with up to 10 nF of parasitic capacitance • 8.0 kV ESD protection attainable with few additional components • Standby mode: no VBAT current drain with VDD at 5.0 V • Low current drain during operation with VDD at 5.0 V Figure 1. 33660 simplified application diagram ISO9141 PHYSICAL INTERFACE EF SUFFIX (PB-FREE) 98ASB42564B 8-PIN SOICN 33660 Applications • Farm equipment • Automotive systems • Industrial equipment • Robotic equipment • Applications where module-to-module communications are required • Marine and aircraft networks VDD ISO K-LINE TXD RXD VDD VDD RX TX GND ISOCEN VBB MCU 33660 Dx SCIRxD SCITxD +VBAT © 2016 NXP B.V.

Page 3

1 Orderable parts Table 1. Orderable part variations Part number (1) Temperature (TA) Package Parameter Symbol Condition 33660 33660B (2) MC33660EF -40 °C to 125 °C 8-SOICN VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 7637-3) VBB(5a) VBB(5b) Pulse 5a 470 ohm series resistor and 100 nF capacitor to GND on VBB Pulse 5b 470 ohm series resistor and 100 nF capacitor to GND on VBB – 45 V 82 V 45 V MC33660BEF Module Level ESD (Air Discharge, Powered) VESD4 33 V zener diode and 470 pF capacitor to GND on ISO – ±25000 V Notes 1. To order parts in tape & reel, add the R2 suffix to the part number. 2. Recommended for all new designs 2 NXP Semiconductors 33660

Page 4

2 Internal block diagram Figure 2. 33660 simplified internal block diagram Thermal Shutdown VBB 60 V CEN 10 V 125 kΩ RHYS 10 V 45 V RX ISO VDD TX 55 V 125 kΩ GND Master Bias 10 V 10 V 600 kΩ 55 kΩ 550 kΩ 110 kΩ 2.0 kΩ 20 V3.0 kΩ * Only applies to 33660B NXP Semiconductors 3 33660

Page 5

3 Pin connections 3.1 Pinout diagram Figure 3. 33660 pin connections 3.2 Pin definitions Table 2. 33660 pin definitions Pin Number Pin Name Definition 1 VBB Battery power through external resistor and diode. 2 NC Not to be connected. (3) 3 GND Common signal and power return. 4 ISO Bus connection. 5 TX Logic level input for data to be transmitted on the bus. 6 RX Logic output of data received on the bus. 7 VDD Logic power source input. 8 CEN Chip enable. Logic “1” for active state. Logic “0” for sleep state. Notes 3. NC pins should not have any connections made to them. NC pins are not guaranteed to be open circuits. 2 3 4 8 7 6 5 11 2 4 3 8 7 5 6 CEN VDD TX VBB NC GND ISO RX 4 NXP Semiconductors 33660

Page 6

4 Electrical characteristics 4.1 Maximum ratings Table 3. Maximum ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Symbol Rating Value Unit Notes VDD VDD DC Supply Voltage -0.3 to 7.0 V VBB(5a) VBB(5b) VBB Load Dump Peak Voltage (in accordance with ISO 7637-2 & ISO 7637-3) • Pulse 5a - 33660B only • Pulse 5b 82 45 V VISO ISO Pin Load Dump Peak Voltage 40 V (4) VESD1 VESD2 VESD3-1 VESD3-2 VESD4 ESD Voltage • Human Body Model • Machine Model 33660 33660B • Charge Device Model Corner Pins All other Pins • Module Level ESD (Air Discharge, Powered) 33660B only ISO pin with 33 V zener diode and 470 pF capacitor to GND - ±2000 ±150 ±200 ±750 ±500 ±25000 V (5) (6) (6) (6) (7) ECLAMP ISO Clamp Energy 10 mJ (8) TSTG Storage Temperature -55 to +150 °C TC Operating Case Temperature -40 to +125 °C TJ Operating Junction Temperature -40 to +150 °C PD Power Dissipation TA = 25 °C 100 mW TPPRT Peak Package Reflow Temperature During Reflow Note 10. °C (9), (10) RθJA Thermal Resistance: Junction-to-Ambient 150 °C/W Notes 4. Device will survive double battery jump start conditions in typical applications for 10 minutes duration, but is not guaranteed to remain within specified parametric limits during this duration. 5. ESD data available upon request. 6. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), ESD3 testing is performed in accordance with the Charge Device Model (CZAP = 4.0 pF). 7. ESD4 testing is performed in accordance with ISO 10605 ESD model (C = 330 pF, R = 2.0 kΩ). ESD discharges start at ±5.0 kV and go up to ±25 kV in increments of 5.0 kV. There are two positions for discharges: 8.0 cm cable from ISO connector, 85 cm cable from ISO connector. There are 10 ESD discharges per voltage at each cable position at a minimum of 1.0 s intervals. Remaining charge is not bled off after every discharge. 8. Nonrepetitive clamping capability at 25 °C. 9. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 10. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. NXP Semiconductors 5 33660

Page 7

4.2 Static electrical characteristics Table 4. Static electrical characteristics Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes Power and control IDD(SS) VDD Sleep State Current • Tx = 0.8 VDD, CEN = 0.3 VDD – – 0.1 mA IDD(Q) VDD Quiescent Operating Current • Tx = 0.2 VDD, CEN = 0.7 VDD – – 1.0 mA IBB(SS) VBB Sleep State Current • VBB = 16 V, Tx = 0.8 VDD, CEN = 0.3 VDD – – 50 µA IBB(Q) VBB Quiescent Operating Current • TX = 0.2 VDD, CEN = 0.7 VDD – – 1.0 mA VIH(CEN) VIL(CEN) Chip Enable • Input High Voltage Threshold • Input Low Voltage Threshold 0.7 VDD – – – – 0.3 VDD V (11) (12) IPD(CEN) Chip Enable Pull-down Current 2.0 – 40 µA (13) VIL(TX) TX Input Low Voltage Threshold • RISO = 510 Ω – – 0.3 x VDD V (14) VIH(TX) TX Input High Voltage Threshold • RISO = 510 Ω 0.7 x VDD – – V (15) IPU(TX) TX Pull-up Current -40 – -2.0 µA (16) VOL(RX) RX Output Low Voltage Threshold • RISO = 510 Ω, TX = 0.2 VDD, Rx Sinking 1.0 mA – – 0.2 VDD V VOH(RX) RX Output High Voltage Threshold • RISO = 510 Ω, TX = 0.8 VDD, RX Sourcing 250 µA 0.8 VDD – – V TLIM Thermal Shutdown 150 170 – °C (17) ISO I/O VIL(ISO) Input Low Voltage Threshold • RISO = 510 Ω, TX = 0.8 VDD – – 0.4 x VBB V VIH(ISO) Input High Voltage Threshold • RISO = 510 Ω, TX = 0.8 VDD 0.7 x VBB – – V VHYS(ISO) Input Voltage Hysteresis 0.05 x VBB – 0.1 x VBB V IPU(ISO) Internal Pull-up Current • RISO = ∞ Ω, TX = 0.8 VDD, VISO = 9.0 V, VBB = 18 V -5.0 – -140 µA ISC(ISO) Short-circuit Current Limit • RISO = 0 Ω, TX = 0.4 VDD, VISO = VBB 50 – 200 mA Notes 11. When IBB transitions to >100 µA. 12. When IBB transitions to <100 µA. 13. Enable pin has an internal current pull-down. Pull-down current is measured with CEN pin at 0.3 VDD. 14. Measured by ramping TX down from 0.8 VDD and noting TX value at which ISO falls below 0.2 VBB. 15. Measured by ramping TX up from 0.2 VDD and noting the value at which ISO rises above 0.9 VBB. 16. Tx pin has internal current pull-up. Pull-up current is measured with TX pin at 0.7 VDD. 17. Thermal Shutdown performance (TLIM) is guaranteed by design, but not production tested. 6 NXP Semiconductors 33660

Page 8

4.3 Dynamic electrical characteristics 4.4 Electrical performance curves Figure 4. ISO input threshold/VBB vs. temperature ISO I/O (Continued) VOL(ISO) Output Low Voltage • RISO = 510 Ω, TX = 0.2 VDD – – 0.1 x VBB V VOH(ISO) Output High Voltage • RISO = ∞ Ω, TX = 0.8 VDD 0.95 x VBB – – V Table 5. Dynamic electrical characteristics Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes tFALL(ISO) Fall Time • RISO = 510 Ω to VBB, CISO = 10 nF to Ground – – 2.0 µs (18) tPD(ISO) ISO Propagation Delay • High to Low: RISO = 510 Ω, CISO = 500 pF • Low to High: RISO = 510 Ω, CISO = 500 pF – – – – 2.0 2.0 µs (19) (20) (21) Notes 18. Time required ISO voltage to transition from 0.8 VBB to 0.2 VBB. 19. Changes in the value of CISO affect the rise and fall time but have minimal effect on Propagation Delay. 20. Step TX voltage from 0.8 VDD to 0.2 VDD. Time measured from VIH(Tx) until VISO reaches 0.3 VBB. 21. Step TX voltage from 0.2 VDD to 0.8 VDD. Time measured from VIL(Tx) until VISO reaches 0.7 VBB. Table 4. Static electrical characteristics (continued) Characteristics noted under conditions of 4.75 V ≤ VDD ≤ 5.25 V, 8.0 V ≤ VBB ≤ 18 V, -40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Symbol Characteristic Min. Typ. Max. Unit Notes -50 0 50 100 150 0.475 0.5 0.525 0.55 0.575 0.6 TA, AMBIENT TEMPERATURE (°C) VIH; VDD = 5.25 V, VBB = 18 V VIH; VDD = 4.75 V, VBB = 8.0 V VIL; VDD = 5.25 V, VBB = 18 V VIL; VDD = 4.75 V, VBB = 8.0 V V IL a nd V IH , I N P U T T H R E S H O LD ( R A T IO ) NXP Semiconductors 7 33660

Page 9

Figure 5. ISO output/VBB vs. temperature Figure 6. ISO fall time vs. temperature Figure 7. ISO propagation delay vs. temperature -50 0 50 100 150 TA, AMBIENT TEMPERATURE (°C) 0.65 0.7 0.75 0.8 0.85 0.9 0.95 VDD = 5.25 V, VBB = 18 V VDD = 4.75 V, VBB = 8.0 V t fa ll( IS O ), IS O F A L L T IM E ( µ s) VOH VOL TA, AMBIENT TEMPERATURE (°C) -50 0 50 100 150 0 0.2 0.4 0.6 0.8 1.0 1.2 VDD = 4.75 V, VBB = 8.0 V and VDD = 5.25 V, VBB = 18 V V O L a nd V O H , I S O O U T P U T ( R A T IO ) -50 0 50 100 150 TA, AMBIENT TEMPERATURE (°C) 0.2 0.3 0.4 0.5 0.6 0.7 PdH-L PdL-H VDD = 5.25 V, VBB = 18 V VDD = 4.75 V, VBB = 8.0 V VDD = 4.75 V, VBB = 8.0 V VDD = 5.25 V, VBB = 18 V t P D (I S O ), P R O P A G A T IO N D E LA Y ( µ s) 8 NXP Semiconductors 33660

Page 10

5 Typical applications 5.1 Introduction The 33660 is a serial link bus interface device conforming to the ISO 9141 physical bus specification. The device is designed for automotive environment usage, compliant with On-board Diagnostics (OBD) requirements set forth by the California Air Resources Board (CARB) using the ISO K line. The device does not incorporate an ISO L line. It provides bi-directional half-duplex communications interfacing from a microcontroller to the communication bus. The 33660 incorporates circuitry to interface the digital translations from 5.0 V microcontroller logic levels to battery level logic, and from battery level logic to 5.0 V logic levels. The 33660 is built using Freescale Semiconductor’s SMARTMOS process and is packaged in an 8-pin plastic SOIC. 5.2 Functional description The 33660 transforms 5.0 V microcontroller logic signals to battery level logic signals and vice versa. The maximum data rate is set by the rise and fall time. The fall time is set by the output driver. The rise time is set by the bus capacitance and the pull-up resistors on the bus. The fall time of the 33660 allows data rates up to 150 kbps using a 30 percent maximum bit time transition value. The serial link interface remains fully functional over a battery voltage range of 6.0 V to 18 V. The device is parametrically specified over a dynamic VBB voltage range of 8.0 V to 18 V. Required input levels from the microcontroller are ratio-metric with the VDD voltage normally used to power the microcontroller. This enhances the 33660’s ability to remain in harmony with the RX and TX control input signals of the microcontroller. The RX and TX control inputs are compatible with standard 5.0 V CMOS circuitry. For fault tolerant purposes the TX input from the microcontroller has an internal passive pull-up to VDD, while the CEN input has an internal passive pull-down to ground. A pull-up to battery is internally provided as well as an active data pull-down. The internal active pull-down is current-limit protected against shorts to battery, and further protected by thermal shutdown. Typical applications have reverse battery protection by the incorporation of an external 510 Ω pull-up resistor and a diode to battery. Reverse battery protection of the device is provided by the use of a reverse battery blocking diode (See “D” in the Typical application diagram on page 9). Battery line transient protection of the device is provided for by using a 45 V zener and a 500 Ω resistor connected to the VBB source, as shown in the same diagram. Device ESD protection from the communication lines exiting the module is through the use of the capacitor connected to the VBB device pin, and the capacitor used in conjunction with the 27 V zener connected to the ISO pin. Figure 8. Typical application diagram Components necessary for Reverse Battery (1), Overvoltage Transient (2), and 8.0 kV ESD Protection (3) in a metal module case. VCC Dx SCIRxD SCITxD MCU VDD CEN RX TX VBB ISO GND 500 Ω(2) D(1) ISO K Line 510 Ω Service Scan Tool or End of Production Line Programming or System Checking TxD RxD +VDD = 5.0 V 45 V(2) 27 V(3)5.0 nF(3) 33660 1.0 nF 10 nF(3) +VBATOn-Board Diagnostic Link NXP Semiconductors 9 33660

MC33660EFReviews

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Remi *****abarti

January 17, 2020

The order process is easy and user friendly, very helpful customer service, always fast shipping.

Roy*****lters

December 29, 2020

Tested one of them and works good.

Saria*****nington

December 25, 2019

Your technical assistance and professionalism cannot be complained!

Cohe*****ntura

December 22, 2019

I was able to make my list of needed parts and use suggested products. The big plus is the fact they show inventory quantity.

Caro*****Sawyer

December 16, 2019

Excellent service and product arrives in reasonable shipping rates. Well done!

Sore*****ngat

December 11, 2019

Excellent safe and secure packing. Fast ship out. Thanks

Ros*****rtega

November 17, 2019

fast delivery and good product, very happy

Andr*****uran

November 12, 2019

To be honest, you're beating your competitor on delivery - sometimes I request 2nd day and you still get it here overnight. Thanks!

Tro*****hurch

October 12, 2019

Very supportive of my small orders, but very glad easy to work with. Hard to see how it could be any more efficient!

Lan*****ranch

October 2, 2019

This product is very easy to replace and solved my problem.

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