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MCF51AG96CLH

hot MCF51AG96CLH

MCF51AG96CLH

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Part Number MCF51AG96CLH
Manufacturer NXP
Description IC MCU 32BIT 96KB FLASH 64LQFP
Datasheet MCF51AG96CLH Datasheet
Package 64-LQFP
In Stock 5612 piece(s)
Unit Price $ 5.2235 *
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MCF51AG96CLH Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet MCF51AG96CLH Datasheet
Package64-LQFP
SeriesMCF51AG
Core ProcessorColdfire V1
Core Size32-Bit
Speed50MHz
ConnectivityI2C, SCI, SPI
PeripheralsDMA, LVD, PWM, WDT
Number of I/O53
Program Memory Size96KB (96K x 8)
Program Memory TypeFLASH
RAM Size16K x 8
Voltage - Supply (Vcc/Vdd)2.7 V ~ 5.5 V
Data ConvertersA/D 19x12b
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)

MCF51AG96CLH Datasheet

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Freescale Semiconductor Data Sheet: Technical Data Document Number: MCF51AG128 Rev. 5, 6/2010 MCF51AG128 80 LQFP 14 mm × 14 mm 64 LQFP 10 mm × 10 mm 64 QFP 14 mm × 14 mm 48 LQFP 7 mm x 7mmCovers: MCF51AG128 and MCF51AG96 MCF51AG128 ColdFire MicrocontrollerThe MCF51AG128 is a member of the ColdFire® family of 32-bit variable-length reduced instruction set (RISC) microcontroller. This document provides an overview of the MCF51AG128 series MCUs, focusing on its highly integrated and diverse feature set. The MCF51AG128 derivative are low-cost, low-power, and high-performance 32-bit ColdFire V1 microcontroller units (MCUs) designed for industrial and appliance applications. It is an ideal upgrade for designs based on the MC9S08AC128 series of 8-bit microcontrollers. The MCF51AG128 features the following functional units: • 32-bit Version 1 ColdFire® central processor unit (CPU) – Up to 50.33 MHz ColdFire CPU from 2.7 V to 5.5 V – Provide 0.94 Dhrystone 2.1 DMIPS per MHz performance when running from internal RAM (0.76 DMIPS per MHz when running from flash) – Implements Coldfire Instruction Set Revision C (ISA_C) • On-chip memory – Up to 128 KB flash memory read/program/erase over full operating voltage and temperature – Up to 16 KB random access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Three ultra-low power stop modes and reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents • System Protection – Advanced independent clocked watchdog (WDOG) with features like, robust refresh mechanism, windowed mode, high granulation timeout, fast test of timeout, and always forces a reset – Additional external watchdog monitor (EWM) to help reset external circuits© Freescale Semiconductor, Inc., 2010. All rights reserved. Freescale reserves the right to change the detail specifications a improvements in the design of its products.– Low-voltage detection with reset or interrupt – Separate low voltage warning with selectable trip points – Illegal opcode and illegal address detection with reset – Flash block protection for each array to prevent accidental write/erasure – Hardware CRC module to support fast cyclic redundancy checks • Debug Support – Single-wire back ground debug interface – Real-time debug support, with six hardware breakpoints (4 PC, 1 address pair and 1 data) that can be configured into a 1- or 2-level trigger – On-chip trace buffer provides programmable start/stop recording conditions – Support for real-time program (and optional partial data) trace using the debug visibility bus • DMA Controller – Four independently programmable DMA channels provide the means to directly transfer data between system memory and I/O peripherals – DMA enabled peripherals include IIC, SCI, SPI, FTM, HSCMP, ADC, RTC, and eGPIO, and the DMA request from these peripherals can be configured as DMA source or as an iEvent input • CF1_INTC – Support of 44 peripheral I/O interrupt requests and seven software (one per level) interrupt requests – Fixed association between interrupt request source, level and priority, up to two requests can be remapped to the highest maskable level and priority – Unique vector number for each interrupt source – Support for service routine interrupt acknowledge (software IACK) read cycles for improved system performance – Ability to mask any individual or all interrupt sourcess may be required to permit

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• System Clock Sources – Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Frequency-locked-loop (FLL) controlled by internal or external reference; trimmable internal reference allows 0.2% resolution and 2% deviation (1% across 0 to 70 ºC) • Peripherals – ADC — 24 analog inputs with 12 bits resolution; output formatted in 12-, 10- or 8-bit right-justified format; single or continuous conversion (automatic return to idle after single conversion); interrupt or DMA request when conversion complete; operation in low-power modes for lower noise operation; asynchronous clock source for lower noise operation; selectable asynchronous hardware conversion triggers from RTC, PDB, or iEvent; dual samples based on hardware triggers during ping-pong mode; on-chip temperature sensor – PDB — 16-bit of resolution with prescaler; seven possible trigger events input; positive transition of trigger event signal initiates the counter; support continuous trigger or single shot, bypass mode; supports two triggered delay outputs or ORed together; pulsed output could be used for HSCMP windowing signal – iEvent — User programmable combinational boolean output using the four selected iEvent input channels for use as interrupt requests, DMA transfer requests, or hardware triggers – FTM — Two 6-channel flexible timer/PWM modules with DMA request option; deadtime insertion is available for each complementary channel pair; channels operate as pairs with equal outputs, pairs with complimentary outputs or independent channels (with independent outputs); 16-bit free-running counter; the load of the FTM registers which have write buffer can be synchronized; write protection for critical registers; backwards compatible with TPM – TPM — 16-bit free-running or modulo up/down count operation; two channels, each channel may be input capture, output compare, or edge-aligned PWM; one interrupt per channel plus terminal count interrupt – CRC — High speed hardware CRC generator circuit using 16-bit shift register; CRC16-CCITT compliancy with x16 + x12 + x5 + 1 polynomial; error detection for all single, double, odd, and most multi-bit errors; programmable initial seed value – HSCMP — Two analog comparators with selectable interrupt on rising edge, falling edge, or either edges of comparator output; the positive and negative inputs of the comparator are both driven from 4-to-1 muxes; programmable voltage reference from two internal DACs; support DMA transfer – IIC — Compatible with IIC bus standard and SMBus version 2 features; up to 100 kbps with maximum bus loading; multi-master operation; software programmable for one of 64 different serial clock frequencies; programmable slave address and glitch input filter; interrupt driven byte-by-byte data transfer; arbitration lost interrupt with automatic mode switching from master to slave; calling address identification interrupt; bus busy detection; broadcast and 10-bit address extension; address matching causes wake-up when MCU is in Stop3 mode; DMA support – SCI — Two serial communications interface modules with optional 13-bit break; full-duplex, standard non-return-to-zero (NRZ) format; double-buffered transmitter and receiver with separate enables; 13-bit baud rate selection with /32 fractional divide; interrupt-driven or polled operation; hardware parity generation and checking; programmable 8-bit or 9-bit character length; receiver wakeup by idle-line or address-mark; address match feature in receiver to reduce address-mark wakeup ISR overhead; 1/16 bit-time noise detection; DMA transmission for both transmit and receive – SPI — Two serial peripheral interfaces with full-duplex or single-wire bidirectional option; double-buffered transmitter and receiver; master or slave mode operation; selectable MSB-first or LSB-first shifting; 8-bit or 16-bit data modes; programmable transmit bit rate; receive data buffer hardware match feature; DMA transmission for transmit and receive • Input/Output – Up to 69 GPIOs and one Input-only pin – Interrupt or DMA request with selectable polarity on all input pins – Programmable glitch filter, hysteresis and configurable pull up/down device on all input pins – Configurable slew rate and drive strength on all output pins – Independent pin value register to read logic level on digital pin – Up to 16 rapid general purpose I/O (RGPIO) pins connected to the processor’s local 32-bit platform bus with set, clear, and faster toggle functionalityMCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor2

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MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor3 Table of Contents 1 MCF51AG128 Family Configurations . . . . . . . . . . . . . . . . . . . .4 1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . . .14 2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .14 2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 2.4 Electrostatic Discharge (ESD) Protection Characteristics 16 2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21 2.7 High Speed Comparator (HSCMP) Electricals . . . . . . .23 2.8 Digital to Analog (DAC) Characteristics . . . . . . . . . . . .23 2.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.10 External Oscillator (XOSC) Characteristics . . . . . . . . .27 2.11 ICS Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . . .31 2.12.3 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . .32 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions. . . . . . . . . . . . . . . . . . . . . .35 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5 Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .37 5.1 80-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .37 5.2 64-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .40 5.3 64-pin QFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.4 48-pin LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . .46 6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 List of Tables Table 1. MCF51AG128 Series Device Comparison. . . . . . . . . . .4 Table 2. MCF51AG128 Series Functional Units . . . . . . . . . . . . . .7 Table 3. Pin Availability by Package Pin-Count. . . . . . . . . . . . . .12 Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .14 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15 Table 6. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .15 Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .16 Table 9. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 17 Table 10. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 21 Table 11.HSCMP Electrical Specifications. . . . . . . . . . . . . . . . . 23 Table 12.5V 12-bit ADC Operating Conditions. . . . . . . . . . . . . . 23 Table 13.5 V 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14.Oscillator Electrical Specifications (Temperature Range = –40 to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15.ICS Frequency Specifications (Temperature Range = –40 to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.TPM/FTM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 18.SPI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . 32 Table 19.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 20.Orderable Part Number Summary. . . . . . . . . . . . . . . . 36 Table 21.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 22.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 List of Figures Figure 1.MCF51AG128 Series MCUs Block Diagram . . . . . . . . . 6 Figure 2.80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 3.64-Pin QFP and LQFP . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4.48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5.Typical IOH vs. VDD – VOH (Low Drive,PTxDSn = 0) . . 19 Figure 6.Typical IOH vs. VDD – VOH (High Drive, PTxDSn = 1) . 19 Figure 7.Typical IOL vs. VOL (Low Drive, PTxDSn = 0) . . . . . . . 20 Figure 8.Typical IOL vs. VOL (High Drive, PTxDSn = 1) . . . . . . . 20 Figure 9.Run Current at Different Conditions. . . . . . . . . . . . . . . 22 Figure 10.ADC Input Impedance Equivalency Diagram. . . . . . . 25 Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 31 Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 33 Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . . 33 Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 34 Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 34

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MCF51AG128 Family Configurations1 MCF51AG128 Family Configurations 1.1 Device Comparison The following table compares the various device derivatives available within the MCF51AG128 series MCUs. Table 1. MCF51AG128 Series Device Comparison Feature MCF51AG128 MCF51AG96 80-pin 64-pin 48-pin 80-pin 64-pin 48-pin Flash memory size (KB) 128 96 RAM size (KB) 16 ColdFire V1 core with BDM (background debug module) Yes HSCMP (analog comparator) 2 2 1 2 2 1 ADC (analog-to-digital converter) channels (12-bit) 24 19 12 24 19 12 CRC (cyclic redundancy check) Yes DAC 2 2 1 2 2 1 DMA controller 4-ch iEvent (intelligent Event module) Yes EWM (External Watchdog Monitor) Yes WDOG (Watchdog timer) Yes RTC Yes DBG (debug module) Yes IIC (inter-integrated circuit) 1 1 No 1 1 No IRQ (interrupt request input) Yes INTC (interrupt controller) Yes LVD (low-voltage detector) Yes ICS (internal clock source) Yes OSC (crystal oscillator) Yes Port I/O1 69 53 39 69 53 39 RGPIO (rapid general-purpose I/O) 16 16 15 16 16 15 SCI (serial communications interface) 2 SPI1 (serial peripheral interface) Yes SPI2 (serial peripheral interface) Yes No No Yes No No FTM1 (flexible timer module) channels 62 FTM2 channels 62MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor4

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MCF51AG128 Family Configurations1.2 Block Diagram Figure 1 shows the connections between the MCF51AG128 series pins and modules. TPM3 (timer pulse-width modulator) channels 2 Debug Visibility Bus Yes No No Yes No No 1 Up to 16 pins on Ports E and F are shared with the ColdFire Rapid GPIO module. 2 Some pins of FTMx might not be bonded on small package, therefore these channels could be used as soft timer only. Table 1. MCF51AG128 Series Device Comparison (continued) Feature MCF51AG128 MCF51AG96 80-pin 64-pin 48-pin 80-pin 64-pin 48-pinMCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 5

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MCF51AG128 Family Configurations B Figure 1. MCF51AG128 Series MCUs Block Diagram P o rt B PTB3/ADP15 PTB4/ADP14 PTB5/ADP13 PTB2ADP16 PTB1/ADP17/TPM3CH1 PTB0/ADP18/TPM3CH0 PTB6/ADP12 PTB7/ADP11 P o rt D PTD3/ADP5 PTD4/FTM2CLK/ADP2 PTD5/ADP1 PTD2/ADP6/CMP1OUT PTD1/ADP9/C1IN3 PTD0/ADP10/C1IN2 PTD6/FTM1CLK/ADP0 PTD7/ADP7 P o rt C PTC3/TxD2 PTC4/SS2 PTC5/RxD2 PTC2/ADP8 PTC1/SDA PTC0/SCL PTC6/FTM2FLT P o rt F PTF3/RGPIO11/FTM1CH5 PTF4/RGPIO12/FTM2CH0 PTF5/RGPIO13/FTM2CH1 PTF2/RGPIO10/FTM1CH4 PTF1/RGPIO9/FTM1CH3 PTF0/RGPIO8/FTM1CH2 PTF6/RGPIO14/FTM1FLT PTF7/RGPIO15 P o rt E PTE3/RGPIO3/FTM1CH1 PTE4/RGPIO4/SS1 PTE5/RGPIO5/MISO1 PTE2/RGPIO2/FTM1CH0 PTE1/RGPIO1/RxD1 PTE0/RGPIO0/TxD1 PTE6/RGPIO6/MOSI1 PTE7/RGPIO7/SPSCK1 P o rt G PTG3/ADP4 PTG4/ADP3 PTG5/EXTAL PTG2/BKPT PTG1/PSTCLK1/TPM3CH1 PTG0/PSTCLK0/TPM3CH0 PTG6/XTAL P o rt H PTH3/ADP19/FTM2CH5 PTH4/SPSCK2 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 P o rt J PTJ3/PST3 PTJ4/DDATA0//FTM2CH5 PTJ2/PST2 PTJ1/PST1 PTJ0/PST0 P o rt A PTA3/CMP2OUT PTA4/C2IN2 PTA5/C2IN3 PTA2/CIN1 PTA1/EWM_out PTA0/EWM_in PTA6/MCLK PTA7/ADP23 ADC VREFH VREFL VDDA VSSA TPMCLK FTM1* FTM1CLK SPI1 SCI1 ICS VREG SIM ColdFire V1 core Port G: EXTAL XTAL Port E: RXD1 TXD1 Port E: SS1 SPSCK1 MOSI1 MISO1 Port F: FTM1CH5 FTM1CH4 FTM1CH3 FTM1CH2 Port E: FTM1CH1 FTM1CH0 TPM3 or Port G: TPM3CH1 TPM3CH0 IIC Port C: SDA SCL SCI2 Port C: RXD2 TXD2 SPI2 Port H: SS2 SPSCK2 MOSI2 MISO2 RAM RGPIO Port F: RGPIO15 RGPIO14 RGPIO13 RGPIO12 RGPIO11 RGPIO10 RGPIO9 RGPIO8 Port E: RGPIO7 RGPIO6 RGPIO5 RGPIO4 RGPIO3 RGPIO2 RGPIO1 RGPIO0 HSCMP1 Port D: CMP1OUT CIN1 C1IN2 RTC IRQ/ VREFH VREFL VDDA VSSA KGD/MS RESET VDD VSS VSS WDOG IRQ FLASH 128 or 96 KB 16 KB OSC BDM DBG FTM2* FTM2CLK Port J: FTM2CH5 FTM2CH4 FTM2CH3 Port F: FTM2CH1 FTM2CH0 HSCMP2 Port A: CMP2OUT CIN1 C2IN2 PTH6/MISO2 PTH5/MOSI2 PTJ7/DDATA3/FTM2CH2 PTJ6/DDATA2/FTM2CH3 PTJ5/DDATA1/FTM2CH4 TPMCLK LVD CRC VBUS Port J: DDATA3- DDATA0 PST0 Port G: PSTCLK BKPT PST3- + DMA + iEvent EWM EWM_in EWM_out C1IN3 C2IN3 FTM2CH2 Port C,D,G: Port B: Port H: Port A: ADP10- ADP0 ADP11 ADP19 ADP23 ADP18- ADP22- DAC1 DAC2 Port B:MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor6

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MCF51AG128 Family Configurations1.3 Features Table 2 describes the functional units of the MCF51AG128 series. Table 2. MCF51AG128 Series Functional Units Functional Unit Function CF1Core (V1 ColdFire core) Executes programs and interrupt handlers BDM (background debug module) Provides single pin debugging interface (part of the V1 ColdFire core) DBG (debug) Provides debugging and emulation capabilities (part of the V1 ColdFire core) VBUS (debug visibility bus) Allows for real-time program traces (part of the V1 ColdFire core) SIM (system integration module) Controls resets and chip level interfaces between modules Flash (flash memory) Provides storage for program code, constants, and variables RAM (random-access memory) Provides storage for program variables RGPIO (rapid general-purpose input/output) Allows for I/O port access at CPU clock speeds VREG (voltage regulator) Controls power management across the device LVD (low-voltage detect) Monitors internal and external supply voltage levels, and generates a reset or interrupt when the voltages are too low CF1_INTC (interrupt controller) Controls and prioritizes all device interrupts ADC (analog-to-digital converter) Measures analog voltages at up to 12 bits of resolution FTM1, FTM2 (flexible timer/pulse-width modulators) Provide a variety of timing-based features TPM3 (timer/pulse-width modulator) Provides a variety of timing-based features CRC (cyclic redundancy check) Accelerates computation of CRC values for ranges of memory HSCMP1, HSCMP2 (analog comparators) Compare two analog inputs DAC1, DAC2 (digital-to-analog converter) Provide programmable voltage reference for HSCMPx IIC (inter-integrated circuit) Supports standard IIC communications protocol ICS (internal clock source) Provides clocking options for the device, including a frequency-locked loop (FLL) for multiplying slower reference clock sources OSC (crystal oscillator) Allows a crystal or ceramic resonator to be used as the system clock source or reference clock for the FLL SCI1, SCI2 (serial communications interfaces) Serial communications UARTs capable of supporting RS-232 and LIN protocols SPI1, SPI2 (8/16-bit serial peripheral interfaces) Provide 8/16-bit 4-pin synchronous serial interface DMA Provides the means to directly transfer data between system memory and I/O peripherals iEvent Highly programmable module for creating combinational boolean outputs for use as interrupt requests, DMA transfer requests, or hardware triggers EWM (External Watchdog Monitor) Additional watchdog system to help reset external circuitsMCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 7

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MCF51AG128 Family ConfigurationsWDOG (Watchdog timer) keeps a watch on the system functioning and resets it in case of its failure RTC (Real Time Counter) Provides a constant time-base with optional interrupt Table 2. MCF51AG128 Series Functional Units (continued) Functional Unit FunctionMCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor8

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MCF51AG128 Family Configurations1.4 Pin Assignments This section describes the pin assignments for the available packages. Figure 2 shows the pinout of the 80-pin LQFP. Figure 2. 80-Pin LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80-Pin LQFP PTG3/ADP4PTC0/SCL P T C 5 /R x D 2 PTD3/ADP5PTC1/SDA PTD2/ADP6/CMP1OUTIRQ/TPMCLK PTD7/ADP7PTF0/RGPIO8/FTM1CH2 PTC2/ADP8PTF1/RGPIO9/FTM1CH3 PTD1/ADP9/C1IN3PTF2/RGPIO10/FTM1CH4 PTD0/ADP10/C1IN2 PTF5/RGPIO13/FTM2CH1 PTB7/ADP11 PTF6/RGPIO14/FTM1FLT PTB6/ADP12 PTJ0/PST0 PTB5/ADP13 PTJ1/PST1 PTB4/ADP14 PTJ2/PST2 PTB3/ADP15 PTJ3/PST3 PTB2/ADP16 PTE0/RGPIO0/TxD1 PTB1/ADP17/TPM3CH1 PTE1/RGPIO1/RxD1 PTB0/ADP18/TPM3CH0 PTF3/RGPIO11/FTM1CH5 PTH3/ADP19/FTM2CH5 PTF4/RGPIO12/FTM2CH0 P T C 3 /T x D 2 P T H 6 /M IS O 2 P T H 5 /M O S I2 P T H 4 /S P C K 2 P T G 6 /X T A L V S S V D D P T G 0 /P S T C L K 0 /T P M 3 C H 0 V D D A V S S V S S A P T G 2 /B K P T P T C 4 /S S 2 P T A 0 /E W M _ in P T D 6 /F T M 1 C L K /A D P 0 P T D 5 /A D P 1 P T D 4 /F T M 2 C L K /A D P 2 V D D P T G 4 /A D P 3 P T G 1 /P S T C L K 1 /T P M 3 C H 1 PTC6/FTM2FLT PTF7/RGPIO15 PTE2/RGPIO2/FTM1CH0 PTE3/RGPIO3/FTM1CH1 PTH2/ADP20/FTM2CH4 PTH1/ADP21/FTM2CH3 PTH0/ADP22/FTM2CH2 PTA7/ADP23 R E S E T B K G D /M S V R E F H V R E F L P T A 1 /E W M _ o u t P T A 2 /C IN 1 P T A 3 /C M P 2 O U T P T A 4 /C 2 IN 2 P T A 5 /C 2 IN 3 P T A 6 /M C L K P T E 4 /R G P IO 4 /S S 1 P T E 5 /R G P IO 5 /M IS O 1 P T J 4 /D D A T A 0 /F T M 2 C H 5 P T J 5 /D D A T A 1 /F T M 2 C H 4 P T E 6 /R G P IO 6 /M O S I1 P T E 7 /R G P IO 7 /S P S C K 1 P T J 6 /D D A T A 2 /F T M 2 C H 3 P T J 7 /D D A T A 3 /F T M 2 C H 2 Note: Pin names in bold are not available in lower pin count packages. P T G 5 /E X T A L MCF51AG128 ColdFire Microcontroller, Rev. 5 Freescale Semiconductor 9

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