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MCIMX503EVM8B

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MCIMX503EVM8B

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Part Number MCIMX503EVM8B
Manufacturer NXP
Description IC MPU I.MX50 800MHZ 400MAPBGA
Datasheet MCIMX503EVM8B Datasheet
Package 400-LFBGA
In Stock 237 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 6 - Aug 11 (Choose Expedited Shipping)
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Part Number # MCIMX503EVM8B (Embedded - Microprocessors) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MCIMX503EVM8B Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MCIMX503EVM8BDatasheet
Package400-LFBGA
Seriesi.MX50
Core ProcessorARM? Cortex?-A8
Number of Cores/Bus Width1 Core, 32-Bit
Speed800MHz
Co-Processors/DSPMultimedia; NEON? SIMD
RAM ControllersLPDDR, LPDDR2, DDR2
Graphics AccelerationYes
Display & Interface ControllersLCD
Ethernet10/100 Mbps (1)
SATA-
USBUSB 2.0 + PHY (2)
Voltage - I/O1.2V, 1.875V, 2.775V, 3.0V
Operating Temperature-20°C ~ 70°C (TA)
Security FeaturesBoot Security, Cryptography, Secure JTAG
Package / Case400-LFBGA
Supplier Device Package400-MAPBGA (17x17)

MCIMX503EVM8B Datasheet

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Freescale Semiconductor Data Sheet: Technical Data Document Number: IMX50CEC Rev. 7, 10/2013 MCIMX50 Package Information Plastic Package Case 416 MAPBGA 13 x 13 mm, 0.5 mm pitch Case 416 PoPBGA 13 x 13 mm, 0.5 mm pitch Case 400 MAPBGA 17 x 17 mm, 0.8 mm pitch Ordering Information See Table 1 on page 7 for ordering information. © 2011–2013 Freescale Semiconductor, Inc. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 1 Introduction The i.MX50 applications processors are multimedia-focused products offering high-performance processing optimized for lowest power consumption. The i.MX50 processors are Freescale Energy Efficiency Solutions products. The i.MX50 is optimized for portable multimedia applications and features Freescale’s advanced implementation of the ARM Cortex-A8® core, which operates at speeds as high as 1 GHz. The i.MX50 provides a powerful display architecture, including a 2D Graphics Processing Unit (GPU) and Pixel Processing Pipeline (ePXP). Additionally, the i.MX50 includes a complete integration of the electrophoretic display function. The i.MX50 supports DDR2, LPDDR2, and LPDDR1 DRAM at clock rate up to 266 MHz to enable a range of performance and power trade-offs. The flexibility of the i.MX50 architecture allows it to be used in a variety of applications. As the heart of the i.MX50 Applications Processors for Consumer Products 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 1.4. Part Number Feature Comparison . . . . . . . . . . . . . 8 1.5. Package Feature Comparison . . . . . . . . . . . . . . . . 9 2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. Special Signal Considerations . . . . . . . . . . . . . . . 17 4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 21 4.2. Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4. Output Buffer Impedance Characteristics . . . . . . 37 4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 48 4.7. External Interface Module (EIM) . . . . . . . . . . . . . . 60 4.8. DRAM Timing Parameters . . . . . . . . . . . . . . . . . . 68 4.9. External Peripheral Interfaces . . . . . . . . . . . . . . . 73 5. Package Information and Contact Assignments . . . . . 101 5.1. 13 x 13 mm, 0.5 mm Pitch, 416 Pin MAPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.2. 13 x 13 mm, 0.5 mm Pitch, 416 Pin PoPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3. 17 x 17 mm, 0.8 mm Pitch, 400 Pin MAPBGA Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.4. Signal Assignments . . . . . . . . . . . . . . . . . . . . . . 124 6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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i.MX50 Applications Processors for Consumer Products, Rev. 7 Introduction Freescale Semiconductor2 application chipset, the i.MX50 provides a rich set of interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, and displays. 1.1 Product Overview The i.MX50 is designed to enable high-tier portable applications by satisfying the performance requirements of advanced operating systems and applications. 1.1.1 Dynamic Performance Scaling Freescale’s dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant power reduction. 1.1.2 Multimedia Processing Powerhouse The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level cache system, a NEON™ coprocessor with SIMD media processing architecture and 32-bit single-precision floating point support, and two vector floating point coprocessors. The system is further enhanced by a programmable smart DMA (SDMA) controller. 1.1.3 Powerful Display System The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper). The display subsystem consists of the following modules: • Electrophoretic Display Controller (EPDC) (i.MX508 only) The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD controller. It is specifically designed to drive E-INKTM EPD panels, supporting a wide variety of TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this functionality for e-paper applications, allowing a significant bill of materials cost savings over an external solution while reaching much higher levels of performance and lower power. The EPDC module is defined in the context of an optimized hardware/software partitioning and works in conjunction with the ePXP (see Section 1.1.4, “Graphics Accelerators”). • Enhanced LCD Controller Interface (eLCDIF) The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart panels. The module also supports synchronous operation with the ePXP to allow the processed frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF can support up to 32-bit interfaces. 1.1.4 Graphics Accelerators Integrated graphics accelerators offload processing from the ARM processor, enabling high performance graphic applications at minimum power.

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Introduction i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 3 • Pixel Processing Pipeline (ePXP) The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma mapping, and rotation. The ePXP is enhanced with features specifically for grayscale applications working in conjunction with the electrophoretic display controller to form a full grayscale display solution. In addition, the ePXP supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with the integrated LCD controller (eLCDIF). • Graphics acceleration The i.MX50 provides a 2D graphics accelerator with performance up to 200 Mpix/s. 1.1.5 Multilevel Memory System The multilevel memory system of the i.MX50 is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The i.MX50 supports many types of external memory devices, including DDR2, LPDDR2, LPDDR1, NOR Flash, PSRAM, Cellular RAM, NAND Flash (MLC and SLC) and OneNAND™, and managed NAND including eMMC up to rev. 4.4. 1.1.6 Smart Speed™ Technology The i.MX50 device has power management throughout the SOC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart Speed technology enables the designer to deliver a feature-rich product that requires levels of power that are far less than industry expectations. 1.1.7 Interface Flexibility The i.MX50 supports connection to a variety of interfaces, including an LCD controller for displays, two high-speed USB on-the-go-capable PHYs, multiple expansion card ports (high-speed MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces (for example, UART, I2C, and I2S serial audio). 1.1.8 Advanced Security The i.MX50 delivers hardware-enabled security features, such as High-Assurance Boot 4 (HAB4) for signed/authenticated firmware images, basic DRM support with random private keys and AES encryption/decryption, and storage and programmability of on-chip fuses. 1.2 Features The i.MX50 applications processor is based on the ARM Cortex-A8 platform and has the following features: • MMU, L1 instruction cache, and L1 data cache • Unified L2 cache • 800 MHz or 1 GHz target frequency of the core (including NEON, VFPv3, and L1 cache)

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i.MX50 Applications Processors for Consumer Products, Rev. 7 Introduction Freescale Semiconductor4 • NEON coprocessor (SIMD Media Processing Architecture) and Vector Floating Point (VFP-Lite) coprocessor supporting VFPv3 The memory system consists of the following components: • Level 1 cache: — Instruction (32 Kbyte) — Data (32 Kbyte) • Level 2 cache: — Unified instruction and data (256 Kbyte) • Level 2 (internal) memory: — Boot ROM, including HAB (96 Kbyte) — Internal multimedia/shared, fast access RAM (128 Kbyte) • External memory interfaces: — 16/32-bit DDR2-533, LPDDR2-533, or LPDDR1-400 up to a total of 2 GByte — 8-bit NAND SLC/MLC Flash with up to 100 MHz synchronous clock rate and up to 32-bit hardware ECC for 1 Kbyte block size — 16/32-bit NOR Flash with a dedicated 16-bit muxed-mode interface. I/O muxing logic selects EIMv2 port as primary muxing at system boot. — 16-bit PSRAM, Cellular RAM — Managed NAND, including eMMC up to rev 4.4 The i.MX50 introduces a next generation system bus fabric architecture that aggregates various sub-system buses and masters for access to system peripherals and memories. The various bus-systems and components are as follows: • 64-bit AXI Fabric (266 MHz)—This bus-fabric is the SoC’s central bus aggregation point. — Provides access to all slave targets in the SoC: – ROM (ROMCP) – On-chip RAM (OCRAM) – External DRAM (DRAM MC) – External static RAM (EIM) – Interrupt controller (TZIC) – Decode into the AHB MAX crossbar second level AHB fabric. — Provides arbitration to the following masters in the system: – ARM CPU complex – Pixel processing pipeline (ePXP) – Electrophoretic display controller (EPDC) – eLCDIF LCD display controller – DCP Crypto engine – BCH ECC engine – MAX AHB crossbar

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Introduction i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 5 – GPU 2D – SDMA – USBOH1 (USB OTG and host controller complex) – FEC Ethernet controller • MAX AHB crossbar (133 MHz)—This connects the various AHB bus sub-segments in the system and provides decode into the following slaves: — IP-Bus 1 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability — IP-Bus 2 (66 MHz)—This bus segment contains peripherals accessible by the ARM core and without DMA capability — APBH DMA bridge (133 MHz)—The APBH DMA bridge is a master to the MAX for its memory-side DMA operations. The APBH bus is an AMBA APB slave bus providing peripheral access to many of the high-speed IP blocks on the i.MX50. • IP-Bus 3 (66 MHz)—This third peripheral bus segment contains peripherals accessible by the ARM core and SDMA and as such houses peripherals with DMA capability. The IP-Bus 3 can be accessed by the ARM CPU through IP-Bus 1 and SPBA. • Quality of service controller (QoSC)—This provides both soft and dynamic arbitration/priority control. The QoSC works in conjunction with the critical display modules such as the eLCDIF and EPDC to provide dynamic priority control, based on real-time metrics. The i.MX50 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption, while freeing up the CPU core for other tasks. The i.MX50 incorporates the following hardware accelerators: • GPU2Dv1—2D Graphics accelerator, OpenVG 1.1, 200 Mpix/s performance • ePXP—enhanced PiXel Processing Pipeline off loading key pixel processing operations required to support both LCD and EPD display applications The i.MX50 includes the following interfaces to external devices: NOTE Not all the interfaces are available simultaneously depending on I/O multiplexer configuration. • Displays: — EPDC (i.MX508 Only)—Supporting direct-driver TFT backplanes beyond 2048 × 1536 at 106 Hz refresh (or 4096 × 4096 at 20 Hz) — eLCDIF—Supporting beyond SXGA + (1400 × 1050) at 60 Hz resolutions with up to a 32-bit display interface — On the i.MX508, both displays can be active simultaneously. If both displays are active, the eLCDIF only provides a 16-bit interface due to pin muxing. • Expansion cards: — Four SD/MMC card

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i.MX50 Applications Processors for Consumer Products, Rev. 7 Introduction Freescale Semiconductor6 • USB: — One High Speed (HS) USB 2.0 OTG-capable port with integrated HS USB PHY — One High Speed (HS) USB 2.0 host port with integrated HS USB PHY • Miscellaneous interfaces: — One-wire (OWIRE) port — Two I2S/SSI/AC97 ports, supporting up to 1.4 Mbps each connected to the Audio Multiplexer (AUDMUX) providing four external ports — Five UART RS232 ports, up to 4.0 Mbps each — Two eCSPI (Enhanced CSPI) ports, up to 66 Mbps each plus CSPI port, up to 16.6 Mbps — Three I2C ports, supporting 400 kbps — Fast Ethernet controller IEEE 802.3, 10/100 Mbps — Key pad port (KPP) — Two pulse width modulators (PWM) — GPIO with interrupt capabilities — Secure JTAG controller (SJC) The system supports efficient and smart power control and clocking: • Supporting DVFS techniques for low power modes, including auto slow architecture • Power gating-SRPG (state retention power gating) for ARM core and NEON • Support for various levels of system power modes • Flexible clock gating control scheme • On-chip temperature monitor • On-chip 32 kHz and 24 MHz oscillators • A total of four PLLs with the fourth PLL providing up to eight independently controllable outputs, improving the ease of clocking control, especially for display and connectivity modules Security functions are enabled and accelerated by the following hardware: • Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features • Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches • Advanced high assurance boot (A-HAB)—HAB with the next embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

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Introduction i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 7 1.3 Ordering Information Table 1 provides the ordering information. Table 1. Ordering Information Part Number Maximum ARM CLK Frequency Mask Set Features Temperature Range (°C) Package1 1 Case MAPBGA is RoHS compliant, lead-free MSL (Moisture Sensitivity Level) 3. Tambient Tjunction MCIMX508CVK1B 1 GHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX508CVM1B 1 GHz N78A Full Specification 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX508CVK8B 800 MHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX508CZK8B 800 MHz N78A Full Specification 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 PoPBGA MCIMX508CVM8B 800 MHz N78A Full Specification 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVM1B 1 GHz N78A No GPU 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVK1B 1 GHz N78A No GPU 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX507CVM8B 800 MHz N78A No GPU 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX507CVK8B 800 MHz N78A No GPU 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX503CVK8B 800 MHz N78A No EPD controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX503CVM8B 800 MHz N78A No EPD controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX503EVM8B 800 MHz N78A No EPD controller, Extended Temperature -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX502CVK8B 800 MHz N78A No GPU, no EPD controller 0 to 70 0 to 90 13 x 13 mm, 0.5 mm pitch BGA Case: 416 MAPBGA MCIMX502CVM8B 800 MHz N78A No GPU, no EPD controller 0 to 70 0 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA MCIMX502EVM8B 800 MHz N78A No GPU, no EPD controller, Extended Temperature -20 to 70 -20 to 90 17 x 17 mm, 0.8 mm pitch BGA Case: 400 MAPBGA

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i.MX50 Applications Processors for Consumer Products, Rev. 7 Introduction Freescale Semiconductor8 1.4 Part Number Feature Comparison Table 2 provides an overview of the feature differences between the i.MX50 part numbers. Table 2. Part Number Feature Comparison Part Number Disabled Features Comments MCIMX508 None MCIMX507 GPU MCIMX503 EPDC The i.MX503 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist on the i.MX503, but because the EPDC block is disabled, those pins cannot be used for EPDC functionality (ALT0) and must be configured in the IOMUX with another ALT-mode setting. MCIMX502 GPU, EPDC The i.MX502 has the same ball map and IOMUX as the i.MX508. The EPDC pins still exist on the i.MX502, but because the EPDC block is disabled, those pins cannot be used for EPDC functionality (ALT0) and must be configured in the IOMUX with another ALT-mode setting.

Page 10

Introduction i.MX50 Applications Processors for Consumer Products, Rev. 7 Freescale Semiconductor 9 1.5 Package Feature Comparison Table 3 provides an overview of the feature and pin differences between the i.MX50 packages. Table 3. Package Feature Comparison Package Dimensions I/O Pin Differences Versus 416 MAPBGA Notes on Package Differences 416 MAPBGA 13 x 13 mm, 0.5 mm pitch — • USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 MAPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 MAPBGA package substrate. 416 PoPBGA 13 x 13 mm, 0.5 mm pitch Deleted Pins: DRAM_A10 DRAM_A11 DRAM_A12 DRAM_A13 DRAM_A14 DRAM_CAS DRAM_OPEN DRAM_OPENFB DRAM_RAS DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_SDCLK_1 DRAM_SDCLK_1_B DRAM_SDODT0 DRAM_SDODT1 DRAM_SDWE DRAM_OPEN DRAM_OPENFB Added Pins: POP_EMMC_RST POP_LPDDR2_ZQ0 POP_LPDDR2_ZQ1 POP_LPDDR2_1.8V POP_NAND_VCC • The i.MX50 PoPBGA package supports 168-FBGA LPDDR2 DRAM memory only. It is not possible to support LPDDR1 or DDR2 on the i.MX50 PoPBGA. • i.MX50 PoPBGA was designed to accommodate a combined LPDDR2 / eMMC PoP memory. The PoP eMMC device uses the SD3_DATA[7:0], SD3_CLK, and SD3_CMD pins. Because the PoP eMMC I/O and memory supplies are tied together on the substrate, 1.8 V eMMC I/O operation is not supported for the PoP eMMC device. POP_NAND_VCC and NVCC_NANDF must use a 3 V supply. • The NVCC_EMI_DRAM power pins supply 1.2 V power to the i.MX50 DRAM controller as well as the PoP LPDDR2 DRAM. • Additional PoP package pin descriptions may be found in the Special Signals Considerations section (Table 5). • On the PoPBGA package, the DRAM Address, Data, and clock pins are routed to the bottom balls for Freescale test purposes only. It is recommended that these bottom DRAM pins are left unconnected on the customer PCB. • USB_OTG_VDDA25 and USB_H1_VDDA25 are shorted together on the 416 PoPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are shorted together on the 416 PoPBGA package substrate. 400 MAPBGA 17 x 17 mm, 0.8 mm pitch Deleted Pins: DRAM_SDCLK_1 DRAM_SDCLK_1_B DRAM_A14 DRAM_SDODT1 UART2_CTS UART2_RTS • USB_OTG_VDDA25 and USB_H1_VDDA25 are independent and NOT shorted together on the 400 MAPBGA package substrate. • USB_OTG_VDDA33 and USB_H1_VDDA33 are independent and NOT shorted together on the 400 MAPBGA package substrate.

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Sari*****urley

July 14, 2020

I had no problems with this product. Would I recommend it. Yes.

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July 12, 2020

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Brynl*****fferson

July 12, 2020

So easy to do business with Heisener and they generally have stock on the items we need.

Roge*****Sahni

July 5, 2020

These are great for projects with the kids or doing any type of DIY projects. The case is nice to keep everything separated. Very nice.

Mala*****eber

July 4, 2020

They worked great. Not much to say - as far as I can tell they adhere to the specs, and did the job I needed them to. Good transistors for higher current situations.

Kimbe*****incent

July 2, 2020

Those components are in stock shipped fast and arrive promptly. Really Fast!

Laure*****terson

June 15, 2020

Thanks a lot! Ease of ordering and I love when they upgrade my shipping for free. What a nice thing to do.

Prin***** Ortiz

June 8, 2020

Very good contact, well packed, hope to buy from you again.

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June 4, 2020

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Jer***** King

June 2, 2020

DELIVERY AND COMMUNICATION EXTRA SELLER TOP 5 STARS on my list

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