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MCIMX6S5EVM10AC

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MCIMX6S5EVM10AC

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Part Number MCIMX6S5EVM10AC
Manufacturer NXP
Description IC MPU I.MX6S 1.0GHZ 624MAPBGA
Datasheet MCIMX6S5EVM10AC Datasheet
Package 624-LFBGA
In Stock 272 piece(s)
Unit Price $ 29.0300 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 15 - Jul 20 (Choose Expedited Shipping)
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Part Number # MCIMX6S5EVM10AC (Embedded - Microprocessors) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MCIMX6S5EVM10AC Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MCIMX6S5EVM10ACDatasheet
Package624-LFBGA
Seriesi.MX6S
Core ProcessorARM? Cortex?-A9
Number of Cores/Bus Width1 Core, 32-Bit
Speed1.0GHz
Co-Processors/DSPMultimedia; NEON? SIMD
RAM ControllersLPDDR2, LVDDR3, DDR3
Graphics AccelerationYes
Display & Interface ControllersKeypad, LCD
Ethernet10/100/1000 Mbps (1)
SATA-
USBUSB 2.0 + PHY (4)
Voltage - I/O1.8V, 2.5V, 2.8V, 3.3V
Operating Temperature-20°C ~ 105°C (TJ)
Security FeaturesARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC, Tamper Detection
Package / Case624-LFBGA
Supplier Device Package624-MAPBGA (21x21)

MCIMX6S5EVM10AC Datasheet

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NXP Semiconductors Data Sheet: Technical Data Document Number: IMX6SDLCEC Rev. 7, 10/2016 MCIMX6SxExxxxxB MCIMX6SxExxxxxC MCIMX6UxExxxxxB MCIMX6UxExxxxxC MCIMX6SxDxxxxxB MCIMX6SxDxxxxxC MCIMX6UxDxxxxxB MCIMX6UxDxxxxxC Package Information Plastic Package BGA Case 2240 21 x 21 mm, 0.8 mm pitch Ordering Information See Table 1 on page 3 © 2012-2016 NXP B.V. 1 Introduction The i.MX 6Solo/6DualLite processors represent the latest achievement in integrated multimedia-focused products offering high performance processing with lower cost, as well as optimization for low power consumption. The processors feature advanced implementation of single/dual ARM® Cortex®-A9 core, which operates at speeds of up to 1 GHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 32/64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth®, GPS, hard drive, displays, and camera sensors. The i.MX 6Solo/6DualLite processors are specifically useful for applications such as: • Web and multimedia tablets i.MX 6Solo/6DualLite Applications Processors for Consumer Products 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 Updated Signal Naming Convention . . . . . . . . . . . .9 2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Special Signal Considerations . . . . . . . . . . . . . . . .21 3.2 Recommended Connections for Unused Analog Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .23 4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . .23 4.2 Power Supplies Requirements and Restrictions. . .33 4.3 Integrated LDO Voltage Regulator Parameters . . .34 4.4 PLL’s Electrical Characteristics. . . . . . . . . . . . . . . .37 4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . .38 4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .39 4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . .44 4.8 Output Buffer Impedance Parameters . . . . . . . . . .48 4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . .51 4.10 General-Purpose Media Interface (GPMI) Timing .63 4.11 External Peripheral Interface Parameters. . . . . . . .71 5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . .133 5.1 Boot Mode Configuration Pins . . . . . . . . . . . . . . .133 5.2 Boot Device Interface Allocation. . . . . . . . . . . . . .134 6 Package Information and Contact Assignments . . . . . .135 6.1 Updated Signal Naming Convention . . . . . . . . . .135 6.2 21x21 mm Package Information. . . . . . . . . . . . . .136 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 2 NXP Semiconductors Introduction • Web and multimedia tablets • Color eReaders • IPTV • Human Machine Interfaces (HMI) • Portable medical • IP phones • Home energy management systems The i.MX 6Solo/6DualLite applications processors feature: • Applications processors—The processors enhance the capabilities of high-tier portable applications by fulfilling the ever increasing MIPS requirements of operating systems and games. The Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks, such as audio decode. • Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processors support many types of external memory devices, including DDR3, low voltage DDR3, LPDDR2, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND, including eMMC up to rev 4.4/4.41. • Smart speed technology—The processors have power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product, requiring levels of power far lower than industry expectations. • Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices by scaling the voltage and frequency to optimize performance. • Multimedia powerhouse—The multimedia performance of each processor is enhanced by a multilevel cache system, NEON™ MPE (Media Processor Engine) co-processor, a multi-standard hardware video codec, an image processing unit (IPU), a programmable smart DMA (SDMA) controller, and an asynchronous sample rate converter. • Powerful graphics acceleration—Each processor provides two independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator with a shader and a 2D graphics accelerator. • Interface flexibility—Each processor supports connections to a variety of interfaces: LCD controller for up to two displays (including parallel display, HDMI1.4, MIPI display, and LVDS display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100/1000 Mbps Gigabit Ethernet controller two CAN ports, ESAI audio interface, and a variety of other popular interfaces (such as UART, I2C, and I2S serial audio, and PCIe-II). • Eink Panel Display Controller—The processors integrate EPD controller that supports E-INK color and monochrome with up to 1650x2332 resolution and 5-bit grayscale (32-levels per color channel).

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Introduction i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 NXP Semiconductors 3 • Advanced security—The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. The security features are discussed in detail in the i.MX 6Solo/6DualLite Security Reference Manual (IMX6DQ6SDLSRM). • Integrated power management—The processors integrate linear regulators and internally generate voltage levels for different domains. This significantly simplifies system power management structure. 1.1 Ordering Information Table 1 provides examples of orderable part numbers covered by this data sheet. Table 1 does not include all possible orderable part numbers. The latest part numbers are available on the web page nxp.com/imx6series. If the desired part number is not listed in Table 1, go to nxp.com/imx6series or contact a NXP representative for details. Table 1. Example Orderable Part Numbers Part Number i.MX6 CPU Solo/ DualLite Options Speed Grade1 Temperature Grade Package MCIMX6U8DVM10AB DualLite With VPU, GPU, EPDC, MLB 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U8DVM10AC DualLite With VPU, GPU, EPDC, MLB 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U5DVM10AB DualLite With VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U5DVM10AC DualLite With VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA SCIMX6U5DVM10CB DualLite HDCP enabled with VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA SCIMX6U5DVM10CC DualLite HDCP enabled with VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U5EVM10AB DualLite With VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Extended Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6U5EVM10AC DualLite With VPU, GPU, MLB, no EPDC 2x ARM Cortex-A9 64-bit DDR 1 GHz Extended Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S8DVM10AB Solo With VPU, GPU, MLB, EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S8DVM10AC Solo With VPU, GPU, MLB, EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S5DVM10AB Solo With VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S5DVM10AC Solo With VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 4 NXP Semiconductors Introduction Figure 1 describes the part number nomenclature to identify the characteristics of a specific part number (for example, cores, frequency, temperature grade, fuse options, and silicon revision). The primary characteristic that differentiates which data sheet applies to a specific part is the temperature grade (junction) field. The following list describes the correct data sheet to use for a specific part: • The i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors data sheet (IMX6SDLAEC) covers parts listed with an “A (Automotive temp)” • The i.MX 6Solo/6DualLite Applications Processors for Consumer Products data sheet (IMX6SDLCEC) covers parts listed with a “D (Commercial temp)” or “E (Extended Commercial temp)” • The i.MX 6Solo/6DualLite Applications Processors for Industrial Products data sheet (IMX6SDLIEC) covers parts listed with “C (Industrial temp)” For more information go to nxp.com/imx6series or contact a NXP representative for details. SCIMX6S5DVM10CB Solo HDCP enabled with VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA SCIMX6S5DVM10CC Solo HDCP enabled with VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S5EVM10AB Solo With VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Extended Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA MCIMX6S5EVM10AC Solo With VPU, GPU, MLB, no EPDC 1x ARM Cortex-A9 32-bit DDR 1 GHz Extended Commercial 21 mm x 21 mm, 0.8 mm pitch, MAPBGA 1 If a 24 MHz input clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz. Table 1. Example Orderable Part Numbers (continued) Part Number i.MX6 CPU Solo/ DualLite Options Speed Grade1 Temperature Grade Package

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Introduction i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 NXP Semiconductors 5 Figure 1. Part Number Nomenclature—i.MX 6Solo and 6DualLite Figure 2. Example Part Marking for Revision 1.2/1.3 Devices 1.2 Features The i.MX 6Solo/6DualLite processors are based on ARM Cortex-A9 MPCore Platform, which has the following features: • The i.MX 6Solo supports single ARM Cortex-A9 MPCore (with TrustZone) • The i.MX 6DualLite supports dual ARM Cortex-A9 MPCore (with TrustZone) • The core configuration is symmetric, where each core includes: — 32 KByte L1 Instruction Cache — 32 KByte L1 Data Cache — Private Timer and Watchdog Temperature Tj + Commercial: 0 to + 95°C D Extended commercial: -20 to + 105°C E Industrial: -40 to +105°C C Automotive: -40 to + 125°C A Frequency $$ 800 MHz2 08 1 GHz3 10 Package type RoHS MAPBGA 21 x 21 0.8mm VM Qualification level MC Prototype Samples PC Mass Production MC Special SC Part # series X i.MX 6DualLite 2x ARM Cortex-A9, 64-bit DDR U i.MX 6Solo 1x ARM Cortex-A9, 32-bit DDR S Silicon revision1 A Rev 1.1 B Rev 1.2 (Maskset ID: 2N81E) Rev 1.3 (Maskset ID: 3N81E) C Fusing % Default settings A HDCP enabled C MC IMX6 X @ + VV $$ % A 1. See the nxp.com\imx6series Web page for latest information on the available silicon revision. 2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz. 3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz. Part differentiator @ Consumer VPU GPU EPDC MLB 8 Industrial VPU GPU – – 7 Automotive VPU GPU – MLB 6 Consumer VPU GPU – MLB 5 Automotive – GPU – MLB 4 Automotive – – – MLB 1 (FSL Logo) MCIMX6U5EVM10AC AWLYYWW MMMMM CCCCC YWWLAZ Device orderable part number Maskset ID (only on Rev 1.2/Rev 1.3) (company l go)

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 6 NXP Semiconductors Introduction — Cortex-A9 NEON MPE (Media Processing Engine) Co-processor The ARM Cortex-A9 MPCore complex includes: • General Interrupt Controller (GIC) with 128 interrupt support • Global Timer • Snoop Control Unit (SCU) • 512 KB unified I/D L2 cache: — Used by one core in i.MX 6Solo — Shared by two cores in i.MX 6DualLite • Two Master AXI bus interfaces output of L2 cache • Frequency of the core (including NEON and L1 cache), as per Table 8. • NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64-bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating point execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components: — Boot ROM, including HAB (96 KB) — Internal multimedia / shared, fast access RAM (OCRAM, 128 KB) — Secure/non-secure RAM (16 KB) • External memory interfaces: The i.MX 6Solo/6DualLite processors support latest, high volume, cost effective handheld DRAM, NOR, and NAND Flash memory standards. — 16/32-bit LP-DDR2-800, 16/32-bit DDR3-800 and DDR3L-800 in i.MX 6Solo; 16/32/64-bit LP-DDR2-800, 16/32/64-bit DDR3-800 and DDR3L-800, supporting DDR interleaving mode for 2x32 LPDDR2-800 in i.MX 6DualLite — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit. — 16/32-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Solo/6DualLite processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously): • Displays—Total of five interfaces available. Total raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to two interfaces may be active in parallel (excluding EPDC). — One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 165 Mpixels/sec or two ports up to 85 MP/sec (for example, WUXGA at 60 Hz) each — HDMI 1.4 port

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Introduction i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 NXP Semiconductors 7 — MIPI/DSI, two lanes at 1 Gbps — EPDC, Color, and monochrome E-INK, up to 1650x2332 resolution and 5-bit grayscale • Camera sensors: — Two parallel Camera ports (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 Serial port, supporting from 80 Mbps to 1 Gbps speed per data lane. The CSI-2 Receiver core can manage one clock lane and up to two data lanes. Each i.MX 6Solo/6DualLite processor has two lanes. • Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max) – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) • USB: — One high speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB Phy — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed Phy – Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) Phy • Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. • Miscellaneous IPs and interfaces: — SSI block is capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode — ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with 7.1 multi channel outputs — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. — Four eCSPI (Enhanced CSPI) — Four I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Solo/6DualLite errata document (IMX6SDLCE).

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i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 8 NXP Semiconductors Introduction — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) — MLB (MediaLB) provides interface to MOST Networks (MOST25, MOST50, MOST150) with the option of DTCP cipher accelerator The i.MX 6Solo/6DualLite processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature • Support DVFS techniques for low power modes • Use SW State Retention and Power Gating for ARM and MPE • Support various levels of system power modes • Use flexible clock gating control scheme The i.MX 6Solo/6DualLite processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Solo/6DualLite processors incorporate the following hardware accelerators: • VPU—Video Processing Unit • IPUv3H—Image Processing Unit version 3H • GPU3Dv5—3D Graphics Processing Unit (OpenGL ES 2.0) version 5 • GPU2Dv2—2D Graphics Processing Unit (BitBlt) • PXP—PiXel Processing Pipeline. Off loading key pixel processing operations are required to support the EPD display applications. • ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.) • SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features. • CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash engines, 16 KB secure RAM, and True and Pseudo Random Number Generator (NIST certified). • SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock • CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy. • A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.

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Introduction i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 7, 10/2016 NXP Semiconductors 9 NOTE The actual feature set depends on the part numbers as described in Table 1, "Example Orderable Part Numbers," on page 3. Functions, such as video hardware acceleration, and 2D and 3D hardware graphics acceleration may not be enabled for specific part numbers. 1.3 Updated Signal Naming Convention The signal names of the i.MX6 series of products have been standardized to better align the signal names within the family and across the documentation. Some of the benefits of these changes are as follows: • The names are unique within the scope of an SoC and within the series of products • Searches will return all occurrences of the named signal • The names are consistent between i.MX 6 series products implementing the same modules • The module instance is incorporated into the signal name This change applies only to signal names. The original ball names have been preserved to prevent the need to change schematics, BSDL models, IBIS models, etc. Throughout this document, the updated signal names are used except where referenced as a ball name (such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal name changes is in the document, IMX 6 Series Signal Name Mapping (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions.

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