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MM74HC123AMX

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MM74HC123AMX

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Part Number MM74HC123AMX
Manufacturer ON Semiconductor
Description IC MULTIVIBRATOR DUAL 16-SOIC
Datasheet MM74HC123AMX Datasheet
Package 16-SOIC (0.154", 3.90mm Width)
In Stock 1,583 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 15 - Jul 20 (Choose Expedited Shipping)
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Part Number # MM74HC123AMX (Logic - Multivibrators) is manufactured by ON Semiconductor and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MM74HC123AMX Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Logic - Multivibrators
Datasheet MM74HC123AMXDatasheet
Package16-SOIC (0.154", 3.90mm Width)
Series74HC
Logic TypeMonostable
Independent Circuits2
Schmitt Trigger InputYes
Propagation Delay22ns
Current - Output High, Low5.2mA, 5.2mA
Voltage - Supply2V ~ 6V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case16-SOIC (0.154", 3.90mm Width)
Supplier Device Package16-SOIC

MM74HC123AMX Datasheet

Page 1

Page 2

© 2001 Fairchild Semiconductor Corporation DS005206 www.fairchildsemi.com September 1983 Revised May 2001 M M 7 4 H C 1 2 3 A D u a l R e trig g e ra b le M o n o s ta b le M u ltiv ib ra to r MM74HC123A Dual Retriggerable Monostable Multivibrator General Description The MM74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technol- ogy. They feature speeds comparable to low power Schot- tky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits. Each multivibrator features both a negative, A, and a posi- tive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The MM74HC123A can be triggered on the positive transition of the clear while A is held LOW and B is held HIGH. The MM74HC123A is retriggerable. That is it may be trig- gered repeatedly while their outputs are generating a pulse and the pulse will be extended. Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques. The out- put pulse equation is simply: PW = (REXT) (CEXT); where PW is in seconds, R is in ohms, and C is in farads. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Features ■Typical propagation delay: 25 ns ■Wide power supply range: 2V–6V ■Low quiescent current: 80 µ A maximum (74HC Series) ■Low input current: 1 µ A maximum ■Fanout of 10 LS-TTL loads ■Simple pulse width formula T = RC ■Wide pulse range: 400 ns to ∞ (typ) ■Part to part variation: ± 5% (typ) ■Schmitt Trigger A & B inputs allow rise and fall times to be as slow as one second Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View Timing Component Note: Pin 6 and Pin 14 must be hard-wired to GND. Order Number Package Number Package Description MM74HC123AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC123ASJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC123AMTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC123AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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www.fairchildsemi.com 2 M M 7 4 H C 1 2 3 A Truth Table H = HIGH Level L = LOW Level ↑ = Transition from LOW-to-HIGH ↓ = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant Logic Diagram Inputs Outputs Clear A B Q Q L X X L H X H X L H X X L L H H L ↑ H ↓ H ↑ L H

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3 www.fairchildsemi.com M M 7 4 H C 1 2 3 A Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation Temperature Derating: Plastic “N” Package: − 12mW/° C from 65° C to 85° C DC Electrical Characteristics (Note 4) Note 4: For a power supply of 5V ± 10% the worst-case output voltages (VOH, VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when design- ing with this supply. Worst-case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC) − 0.5V to + 7.0V DC Input Voltage (VIN) − 1.5V to VCC + 1.5V DC Output Voltage (VOUT) − 0.5V to VCC + 0.5V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current, per pin (IOUT) ± 25 mA DC VCC or GND Current, per pin (ICC) ± 50 mA Storage Temperature Range (TSTG) − 65° C to + 150° C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260° C Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V (VIN, VOUT) Operating Temperature Range (TA) − 40 + 85 ° C Input Rise or Fall Times (Clear Input) (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25° C TA = − 40 to 85° C TA = − 55 to 125° C Units Typ Guaranteed Limits VIH Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum LOW Level Input 2.0V 0.3 0.3 0.3 V Voltage 4.5V 0.9 0.9 0.9 V 6.0V 1.2 1.2 1.2 V VOH Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µ A 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VIN = VIH or VIL V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µ A 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VIN = VIH or VIL V |IOUT| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input Current VIN = VCC or GND 6.0V ± 0.5 ± 5.0 ± 5.0 µ A (Pins 7, 15) IIN Maximum Input Current VIN = VCC or GND 6.0V ± 0.1 ± 1.0 ± 1.0 µ A (all other pins) ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 8.0 80 160 µ A Current (standby) IOUT = 0 µ A ICC Maximum Active Supply VIN= VCC or GND 2.0V 36 80 110 130 µ A Current (per R/CEXT = 0.5VCC 4.5V 0.33 1.0 1.3 1.6 mA monostable) 6.0V 0.7 2.0 2.6 3.2 mA

Page 5

www.fairchildsemi.com 4 M M 7 4 H C 1 2 3 A AC Electrical Characteristics VCC = 5V, TA = 25° C, CL = 15 pF, tr = tf = 6 ns AC Electrical Characteristics CL = 50 pF tr = tf = 6 ns (unless otherwise specified) Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Symbol Parameter Conditions Typ Limit Units tPLH Maximum Trigger Propagation Delay 22 33 ns A, B or Clear to Q tPHL Maximum Trigger Propagation Delay 25 42 ns A, B or Clear to Q tPHL Maximum Propagation Delay, Clear to Q 20 27 ns tPLH Maximum Propagation Delay, Clear to Q 22 33 ns tW Minimum Pulse Width, A, B or Clear 14 26 ns tREM Minimum Clear Removal Time 0 ns tWQ(MIN) Minimum Output Pulse Width CEXT = 28 pF 400 ns REXT = 2 kΩ tWQ Output Pulse Width CEXT = 1000 pF 10 µ s REXT = 10 kΩ Symbol Parameter Conditions VCC TA = 25° C TA = − 40 to 85° C TA = − 55 to 125° C Units Typ Guaranteed Limits tPLH Maximum Trigger Propagation 2.0V 77 169 194 210 ns Delay, A, B or Clear to Q 4.5V 26 42 51 57 ns 6.0V 21 32 39 44 ns tPHL Maximum Trigger Propagation 2.0V 88 197 229 250 ns Delay, A, B or Clear to Q 4.5V 29 48 60 67 ns 6.0V 24 38 46 51 ns tPHL Maximum Propagation Delay 2.0V 54 114 132 143 ns Clear to Q 4.5V 23 34 41 45 ns 6.0V 19 28 33 36 ns tPLH Maximum Propagation Delay 2.0V 56 116 135 147 ns Clear to Q 4.5V 25 36 42 46 ns 6.0V 20 29 34 37 ns tW Minimum Pulse Width 2.0V 57 123 144 157 ns A, B, Clear 4.5V 17 30 37 42 ns 6.0V 12 21 27 30 ns tREM Minimum Clear 2.0V 0 0 0 ns Removal Time 4.5V 0 0 0 ns 6.0V 0 0 0 ns tTLH, tTHL Maximum Output 2.0V 30 75 95 110 ns Rise and Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns tWQ(MIN) Minimum Output CEXT = 28 pF 2.0V 1.5 µ s Pulse Width REXT = 2 kΩ 4.5V 450 ns REXT = 6 kΩ (VCC = 2V) 6.0V 380 ns tWQ Output Pulse Width CEXT = 0.1 µ F Min 5.0V 1 0.9 0.86 0.85 ms REXT = 10 kΩ Max 5.0V 1 1.1 1.14 1.15 ms CIN Maximum Input 12 20 20 20 pF Capacitance (Pins 7 & 15) CIN Maximum Input 6 10 10 10 pF Capacitance (other inputs) CPD Power Dissipation (Note 5) 70 pF Capacitance

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5 www.fairchildsemi.com M M 7 4 H C 1 2 3 A Theory of Operation FIGURE 1. Trigger Operation As shown in Figure 1 and the logic diagram, before an input trigger occurs, the one shot is in the quiescent state with the Q output LOW, and the timing capacitor CEXT com- pletely charged to VCC. When the trigger input A goes from VCC to GND (while inputs B and clear are held to VCC) a valid trigger is recognized, which turns on comparator C1 and Nchannel transistor N11. At the same time the output latch is set. With transistor N1 on, the capacitor CEXT rap- idly discharges toward GND until VREF1 is reached. At this point the output of comparator C1 changes state and tran- sistor N1 turns off. Comparator C1 then turns off while at the same time comparator C2 turns on. With transistor N1 off, the capacitor CEXT begins to charge through the timing resistor, REXT, toward VCC. When the voltage across CEXT equals VREF2, comparator C2 changes state causing the output latch to reset (Q goes LOW) while at the same time disabling comparator C2. This ends the timing cycle with the monostable in the quiescent state, waiting for the next trigger. A valid trigger is also recognized when trigger input B goes from GND to VCC (while input A is at GND and input clear is at VCC2). The MM74HC123A can also be triggered when clear goes from GND to VCC (while A is at GND and B is at VCC6). It should be noted that in the quiescent state CEXT is fully charged to VCC causing the current through resistor REXT to be zero. Both comparators are “off” with the total device current due only to reverse junction leakages. An added feature of the MM74HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value of CEXT, REXT, or the duty cycle of the input waveform. Retrigger Operation The MM74HC123A is retriggered if a valid trigger occurs 3 followed by another trigger 4 before the Q output has returned to the quiescent (zero) state. Any retrigger, after the timing node voltage at the R/CEXT pin has begun to rise from VREF1, but has not yet reached VREF2, will cause an increase in output pulse width T. When a valid retrigger is initiated 4, the voltage at the R/CEXT pin will again drop to VREF1 before progressing along the RC charging curve toward VCC. The Q output will remain HIGH until time T, after the last valid retrigger. Because the trigger-control circuit flip-flop resets shortly after CX has discharged to the reference voltage of the lower reference circuit, the minimum retrigger time, trr is a function of internal propagation delays and the discharge time of CX: Another removal/retrigger time occurs when a short clear pulse is used. Upon receipt of a clear, the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger. This time is dependent on the capacitor used and is approximately:

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www.fairchildsemi.com 6 M M 7 4 H C 1 2 3 A Theory of Operation (Continued) Reset Operation These one shots may be reset during the generation of the output pulse. In the reset mode of operation, an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to VCC by turning on transistor Q1 5. When the voltage on the capacitor reaches VREF2, the reset latch will clear and then be ready to accept another pulse. If the clear input is held low, any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change. Since the Q output is reset when an input low level is detected on the Clear input, the output pulse T can be made significantly shorter than the minimum pulse width specification. Typical Output Pulse Width vs. Timing Components Typical Distribution of Output Pulse Width, Part to Part Typical 1ms Pulse Width Variation vs. Supply Minimum REXT vs. Supply Voltage Typical 1ms Pulse Width Variation vs. Temperature Note: R and C are not subjected to temperature. The C is polypropylene.

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7 www.fairchildsemi.com M M 7 4 H C 1 2 3 A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A

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www.fairchildsemi.com 8 M M 7 4 H C 1 2 3 A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

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9 www.fairchildsemi.com M M 7 4 H C 1 2 3 A Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16

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June 28, 2020

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June 18, 2020

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June 12, 2020

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June 11, 2020

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June 10, 2020

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June 10, 2020

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June 7, 2020

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June 3, 2020

Worked like it was intended.

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June 1, 2020

It arrived earlier than the deadline. All is OK. Thank you

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May 30, 2020

The order process is easy and user friendly, very helpful customer service, always fast shipping.

MM74HC123AMX Guarantees

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