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MM74HC4046MTCX

hot MM74HC4046MTCX

MM74HC4046MTCX

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Part Number MM74HC4046MTCX
Manufacturer Fairchild/ON Semiconductor
Description IC PHASE LOCK LOOP CMOS 16-TSSOP
Datasheet MM74HC4046MTCX Datasheet
Package 16-TSSOP (0.173", 4.40mm Width)
In Stock 223256 piece(s)
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MM74HC4046MTCX Specifications

ManufacturerFairchild/ON Semiconductor
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet MM74HC4046MTCX Datasheet
Package16-TSSOP (0.173", 4.40mm Width)
Series74HC
TypePhase Lock Loop (PLL)
PLLNo
InputCMOS
Output3-State
Number of Circuits1
Ratio - Input:Output1:2
Differential - Input:OutputNo/No
Frequency - Max14MHz
Divider/MultiplierNo/No
Voltage - Supply2 V ~ 6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case16-TSSOP (0.173", 4.40mm Width)
Supplier Device Package16-TSSOP

MM74HC4046MTCX Datasheet

Page 1

Page 2

© 2003 Fairchild Semiconductor Corporation DS005352 www.fairchildsemi.com February 1984 Revised October 2003 M M 7 4 H C 4 0 4 6 C M O S P h a s e L o c k L o o p MM74HC4046 CMOS Phase Lock Loop General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high fre- quency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and three phase comparators. The three phase comparators have a common signal input and a common comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels. This device is similar to the CD4046 except that the Zener diode of the metal gate CMOS device has been replaced with a third phase comparator. Phase Comparator I is an exclusive OR (XOR) gate. It pro- vides a digital error signal that maintains a 90 phase shift between the VCO’s center frequency and the input signal (50% duty cycle input waveforms). This phase detector is more susceptible to locking onto harmonics of the input fre- quency than phase comparator I, but provides better noise rejection. Phase comparator III is an SR flip-flop gate. It can be used to provide the phase comparator functions and is similar to the first comparator in performance. Phase comparator II is an edge sensitive digital sequential network. Two signal outputs are provided, a comparator output and a phase pulse output. The comparator output is a 3-STATE output that provides a signal that locks the VCO output signal to the input signal with 0 phase shift between them. This comparator is more susceptible to noise throw- ing the loop out of lock, but is less likely to lock onto har- monics than the other two comparators. In a typical application any one of the three comparators feed an external filter network which in turn feeds the VCO input. This input is a very high impedance CMOS input which also drives the source follower. The VCO’s operating frequency is set by three external components connected to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided to disable the VCO and the source follower, providing a method of putting the IC in a low power state. The source follower is a MOS transistor whose gate is con- nected to the VCO input and whose drain connects the Demodulator output. This output normally is used by tying a resistor from pin 10 to ground, and provides a means of looking at the VCO input without loading down modifying the characteristics of the PLL filter. Features ■Low dynamic power consumption: (VCC = 4.5V) ■Maximum VCO operating frequency: 12 MHz (VCC = 4.5V) ■Fast comparator response time (VCC = 4.5V) Comparator I: 25 ns Comparator II: 30 ns Comparator III: 25 ns ■VCO has high linearity and high temperature stability Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description MM74HC4046M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC4046SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4046N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Page 3

www.fairchildsemi.com 2 M M 7 4 H C 4 0 4 6 Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Block Diagram

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3 www.fairchildsemi.com M M 7 4 H C 4 0 4 6 Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions Note 1: Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/° C from 65° C to 85° C. DC Electrical Characteristics (Note 4) Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur- rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. Supply Voltage (VCC) − 0.5 to + 7.0V DC Input Voltage (VIN) − 1.5 to VCC + 1.5V DC Output Voltage (VOUT) − 0.5 to VCC + 0.5V Clamp Diode Current (IIK, IOK) ± 20 mA DC Output Current per pin (IOUT) ± 25 mA DC VCC or GND Current, per pin (ICC) ± 50 mA Storage Temperature Range (TSTG) − 65° C + 150° C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260° C Min Max Units Supply Voltage (VCC) 2 6 V DC Input or Output Voltage (VIN, VOUT) 0 VCC V Operating Temperature Range (TA) − 40 + 85 ° C Input Rise or Fall Times (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Symbol Parameter Conditions VCC TA = 25° C TA = − 40 to 85° C TA = − 55 to 125° C Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µ A 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VIN = VIH or VIL |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum Low Level VIN = VIHor VIL Output Voltage |IOUT| ≤ 20 µ A 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VIN = VIH or VIL |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input Current (Pins 3,5,9) VIN = VCCor GND 6.0V ± 0.1 ± 1.0 ± 1.0 µ A IIN Maximum Input Current (Pin 14) VIN = VCC or GND 6.0V 20 50 80 100 µ A IOZ Maximum 3-STATE Output VOUT = VCC or GND 6.0V ± 0.5 ± 5.0 ± 10 µ A Leakage Current (Pin 13) ICC Maximum Quiescent VIN = VCC or GND 6.0V 30 80 130 160 µ A Supply Current IOUT = 0 µ A VIN = VCC or GND 6.0V 600 1500 2400 3000 µ A Pin 14 Open

Page 5

www.fairchildsemi.com 4 M M 7 4 H C 4 0 4 6 AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tr = 6 ns (unless otherwise specified.) Symbol Parameters Conditions VCC TA= 25C TA = − 40 to 85° C TA = − 55 to 125° C Units Typ Guaranteed Limits AC Coupled C (series) = 100 pF 2.0V 25 100 150 200 mV Input Sensitivity, fIN = 500 kHz 4.5V 50 150 200 250 mV Signal In 6.0V 135 250 300 350 mV tr, tf Maximum Output 2.0V 30 75 95 110 ns Rise and Fall Time 4.5V 9 15 19 22 ns 6.0V 8 12 15 19 ns CIN Maximum Input Capacitance 7 pF Phase Comparator I tPHL, tPLH Maximum 2.0V 65 200 250 300 ns Propagation Delay 4.5V 25 40 50 60 ns 6.0V 20 34 43 51 ns Phase Comparator II tPZL Maximum 3-STATE 2.0V 75 225 280 340 ns Enable Time 4.5V 25 45 56 68 ns 6.0V 22 38 48 57 ns tPZH, tPHZ Maximum 3-STATE 2.0V 88 240 300 360 ns Enable Time 4.5V 30 48 60 72 ns 6.0V 25 41 51 61 ns tPLZ Maximum 3-STATE 2.0V 90 240 300 360 ns Disable Time 4.5V 32 48 60 72 ns 6.0V 28 41 51 61 ns tPHL, tPLH Maximum 2.0V 100 250 310 380 ns Propagation Delay 4.5V 34 50 63 75 ns HIGH-to-LOW to Phase Pulses 6.0V 27 43 53 64 ns Phase Comparator III tPHL, tPLH Maximum 2.0V 75 200 250 300 ns Propagation Delay 4.5V 25 40 50 60 ns 6.0V 22 34 43 51 ns CPD Maximum Power All Comparators 130 pF Dissipation Capacitance VIN = VCC and GND Voltage Controlled Oscillator (Specified to operate from VCC= 3.0V to 6.0V) fMAX Maximum C1 = 50 pF Operating R1 = 100Ω 4.5V 7 4.5 MHz Frequency R2 = ∞ 6.0V 11 7 MHz VCOin = VCC C1 = 0 pF 4.5V 12 MHz R1 = 100Ω 6.0 14 MHz VCOin = VCC Duty Cycle 50 % Demodulator Output Offset Voltage Rs = 20 kΩ 4.5V 0.75 1.3 1.5 1.6 V VCOin–Vdem Offset Rs = 20 kΩ 4.5V Variation VCOin = 1.75V 0.65 V 2.25V 0.1 2.75V 0.75

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5 www.fairchildsemi.com M M 7 4 H C 4 0 4 6 Typical Performance Characteristics Typical Center Frequency vs R1, C1 VCC = 4.5V Typical Center Frequency vs R1, C1 VCC = 6V Typical Offset Frequency vs R2, C1 VCC = 4.5V Typical Offset Frequency vs R2, C1 VCC = 6V Typical VCO Power Dissipation @ Center Frequency vs R1 Typical VCO Power Dissipation @ fMIN vs R2

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www.fairchildsemi.com 6 M M 7 4 H C 4 0 4 6 Typical Performance Characteristics (Continued) VCOin vs fout VCC = 4.5V VCOin vs fout VCC = 4.5V VCOout vs Temperature VCC = 4.5V VCOout vs Temperature VCC = 6V

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7 www.fairchildsemi.com M M 7 4 H C 4 0 4 6 Typical Performance Characteristics (Continued) HC4046 Typical Source Follower Power Dissipation vs RS Typical fMAX/fMIN vs R2/R1 VCC = 4.5V & 6V fMAX/fMIN Typical VCO Linaearity vs R1 & C1 Typical VCO Linearity vs R1 & C1

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www.fairchildsemi.com 8 M M 7 4 H C 4 0 4 6 Detailed Circuit Description VOLTAGE CONTROLLED OSCILLATOR/SOURCE FOLLOWER The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and capacitor C1 are selected to determine the center frequency of the VCO. R1 controls the lock range. As R1’s resistance decreases the range of fMIN to fMAX increases. Thus the VCO’s gain increases. As C1 is changed the offset (if used) of R2, and the center frequency is changed. (See typical performance curves) R2 can be used to set the offset fre- quency with 0V at VCO input. If R2 is omitted the VCO range is from 0Hz. As R2 is decreased the offset frequency is increased. The effect of R2 is shown in the design infor- mation table and typical performance curves. By increasing the value of R2 the lock range of the PLL is offset above 0Hz and the gain (Hz/Volt) does not change. In general, when offset is desired, R2 and C1 should be chosen first, and then R1 should be chosen to obtain the proper center frequency. Internally the resistors set a current in a current mirror as shown in Figure 1. The mirrored current drives one side of the capacitor once the capacitor charges up to the thresh- old of the schmitt trigger the oscillator logic flips the capaci- tor over and causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to pin 4. VCO WITHOUT OFFSET R2 = ∞ VCO WITH OFFSET FIGURE 1. Comparator I Comparator II & III R2= ∞ R2≠∞ R2= ∞ R2≠∞ •Given: f0 •Given: f0 and fL •Given: fMAX •Given: fMIN and fMAX •Use f0 with curve titled •Calculate fMIN from the •Calculate f0 from the •Use fMIN with curve titled center frequency vs R1, C equation fMIN = fo − fL equation fo = fMAX/2 offset frequency vs R2, to determine R1 and C1 •Use fMIN with curve titled •Use f0 with curve titled C to determine R2 and C1 offset frequency vs R2, C center frequency vs R1, C •Calculate fMAX/fMIN to determine R2 and C1 to determine R1 and C1 •Use fMAX/fMIN with curve •Calculate fMAX/fMIN from titled fMAX/fMIN vs R2/R1 the equation fMAX/fMIN = to determine ratio R2/R1 fo + fL/fo − fL to obtain R1 •Use fMAX/fMIN with curve titled fMAX/fMIN vs R2/R1 to determine ratio R2/R1 to obtain R1

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9 www.fairchildsemi.com M M 7 4 H C 4 0 4 6 Detailed Circuit Description (Continued) FIGURE 2. Logic Diagram for VCO The input to the VCO is a very high impedance CMOS input and so it will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance a source follower transistor is provided. This transistor can be used by connecting a resistor to ground and its drain output will follow the VCO input signal. An inhibit signal is provided to allow disabling of the VCO and the source follower. This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and source follower. The output of the VCO is a standard high speed CMOS output with an equivalent LSTTL fanout of 10. The VCO output is approximately a square wave. This output can either directly feed the comparator input of the phase com- parators or feed external prescalers (counters) to enable frequency synthesis. PHASE COMPARATORS All three phase comparators share two inputs, Signal In and Comparator In. The Signal In has a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled then this input requires logic levels the same as standard 74HC. The Comparator input is a standard digital input. Both input structures are shown in Figure 3. The outputs of these comparators are essentially standard 74HC voltage outputs. (Comparator II is 3-STATE.) FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators

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