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MPC8547EVUAQG

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MPC8547EVUAQG

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Part Number MPC8547EVUAQG
Manufacturer NXP
Description IC MPU MPC85XX 1.0GHZ 783FCBGA
Datasheet MPC8547EVUAQG Datasheet
Package 783-BBGA, FCBGA
In Stock 611 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
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Part Number # MPC8547EVUAQG (Embedded - Microprocessors) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MPC8547EVUAQG Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MPC8547EVUAQGDatasheet
Package783-BBGA, FCBGA
SeriesMPC85xx
Core ProcessorPowerPC e500
Number of Cores/Bus Width1 Core, 32-Bit
Speed1.0GHz
Co-Processors/DSPSignal Processing; SPE, Security; SEC
RAM ControllersDDR, DDR2, SDRAM
Graphics AccelerationNo
Display & Interface Controllers-
Ethernet10/100/1000 Mbps (4)
SATA-
USB-
Voltage - I/O1.8V, 2.5V, 3.3V
Operating Temperature0°C ~ 105°C (TA)
Security FeaturesCryptography, Random Number Generator
Package / Case783-BBGA, FCBGA
Supplier Device Package783-FCPBGA (29x29)

MPC8547EVUAQG Datasheet

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© 2007-2012, 2014 Freescale Semiconductor, Inc. All rights reserved. Freescale Semiconductor Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 1 Overview This section provides a high-level overview of the device features. The following figure shows the major functional units within the device. Although this document is written from the perspective of the MPC8548E, most of the material applies to the other family members, such as MPC8547E, MPC8545E, and MPC8543E. When specific differences occur, such as pinout differences and processor frequency ranges, they are identified as such. For specific PVR and SVR numbers, see the MPC8548E PowerQUICC III Integrated Host Processor Reference Manual. Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19 6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 20 7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8. Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 27 9. Ethernet Management Interface Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11. Programmable Interrupt Controller . . . . . . . . . . . . . 53 12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14. GPOUT/GPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 15. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 65 17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 18. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 19. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 91 20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 22. System Design Information . . . . . . . . . . . . . . . . . . 135 23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 145 24. Document Revision History . . . . . . . . . . . . . . . . . . 148 MPC8548E PowerQUICC III Integrated Processor Hardware Specifications Document Number: MPC8548EEC Rev. 10, 06/2014

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 2 Freescale Semiconductor Overview Figure 1. Device Block Diagram 1.1 Key Features The following list provides an overview of the device feature set: • High-performance 32-bit core built on Power Architecture® technology. — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis, with separate locking for instructions and data. — Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive instruction set for vector (64-bit) integer and fractional operations. These instructions use both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU. — Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit) floating-point instructions that use the 64-bit GPRs. — 36-bit real addressing — Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set for single-precision (32-bit) floating-point instructions. — Memory management unit (MMU). Especially designed for embedded applications. Supports 4-Kbyte to 4-Gbyte page sizes. — Enhanced hardware and software debug support Core Complex x8 PCI Express 4x RapidIO 66 MHz PCI 32-bit 10/100/1Gb MII, GMII, TBI, RTBI, RGMII, Serial IRQs SDRAM DDR Flash SDRAM GPIO Bus I2C I2C Controller eTSEC 32-bit PCI Bus Interface (If 64-bit not used) e500 Coherency Module DDR/DDR2/ Memory Controller Local Bus Controller Programmable Interrupt Controller (PIC) DUART e500 Core 512-Kbyte L2 Cache/ SRAM 32-bit PCI/ 64-bit PCI/PCI-X Bus Interface 32-Kbyte L1 Instruction Cache 32-Kbyte L1 Data Cache OceaN Switch Fabric Serial RapidIO or PCI Express 4-Channel DMA Controller 133 MHz PCI/PCI-X I2C I2C Controller RMII 10/100/1Gb MII, GMII, TBI, RTBI, RGMII, eTSEC RMII 10/100/1Gb MII, GMII, TBI, RTBI, RGMII, eTSEC RMII 10/100/1Gb RTBI, RGMII, eTSEC Security Engine XOR Engine RMII

Page 4

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 3 Overview — Performance monitor facility that is similar to, but separate from, the device performance monitor The e500 defines features that are not implemented on this device. It also generally defines some features that this device implements more specifically. An understanding of these differences can be critical to ensure proper operations. • 512-Kbyte L2 cache/SRAM — Flexible configuration. — Full ECC support on 64-bit boundary in both cache and SRAM modes — Cache mode supports instruction caching, data caching, or both. — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing). — 1, 2, or 4 ways can be configured for stashing only. — Eight-way set-associative cache organization (32-byte cache lines) — Supports locking entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions. — Global locking and Flash clearing done through writes to L2 configuration registers — Instruction and data locks can be Flash cleared separately. — SRAM features include the following: – I/O devices access SRAM regions by marking transactions as snoopable (global). – Regions can reside at any aligned location in the memory map. – Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-than-cache-line accesses. • Address translation and mapping unit (ATMU) — Eight local access windows define mapping within local 36-bit address space. — Inbound and outbound ATMUs map to larger external address spaces. – Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express – Four inbound windows plus a default window on RapidIO™ – Four outbound windows plus default translation for PCI/PCI-X and PCI Express – Eight outbound windows plus default translation for RapidIO with segmentation and sub-segmentation support • DDR/DDR2 memory controller — Programmable timing supporting DDR and DDR2 SDRAM — 64-bit data interface — Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes — DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports — Full ECC support — Page mode support – Up to 16 simultaneous open pages for DDR

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 4 Freescale Semiconductor Overview – Up to 32 simultaneous open pages for DDR2 — Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self-refresh SDRAM — On-die termination support when using DDR2 — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access via JTAG port — 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2) — Support for battery-backed main memory • Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture. — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high-resolution timers/counters that can generate interrupts — Supports a variety of other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing. — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs. — Interrupt summary registers allow fast identification of interrupt source. • Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP — Four crypto-channels, each supporting multi-command descriptor chains – Dynamic assignment of crypto-execution units via an integrated controller – Buffer size of 256 bytes for each execution unit, with flow control for large data sizes — PKEU—public key execution unit – RSA and Diffie-Hellman; programmable field size up to 2048 bits – Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to 511 bits — DEU—Data Encryption Standard execution unit – DES, 3DES – Two key (K1, K2) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 5 Overview — AESU—Advanced Encryption Standard unit – Implements the Rijndael symmetric key cipher – ECB, CBC, CTR, and CCM modes – 128-, 192-, and 256-bit key lengths — AFEU—ARC four execution unit – Implements a stream cipher compatible with the RC4 algorithm – 40- to 128-bit programmable key — MDEU—message digest execution unit – SHA with 160- or 256-bit message digest – MD5 with 128-bit message digest – HMAC with either algorithm — KEU—Kasumi execution unit – Implements F8 algorithm for encryption and F9 algorithm for integrity checking – Also supports A5/3 and GEA-3 algorithms — RNG—random number generator — XOR engine for parity checking in RAID storage applications • Dual I2C controllers — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus • Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC • DUART — Two 4-wire interfaces (SIN, SOUT, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D • Local bus controller (LBC) — Multiplexed 32-bit address and data bus operating at up to 133 MHz — Eight chip selects support eight external slaves — Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller. — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs)

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 6 Freescale Semiconductor Overview – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8, 16, or 32 bits) • Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Four controllers designed to comply with IEEE Std. 802.3®, 802.3u, 802.3x, 802.3z, 802.3ac, and 802.3ab — Support for various Ethernet physical interfaces: – 1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII – 10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII — Flexible configuration for multiple PHY interface configurations. See Section 8.1, “Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics,” for more information. — TCP/IP acceleration and QoS features available – IP v4 and IP v6 header recognition on receive – IP v4 header checksum verification and generation – TCP and UDP checksum verification and generation – Per-packet configurable acceleration – Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2™, PPPoE session, MPLS stacks, and ESP/AH IP-security headers – Supported in all FIFO modes — Quality of service support: – Transmission from up to eight physical queues – Reception to up to eight physical queues — Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex): – IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or software-programmed PAUSE frame generation and recognition) — Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and IEEE Std. 802.1™ virtual local area network (VLAN) tags and priority — VLAN insertion and deletion – Per-frame VLAN control word or default VLAN for each eTSEC – Extracted VLAN control word passed to software separately — Retransmission following a collision — CRC generation and verification of inbound/outbound frames — Programmable Ethernet preamble insertion and extraction of up to 7 bytes — MAC address recognition: – Exact match on primary and virtual 48-bit unicast addresses

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 7 Overview – VRRP and HSRP support for seamless router fail-over – Up to 16 exact-match MAC addresses supported – Broadcast address (accept/reject) – Hash table match on up to 512 multicast addresses – Promiscuous mode — Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet programming models — RMON statistics support — 10-Kbyte internal transmit and 2-Kbyte receive FIFOs — MII management interface for control and status — Ability to force allocation of header information and buffer descriptors into L2 cache • OCeaN switch fabric — Full crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes • Integrated DMA controller — Four-channel controller — All channels accessible by both the local and remote masters — Extended DMA functions (advanced chaining and striding capability) — Support for scatter and gather transfers — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no snoop) — Ability to start and flow control each DMA channel from external 3-pin interface — Ability to launch DMA from single write transaction • Two PCI/PCI-X controllers — PCI 2.2 and PCI-X 1.0 compatible — One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X frequency in synchronous mode is 110 MHz) — One 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the other port is in 32-bit mode) — Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 8 Freescale Semiconductor Overview — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency • Serial RapidIO™ interface unit — Supports RapidIO™ Interconnect Specification, Revision 1.2 — Both 1× and 4× LP-serial link interfaces — Long- and short-haul electricals with selectable pre-compensation — Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane — Auto detection of 1- and 4-mode operation during port initialization — Link initialization and synchronization — Large and small size transport information field support selectable at initialization time — 34-bit addressing — Up to 256 bytes data payload — All transaction flows and priorities — Atomic set/clr/inc/dec for read-modify-write operations — Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at a remote memory system — Receiver-controlled flow control — Error detection, recovery, and time-out for packets and control symbols as required by the RapidIO specification — Register and register bit extensions as described in part VIII (Error Management) of the RapidIO specification — Hardware recovery only — Register support is not required for software-mediated error recovery. — Accept-all mode of operation for fail-over support — Support for RapidIO error injection — Internal LP-serial and application interface-level loopback modes — Memory and PHY BIST for at-speed production test • RapidIO-compatible message unit — 4 Kbytes of payload per message — Up to sixteen 256-byte segments per message — Two inbound data message structures within the inbox — Capable of receiving three letters at any mailbox — Two outbound data message structures within the outbox — Capable of sending three letters simultaneously — Single segment multicast to up to 32 devIDs — Chaining and direct modes in the outbox

Page 10

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10 Freescale Semiconductor 9 Overview — Single inbound doorbell message structure — Facility to accept port-write messages • PCI Express interface — PCI Express 1.0a compatible — Supports x8,x4,x2, and x1 link widths — Auto-detection of number of connected lanes — Selectable operation as root complex or endpoint — Both 32- and 64-bit addressing — 256-byte maximum payload size — Virtual channel 0 only — Traffic class 0 only — Full 64-bit decode with 32-bit wide windows • Pin multiplexing for the high-speed I/O interfaces supports one of the following configurations: — 8 PCI Express — 4 PCI Express and 4 serial RapidIO • Power management — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle • System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the eight counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow • System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • JTAG boundary scan, designed to comply with IEEE Std. 1149.1™

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Kat*****Park

May 24, 2020

This product is very easy to replace and solved my problem.

Mile*****cobs

May 20, 2020

Well packaged and good condition with the parts, arrived on time, good customer service.

Avah*****toya

May 4, 2020

Very fast reply, professional seller and received the correct parts.

Gian*****hannon

May 3, 2020

I had no problems with this product. Would I recommend it. Yes.

Dar*****Karpe

April 25, 2020

So far all the items still work. I'm using these for some home made solar panels and they're doing great.

Ti*****s Ho

April 20, 2020

Not much to say. Nice and cheap, and haven't had a failure yet.

Ree*****Ratta

April 19, 2020

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Sulli*****elendez

April 16, 2020

I have always get a fast response from Heisener with my orders. As a small business owner I greatly appreciate that I can order as little as 1 item as opposed to other companies who require you place a larger minimum order.

Juli*****orah

April 14, 2020

Good and works well. What else is there to say about it.

Zai*****Balan

April 10, 2020

Worked wonderfully. Went through the instructions to the tea to make sure it was done correctly.

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