0
+86-755-83210559 ext. 811
TOP
Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811
Language Translation
  • • English
  • • Español
  • • Deutsch
  • • Français
  • • Italiano
  • • Nederlands
  • • Português
  • • русский язык
  • • 日本語
  • • 한국어
  • • 简体中文
  • • 繁體中文

* Please refer to the English Version as our Official Version.

Change Country

If your country is not listed, please select International as your region.

  • International
Americas
  • Argentina
  • Brasil
  • Canada
  • Chile
  • Colombia
  • Costa Rica
  • Dominican Republic
  • Ecuador
  • Guatemala
  • Honduras
  • Mexico
  • Peru
  • Puerto Rico
  • United States
  • Uruguay
  • Venezuela
Asia/Pacific
  • Australia
  • China
  • Hong Kong
  • Indonesia
  • Israel
  • India
  • Japan
  • Korea, Republic of
  • Malaysia
  • New Zealand
  • Philippines
  • Singapore
  • Thailand
  • Taiwan
  • Vietnam
Europe
  • Austria
  • Belgium
  • Bulgaria
  • Switzerland
  • Czech Republic
  • Germany
  • Denmark
  • Estonia
  • Spain
  • Finland
  • France
  • United Kingdom
  • Greece
  • Croatia
  • Hungary
  • Ireland
  • Italy
  • Netherlands
  • Norway
  • Poland
  • Portugal
  • Romania
  • Russian Federation
  • Sweden
  • Slovakia
  • Turkey

MPC8560PX667LC

hot MPC8560PX667LC

MPC8560PX667LC

For Reference Only

Part Number MPC8560PX667LC
Manufacturer NXP
Description IC MPU MPC85XX 667MHZ 783FCBGA
Datasheet MPC8560PX667LC Datasheet
Package 784-BBGA, FCBGA
In Stock 765 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jan 28 - Feb 2 (Choose Expedited Shipping)
Winter Hot Sale

* Free Shipping * Up to $100 Discount

Winter Hot Sale

Request for Quotation

MPC8560PX667LC

Quantity
  • We are offering MPC8560PX667LC for competitive price in the global market, please send us a quota request for pricing. Thank you!
  • To process your RFQ, please add MPC8560PX667LC with quantity into BOM. Heisener.com does NOT require any registration to request a quote of MPC8560PX667LC.
  • To learn about the specification of MPC8560PX667LC, please search the datasheet by clicking the link above. If you couldn't find the correct datasheet, please refer to the manufacturer's official datasheet.
Payment Methods
Delivery Services

Do you have any question about MPC8560PX667LC?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

MPC8560PX667LC Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microprocessors
Datasheet MPC8560PX667LC Datasheet
Package784-BBGA, FCBGA
SeriesMPC85xx
Core ProcessorPowerPC e500
Number of Cores/Bus Width1 Core, 32-Bit
Speed667MHz
Co-Processors/DSPCommunications; CPM
RAM ControllersDDR, SDRAM
Graphics AccelerationNo
Ethernet10/100/1000 Mbps (2)
Voltage - I/O2.5V, 3.3V
Operating Temperature0°C ~ 105°C (TA)
Package / Case784-BBGA, FCBGA
Supplier Device Package783-FCPBGA (29x29)

MPC8560PX667LC Datasheet

Page 1

Page 2

© Freescale Semiconductor, Inc., 2008. All rights reserved. Freescale Semiconductor Technical Data The MPC8560 integrates a PowerPC™ processor core built on Power Architecture™ technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8560 is a member of the PowerQUICC™ III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual. To locate any published errata or updates for this document, contact your Freescale sales office. MPC8560EC Rev. 4.2, 1/2008 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8 3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Ethernet: Three-Speed, MII Management . . . . . . . . 23 8. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13. RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70 15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17. System Design Information . . . . . . . . . . . . . . . . . . . 92 18. Document Revision History . . . . . . . . . . . . . . . . . . . 99 19. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 104 MPC8560 Integrated Processor Hardware Specifications

Page 3

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 2 Freescale Semiconductor Overview 1 Overview The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major functional units within the MPC8560. Figure 1. MPC8560 Block Diagram 1.1 Key Features The following lists an overview of the MPC8560 feature set. • High-performance, 32-bit Book E–enhanced core that implements the Power Architecture — 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data — Memory management unit (MMU) especially designed for embedded applications — Enhanced hardware and software debug support — Performance monitor facility (similar to but different from the MPC8560 performance monitor described in Chapter 18, “Performance Monitor.” • High-performance RISC CPM operating at up to 333 MHz — CPM software compatibility with previous PowerQUICC families — One instruction per clock I2C Controller Local Bus Controller RapidIO Controller PCI Controller DMA Controller 10/100/1000 MAC 10/100/1000 MAC MII, GMII, TBI, RTBI, RGMIIs Serial DMA ROM I-Memory DPRAM RISC Engine Parallel I/O Baud Rate Generators Timers MCC MCC FCC FCC FCC SCC SCC SCC SCC SPI I2C T C - L a y e r T im e S lo t A s s ig n e r T im e S lo t A s s ig n e r S e ri a l In te rf a c e s UTOPIAs MIIs, TDMs I/Os CPM DDR SDRAM Controller CPM Controller Interrupt 256KB L2-Cache/ SRAM e500 Core 32 KB L1 I Cache 32 KB L1 D Cache Core Complex Bus e500 Coherency Module OCeaN 16 Gb/s RapidIO-8 133 MHz PCI 64b IRQs SDRAM DDR GPIO 32b Programmable Interrupt Controller MPHY RMIIs

Page 4

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 3 Overview — Executes code from internal ROM or instruction RAM — 32-bit RISC architecture — Tuned for communication environments: instruction set supports CRC computation and bit manipulation. — Internal timer — Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller — Handles serial protocols and virtual DMA. — Three full-duplex fast serial communications controllers (FCCs) that support the following protocols: – ATM protocol through UTOPIA interface (FCC1 and FCC2 only) – IEEE Std 802.3™/Fast Ethernet – HDLC – Totally transparent operation — Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces — Four full-duplex serial communications controllers (SCCs) that support the following protocols: – High level/synchronous data link control (HDLC/SDLC) – LocalTalk (HDLC-based local area network protocol) – Universal asynchronous receiver transmitter (UART) – Synchronous UART (1x clock mode) – Binary synchronous communication (BISYNC) – Totally transparent operation — Serial peripheral interface (SPI) support for master or slave — I2C bus controller — Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following TDM formats: – T1/CEPT lines – T3/E3 – Pulse code modulation (PCM) highway interface – ISDN primary rate – Freescale interchip digital link (IDL) – General circuit interface (GCI) — User-defined interfaces — Eight independent baud rate generators (BRGs) — Four general-purpose 16-bit timers or two 32-bit timers

Page 5

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 4 Freescale Semiconductor Overview — General-purpose parallel ports—16 parallel I/O lines with interrupt capability — Supports inverse muxing of ATM cells (IMA) • 256 Kbyte L2 cache/SRAM — Can be configured as follows – Full cache mode (256-Kbyte cache). – Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block or two 128-Kbyte blocks) – Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM) — Full ECC support on 64-bit boundary in both cache and SRAM modes — Cache mode supports instruction caching, data caching, or both — External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing) — Eight-way set-associative cache organization (1024 sets of 32-byte cache lines) — Supports locking the entire cache or selected lines. Individual line locks are set and cleared through Book E instructions or by externally mastered transactions — Global locking and flash clearing done through writes to L2 configuration registers — Instruction and data locks can be flash cleared separately — Read and write buffering for internal bus accesses — SRAM features include the following: – I/O devices access SRAM regions by marking transactions as snoopable (global) – Regions can reside at any aligned location in the memory map – Byte accessible ECC is protected using read-modify-write transactions accesses for smaller than cache-line accesses. • Address translation and mapping unit (ATMU) — Eight local access windows define mapping within local 32-bit address space — Inbound and outbound ATMUs map to larger external address spaces – Three inbound windows plus a configuration window on PCI/PCI-X – Four inbound windows plus a default and configuration window on RapidIO – Four outbound windows plus default translation for PCI – Eight outbound windows plus default translation for RapidIO • DDR memory controller — Programmable timing supporting DDR-1 SDRAM — 64-bit data interface, up to 333-MHz data rate — Four banks of memory supported, each up to 1 Gbyte — DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports — Full ECC support — Page mode support (up to 16 simultaneous open pages)

Page 6

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 5 Overview — Contiguous or discontiguous memory mapping — Read-modify-write support for RapidIO atomic increment, decrement, set, and clear transactions — Sleep mode support for self refresh SDRAM — Supports auto refreshing — On-the-fly power management using CKE signal — Registered DIMM support — Fast memory access via JTAG port — 2.5-V SSTL2 compatible I/O • RapidIO interface unit — 8-bit RapidIO I/O and messaging protocols — Source-synchronous double data rate (DDR) interfaces — Supports small type systems (small domain, 8-bit device ID) — Supports four priority levels (ordering within a level) — Reordering across priority levels — Maximum data payload of 256 bytes per packet — Packet pacing support at the physical layer — CRC protection for packets — Supports atomic operations increment, decrement, set, and clear — LVDS signaling • RapidIO–compliant message unit — One inbound data message structure (inbox) — One outbound data message structure (outbox) — Supports chaining and direct modes in the outbox — Support of up to 16 packets per message — Support of up to 256 bytes per packet and up to 4 Kbytes of data per message — Supports one inbound doorbell message structure • Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts — Supports 4 message interrupts with 32-bit messages — Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller — Four global high resolution timers/counters that can generate interrupts — Supports 22 other internal interrupt sources — Supports fully nested interrupt delivery — Interrupts can be routed to external pin for external processing

Page 7

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 6 Freescale Semiconductor Overview — Interrupts can be routed to the e500 core’s standard or critical interrupt inputs — Interrupt summary registers allow fast identification of interrupt source • I2C controller — Two-wire interface — Multiple master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus • Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I2C addressing mode — Data integrity checked with preamble signature and CRC • Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 166 MHz — Eight chip selects support eight external slaves — Up to eight-beat burst transfers — The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller — Three protocol engines available on a per chip select basis: – General purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – Dedicated single data rate SDRAM controller — Parity support — Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit) • Two three-speed (10/100/1Gb) Ethernet controllers (TSECs) — Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers — Support for different Ethernet physical interfaces: – 10/100/1Gb Mbps IEEE 802.3 GMII – 10/100 Mbps IEEE 802.3 MII – 10 Mbps IEEE 802.3 MII – 1000 Mbps IEEE 802.3z TBI – 10/100/1Gb Mbps RGMII/RTBI — Full- and half-duplex support — Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100 programming models — 9.6-Kbyte jumbo frame support — RMON statistics support — 2-Kbyte internal transmit and receive FIFOs

Page 8

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 7 Overview — MII management interface for control and status — Programmable CRC generation and checking — Ability to force allocation of header information and buffer descriptors into L2 cache. • OCeaN switch fabric — Four-port crossbar packet switch — Reorders packets from a source based on priorities — Reorders packets to bypass blocked packets — Implements starvation avoidance algorithms — Supports packets with payloads of up to 256 bytes • Integrated DMA controller — Four-channel controller — All channels accessible by both the local and remote masters — Extended DMA functions (advanced chaining and striding capability) — Support for scatter and gather transfers — Misaligned transfer capability — Interrupt on completed segment, link, list, and error — Supports transfers to or from any local memory or I/O port — Selectable hardware-enforced coherency (snoop/no-snoop) — Ability to start and flow control each DMA channel from external 3-pin interface — Ability to launch DMA from single write transaction • PCI/PCI-X controller — PCI 2.2 and PCI-X 1.0 compatible — 64- or 32-bit PCI port supports at 16 to 66 MHz — 64-bit PCI-X support up to 133 MHz — Host and agent mode support — 64-bit dual address cycle (DAC) support — PCI-X supports multiple split transactions — Supports PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses — Supports posting of processor-to-PCI and PCI-to-memory writes — PCI 3.3-V compatible — Selectable hardware-enforced coherency • Power management — Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O — Supports power saving modes: doze, nap, and sleep — Employs dynamic power management, which automatically minimizes power consumption of blocks when they are idle.

Page 9

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 8 Freescale Semiconductor Electrical Characteristics • System performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow • System access port — Uses JTAG interface and a TAP controller to access entire system memory map — Supports 32-bit accesses to configuration registers — Supports cache-line burst accesses to main memory — Supports large block (4-Kbyte) uploads and downloads — Supports continuous bit streaming of entire block for fast upload and download • IEEE Std 1149.1™-compliant, JTAG boundary scan • 783 FC-PBGA package 2 Electrical Characteristics This section provides the electrical specifications and thermal characteristics for the MPC8560. The MPC8560 is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1 Characteristic Symbol Max Value Unit Notes Core supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz VDD –0.3 to 1.32 –0.3 to 1.43 V — PLL supply voltage For devices rated at 667 and 833 MHz For devices rated at 1 GHz AVDD –0.3 to 1.32 –0.3 to 1.43 V —

Page 10

MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 Freescale Semiconductor 9 Electrical Characteristics 2.1.2 Power Sequencing The MPC8560 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up: 1. VDD, AVDD 2. GVDD, LVDD, OVDD (I/O supplies) Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach 10 percent of theirs. DDR DRAM I/O voltage GVDD –0.3 to 3.63 V — Three-speed Ethernet I/O voltage LVDD –0.3 to 3.63 –0.3 to 2.75 V — CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII management, DUART, system control and power management, I2C, and JTAG I/O voltage OVDD –0.3 to 3.63 V 3 Input voltage DDR DRAM signals MVIN –0.3 to (GVDD + 0.3) V 2, 5 DDR DRAM reference MVREF –0.3 to (GVDD + 0.3) V 2, 5 Three-speed Ethernet signals LVIN –0.3 to (LVDD + 0.3) V 4, 5 CPM, Local bus, RapidIO, 10/100 Ethernet, SYSCLK, system control and power management, I2C, and JTAG signals OVIN –0.3 to (OVDD + 0.3) V 5 PCI/PCI-X OVIN –0.3 to (OVDD + 0.3) V 6 Storage temperature range TSTG –55 to 150 °C — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3. Table 1. Absolute Maximum Ratings 1 (continued) Characteristic Symbol Max Value Unit Notes

MPC8560PX667LC Reviews

Average User Rating
5 / 5 (106)
★ ★ ★ ★ ★
5 ★
95
4 ★
11
3 ★
0
2 ★
0
1 ★
0

Coen*****lick

January 2, 2020

Great item at a great price. Quick shipping. Nice seller. Rad transaction!

Aval*****oach

November 27, 2019

Perfect! Nice components, professional service!

Daria*****dhyay

November 18, 2019

Have never had a problem with my order. Packages arrive on time and in great condition.

Augu***** Banks

November 7, 2019

Great Seller, Great Item, the quality is great, Highly Recommended.

Dul*****Ramos

August 31, 2019

Great capacitors. very fast post very good communication.

Wil*****ove

June 30, 2019

You're my good supplier. I appreciate Heisener Electronics on many levels.

Adeli*****awford

June 25, 2019

The items I want are often in stock and available in small quantities.

Tat*****Solis

June 2, 2019

the parts work as they should. Amazing price perfect all round many thanks

Cla*****Mani

May 1, 2019

Worked good to turn my AC welder into a DC welder.

Harl*****rince

April 25, 2019

2nd time buying these - quite good. Very fast shipping

MPC8560PX667LC Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

MPC8560PX667LC Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

MPC8560PX667LC Related Products

hotMPC8560PX667LC MRF6S19100HR3 NXP, FET RF 68V 1.99GHZ NI-780, NI-780, MPC85xx View
hotMPC8560PX667LC MRF8P29300HR6 NXP, FET RF 2CH 65V 2.9GHZ NI1230, NI-1230, MPC85xx View
hotMPC8560PX667LC NX3P1108UKZ NXP, IC HIGH SIDE PWR SWITCH 4WLCSP, 4-UFBGA, WLCSP, MPC85xx View
hotMPC8560PX667LC BGY1085A,112 NXP, IC AMP PUSH PULL SOT115J, SOT-115J, MPC85xx View
hotMPC8560PX667LC MPC8535EBVTANGA NXP, IC MPU MPC85XX 800MHZ 783FCBGA, 783-BBGA, FCBGA, MPC85xx View
hotMPC8560PX667LC MPC8572VTAULB NXP, IC MPU MPC85XX 1.333GHZ 1023BGA, 1023-BFBGA, FCBGA, MPC85xx View
hotMPC8560PX667LC MPC8313EZQAFF NXP, IC MPU MPC83XX 333MHZ 516BGA, 516-BBGA Exposed Pad, MPC85xx View
hotMPC8560PX667LC MPC8360CVVADDH NXP, IC MPU MPC83XX 266MHZ 740TBGA, 740-LBGA, MPC85xx View
hotMPC8560PX667LC MPC8555PXAJD NXP, IC MPU MPC85XX 533MHZ 783FCBGA, 783-BBGA, FCBGA, MPC85xx View
hotMPC8560PX667LC MPC8264ACZUMIBB NXP, IC MPU MPC82XX 266MHZ 408TBGA, 480-LBGA, MPC85xx View
hotMPC8560PX667LC MPC860DPCVR50D4 NXP, IC MPU MPC8XX 50MHZ 357BGA, 357-BBGA, MPC85xx View
hotMPC8560PX667LC P4080NXE7PNAC NXP, IC MPU Q OR IQ 1.5GHZ 1295FCBGA, 1295-BBGA, FCBGA, MPC85xx View

MPC8560PX667LC Tags

  • MPC8560PX667LC
  • MPC8560PX667LC PDF
  • MPC8560PX667LC datasheet
  • MPC8560PX667LC specification
  • MPC8560PX667LC image
  • NXP
  • NXP MPC8560PX667LC
  • buy MPC8560PX667LC
  • MPC8560PX667LC price
  • MPC8560PX667LC distributor
  • MPC8560PX667LC supplier
  • MPC8560PX667LC wholesales

MPC8560PX667LC is Available in