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Part Number MPC9658AC
Manufacturer NXP
Description IC PLL CLK GENERATOR 1:10 32LQFP
Datasheet MPC9658AC Datasheet
Package 32-LQFP
In Stock 426 piece(s)
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Part Number # MPC9658AC (Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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MPC9658AC Specifications

CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet MPC9658ACDatasheet
TypeClock Generator, Fanout Distribution, Multiplexer, Zero Delay Buffer
PLLYes with Bypass
Number of Circuits1
Ratio - Input:Output1:10
Differential - Input:OutputYes/No
Frequency - Max250MHz
Voltage - Supply3.135 V ~ 3.465 V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case32-LQFP
Supplier Device Package32-LQFP (7x7)

MPC9658AC Datasheet

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MPC9658 Rev 5, 10/2004 Freescale Semiconductor Technical Data3.3 V 1:10 LVCMOS PLL Clock Generator The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 MHz and output skews less than 120 ps the device meets the needs of the most demanding clock applications. The MPC9658 is specified for the temperature range of 0°C to +70°C. Features • 1:10 PLL based low-voltage clock generator • Supports zero-delay operation • 3.3 V power supply • Generates clock signals up to 250 MHz • Maximum output skew of 120 ps • Differential LVPECL reference clock input • External PLL feedback • Drives up to 20 clock lines • 32-lead LQFP packaging • 32-lead Pb-free Package Available • Pin and function compatible to the MPC958 Functional Description The MPC9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency. The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se- lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by- pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω trans- mission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the de- vices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP package. MPC9658 LOW VOLTAGE 3.3 V LVCMOS 1:10 PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03© Freescale Semiconductor, Inc., 2004. All rights reserved.

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Figure 1. MPC9658 Logic Diagram Figure 2. MPC9658 32-Lead Pinout (Top View) 1 0 1 0÷ 1 3⋅25 k VCC & 1 0 VCC 2⋅25 k PCLK Q0 Q1 Q2 Q3 Q4 VCO Q5 Q6 Q7 QFB PCLK FB_IN PLL_EN VCO_SEL BYPASS MR/OE ÷ 2 25 k Ref FB PLL 200 – 480 MHz VCC 25 k Q8 Q9 ÷ 2 GND Q1 VCC Q0 GND QFB VCC Q6 VCC Q7 GND Q8 VCC Q 2 V C C Q 3 G N D Q 4 V C C Q 5 G N D V C C _P LL FB _I N BY PA SS PL L_ EN M R /O E PC LK PC LK G N D 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 MPC9658 VCO_SEL Q9 GNDAdvanced Clock Drivers Device Data 2 Freescale Semiconductor MPC9658

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Table 1. Pin Configurations Number Name Type Description PCLK, PCLK Input LVPECL PECL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to QFB VCO_SEL Input LVCMOS Operating frequency range select BYPASS Input LVCMOS PLL and output divider bypass select PLL_EN Input LVCMOS PLL enable/disable MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset Q0–9 Output LVCMOS Clock outputs QFB Output LVCMOS Clock output for PLL feedback, connect to FB_IN GND Supply Ground Negative power supply (GND) VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Refer to APPLICATIONS INFORMATION for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. Table 2. Function Table Control Default 0 1 PLL_EN 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the VCO output.(1) 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. MPC9658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the output dividers. VCO_SEL 1 VCO ÷ 1 (High frequency range). fREF = fQ0–9 = 2 ⋅ fVCO VCO ÷ 2 (Low output range). fREF = fQ0–9 = 4 ⋅ fVCO MR/OE 0 Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). Table 3. Absolute Maximum Ratings(1) 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Symbol Characteristics Min Max Unit Condition VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC +0.3 V VOUT DC Output Voltage –0.3 VCC +0.3 V IIN DC Input Current ±20 mA IOUT DC Output Current ±50 mA TS Storage Temperature –65 125 °CAdvanced Clock Drivers Device Data Freescale Semiconductor 3 MPC9658

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Table 4. General Specifications Symbol Characteristics Min Typ Max Unit Condition VTT Output Termination Voltage VCC ÷ 2 V MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance 4.0 pF Inputs θJA LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, 2S2P multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min θJC LQFP 32 Thermal resistance junction to case 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VPP Peak-to-Peak Input Voltage (PCLK) 250 mV LVPECL VCMR (1) 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Common Mode Range (PCLK) 1.0 VCC –0.6 V LVPECL VOH Output High Voltage 2.4 V IOH = –24 mA (2) 2. The MPC9658 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. VOL Output Low Voltage (3) 3. The MPC9658 output levels are compatible to the MPC958 output levels. 0.55 0.30 V V IOL = 24 mA IOL = 12 mA ZOUT Output Impedance 14 – 17 Ω IIN Input Current (4) 4. Inputs have pull-down resistors affecting the input current. ±200 µA VIN = VCC or GND ICC_PLL Maximum PLL Supply Current 12 20 mA VCC_PLL Pin ICCQ Maximum Quiescent Supply Current 13 20 mA All VCC PinsAdvanced Clock Drivers Device Data 4 Freescale Semiconductor MPC9658

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Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C) (1) 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. Symbol Characteristics Min Typ Max Unit Condition fREF Input reference frequency ÷ 2 feedback (2) PLL mode, external feedback ÷ 4 feedback(3) Input reference frequency in PLL bypass mode(4) 2. ÷ 2 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. 3. ÷ 4 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE = 0. 4. In bypass mode, the MPC9658 divides the input reference clock. 100 50 0 250 125 250 MHz MHz MHz PLL locked PLL locked fVCO VCO lock frequency range (5) 5. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB. 200 500 MHz fMAX Output Frequency ÷ 2 feedback (3) ÷ 4 feedback(4) 100 50 250 125 MHz MHz PLL locked PLL locked VPP Peak-to-peak input voltage (PCLK) 500 1000 mV LVPECL VCMR (6) 6. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). Common Mode Range (PCLK) 1.2 VCC –0.9 V LVPECL tPW,MIN Input Reference Pulse Width (7) 7. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF,MIN. 2.0 ns t(∅) Propagation Delay (static phase offset) PCLK to FB_IN fREF = 100 MHz any frequency –70 –125 +80 +125 ps ps PLL locked tPD Propagation Delay (PLL and divider bypass) PCLK to Q0-9 1.0 4.0 ns tsk(O) Output-to-output Skew (8) 8. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode. 120 ps DC Output Duty Cycle(9) 9. Output duty cycle is DC = (0.5 ± 400 ps ⋅ fOUT) Þ 100%. For example, the DC range at fOUT = 100MHz is 46% < DC < 54%. T = output period. (T ÷ 2)–400 T ÷ 2 (T ÷ 2)+400 ps tr, tf Output Rise/Fall Time 0.1 1.0 ns 0.55 to 2.4 V tPLZ, HZ Output Disable Time 7.0 ns tPZL, LZ Output Enable Time 6.0 ns tJIT(CC) Cycle-to-cycle jitter 80 ps tJIT(PER) Period Jitter 80 ps tJIT(∅) I/O Phase Jitter fVCO = 500 MHz and ÷ 2 feedback, RMS (1σ) (10) fVCO = 500 MHz and ÷ 4 feedback, RMS (1σ) 10. Refer to APPLICATIONS INFORMATION for a jitter calculation for other confidence factors than 1 σ and a characteristic for other VCO frequencies. 5.5 6.5 ps ps BW PLL closed loop bandwidth(11) ÷ 2 feedback(3) ÷ 4 feedback(5) 11. –3 dB point of PLL transfer characteristics. 6 – 20 2 – 8 MHz MHz tLOCK Maximum PLL Lock Time 10 msAdvanced Clock Drivers Device Data Freescale Semiconductor 5 MPC9658

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APPLICATIONS INFORMATION Programming the MPC9658 The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 MHz for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125 MHz and 100 to 250 MHz. Table 7. MPC9658 Configurations (QFB connected to FB_IN) illustrates the configurations supported by the MPC9658. PLL zero-delay is supported if BYPASS = 1, PLL_EN = 1, and the input frequency is within the specified PLL reference frequency range. Power Supply Filtering The MPC9658 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9658 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9658. Figure 3 illustrates a typical power supply filter scheme. The MPC9658 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 12 mA (20 mA maximum), assuming that a minimum of 2.835 V must be maintained on the VCC_PLL pin. Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3 – 5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9658 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the MPC9658 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9658. Designs using the MPC9658 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9658 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Table 7. MPC9658 Configurations (QFB connected to FB_IN) BYPASS PLL_EN VCO_SEL Operation Frequency Ratio Output range (fQ0–9) VCO 0 X X Test mode: PLL and divider bypass fQ0–9 = fREF 0 – 250 MHz n/a 1 0 0 Test mode: PLL bypass fQ0–9 = fREF ÷ 2 0 – 125 MHz n/a 1 0 1 Test mode: PLL bypass fQ0–9 = fREF ÷ 4 0 – 62.5 MHz n/a 1 1 0 PLL mode (high frequency range) fQ0–9 = fREF 100 – 250 MHz fVCO = fREF ⋅ 2 1 1 1 PLL mode (low frequency range) fQ0–9 = fREF 50 – 125 MHz fVCO = fREF ⋅ 4 VCC_PLL VCC MPC965810 nF RF = 5–15 Ω CF = 22 µF CF 33...100 nF RF VCCAdvanced Clock Drivers Device Data 6 Freescale Semiconductor MPC9658

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Calculation of Part-to-Part Skew The MPC9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9658 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t(∅) + tSK(O) + tPD, LINE(FB) + tJIT(∅) ⋅ CF This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: Figure 4. MPC9658 Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst case timing uncertainty from input to any output of –214 ps to 224 ps relative to PCKL (fREF = 100 MHz, FB = ³4, tjit(∅) = 8 ps RMS at fVCO = 400 MHz): tSK(PP) = [–70ps...80ps] + [–120ps...120ps] + [(8ps ⋅ –3)...(8ps ⋅ 3)] + tPD, LINE(FB) tSK(PP) = [–214ps...224ps] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a more precise timing performance analysis. Figure 5. Max. I/O Jitter versus Frequency Driving Transmission Lines The MPC9658 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale Semiconductor Application Note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC ÷ 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9658 clock driver. However, for the series terminated case there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the MPC9658 clock driver is effectively doubled due to its capability to drive multiple lines. Table 8. Confidence Factor CF CF Probability of clock edge within the distribution ± 1σ 0.68268948 ± 2σ 0.95449988 ± 3σ 0.99730007 ± 4σ 0.99993663 ± 5σ 0.99999943 ± 6σ 0.99999999 tPD,LINE(FB) tJIT(∅) +tSK(O) —t(ý) +t(∅) tJIT(∅) +tSK(O) tSK(PP) Max. skew TCLKCommon QFBDevice 1 Any QDevice 1 QFBDevice2 Any QDevice 2 FCO Frequency [MHz] 200 250 300 350 400 450 500 FB = ³ 4 FB = ³ 2 0 15 10 5 20 t jit (f) [p s] R M S I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FBAdvanced Clock Drivers Device Data Freescale Semiconductor 7 MPC9658

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Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9658 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9658. The output waveform in Figure 7 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS (Z0 ÷ (RS+R0 +Z0)) Z0 = 50 Ω || 50 Ω RS = 36 Ω || 36 Ω R0 = 14 Ω VL = 3.0 (25 ÷ (18+14+25) = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering. However, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 8 should be used. In this case, the series terminating resistors are reduced such that, when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. Figure 8. Optimized Dual Line Termination Figure 9. PCLK MPC9658 AC Test Reference 14 Ω In MPC958 Output Buffer RS = 36 Ω ZO = 50 Ω OutA 14 ΩIn MPC958 Output Buffe RS = 36 Ω ZO = 50 Ω OutB0 RS = 36 Ω ZO = 50 Ω OutB1 Time (ns) Vo lta ge (V ) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 OutB tD = 3.9386 OutA tD = 3.8956 In 14 Ω MPC958 Output Buffe RS = 22 Ω ZO = 50 Ω RS = 22 Ω ZO = 50 Ω 14 Ω + 22 Ω || 22Ω = 50 Ω || 50 Ω 25 Ω = 25 Ω Pulse Generator Z = 50 Ω RT = 50 Ω ZO = 50 Ω RT = 50 Ω ZO = 50 Ω MPC9658 DUT VTT VTTAdvanced Clock Drivers Device Data 8 Freescale Semiconductor MPC9658

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Figure 12. Output Duty Cycle (DC) Figure 10. Output-to-Output Skew tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device VCC VCC ÷ 2 GND VCC VCC ÷ 2 GND tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage VCC VCC ÷ 2 GND tP T0 DC = tP/T0 x 100% Figure 14. Cycle-to-Cycle Jitter Figure 13. I/O Jitter Figure 16. Output Transition Time Test Reference tF tR VCC=3.3 V 2.4 0.55 TJIT(∅) = |T0–T1mean| PCLK FB_IN The deviation in t0 for a controlled edge with respect to a T0 mean in a random sample of cycles The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TN TJIT(CC) = |TN–TN+1| TN+1 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles TJIT(PER) = |TN–1/f0| T0 Figure 15. Period Jitter Figure 11. Propagation Delay (t(PD), static phase offset) Test Reference VCC VCC ÷ 2 GND t(PD) PCLK FB_IN PCLK VPP = 0.8V VCMR = VCC–1.3VAdvanced Clock Drivers Device Data Freescale Semiconductor 9 MPC9658

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June 9, 2020

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June 9, 2020

On time and as described, fast delivery. Would definitely buy again. Thx.

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June 1, 2020

Always meet my expectations with order and questions.


May 28, 2020

Works just like the original one and even has the correct connectors installed.


May 27, 2020

It arrived on time. I was able to finish a repair before Sunday service and with no over time. Easy to work with.


May 25, 2020

Itams as described Fast and cheap shipping.


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