Contact Us
SalesDept@heisener.com +86-755-83210559 ext. 811

MT41K256M16TW-093:P

MT41K256M16TW-093:P

MT41K256M16TW-093:P

For Reference Only

Part Number MT41K256M16TW-093:P
Manufacturer Micron Technology Inc.
Description IC SDRAM 4GBIT 1067MHZ 96BGA
Datasheet MT41K256M16TW-093:P Datasheet
Package 96-TFBGA
In Stock 264 piece(s)
Unit Price $ 10.6031 *
Lead Time To be Confirmed
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
Request for Quotation

Part Number # MT41K256M16TW-093:P (Memory) is manufactured by Micron Technology Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For MT41K256M16TW-093:P specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add MT41K256M16TW-093:P with quantity into BOM. Heisener.com does NOT require any registration to request a quote of MT41K256M16TW-093:P.

MT41K256M16TW-093:P Specifications

ManufacturerMicron Technology Inc.
CategoryIntegrated Circuits (ICs) - Memory
Datasheet MT41K256M16TW-093:PDatasheet
Package96-TFBGA
Series-
Memory TypeVolatile
Memory FormatDRAM
TechnologySDRAM - DDR3L
Memory Size4Gb (256M x 16)
Memory InterfaceParallel
Clock Frequency1067MHz
Write Cycle Time - Word, Page-
Access Time20ns
Voltage - Supply1.283 V ~ 1.45 V
Operating Temperature0°C ~ 95°C (TC)
Mounting TypeSurface Mount
Package / Case96-TFBGA
Supplier Device Package96-FBGA (8x14)

MT41K256M16TW-093:P Datasheet

Page 1

Page 2

DDR3L SDRAM MT41K1G4 – 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die Rev :E) data sheet specifications when running in 1.5V compatible mode. Features • VDD = VDDQ = 1.35V (1.283–1.45V) • Backward compatible to VDD = VDDQ = 1.5V ±0.075V – Supports DDR3L devices to be backward com- patible in 1.5V applications • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • TC of 105°C – 64ms, 8192-cycle refresh up to 85°C – 32ms, 8192-cycle refresh at >85°C to 95°C – 16ms, 8192-cycle refresh at >95°C to 105°C • Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration Options Marking • Configuration – 1 Gig x 4 1G4 – 512 Meg x 8 512M8 – 256 Meg x 16 256M16 • FBGA package (Pb-free) – x4, x8 – 78-ball (9mm x 10.5mm) Rev. E RH – 78-ball (7.5mm x 10.6mm) Rev. N RG – 78-ball (8mm x 10.5mm) Rev. P DA • FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) Rev. E HA – 96-ball (7.5mm x 13.5mm) Rev. N LY – 96-ball (8mm x 14mm) Rev. P TW • Timing – cycle time – 938ps @ CL = 14 (DDR3-2133) -093 – 1.07ns @ CL = 13 (DDR3-1866) -107 – 1.25ns @ CL = 11 (DDR3-1600) -125 • Operating temperature – Commercial (0°C TC +95°C) None – Industrial (–40°C TC +95°C) IT – Automotive (–40°C TC +105°C) AT • Revision :E/:N/:P Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) CL (ns) -093 1, 2 2133 14-14-14 13.09 13.09 13.09 -107 1 1866 13-13-13 13.91 13.91 13.91 -125 1600 11-11-11 13.75 13.75 13.75 Notes: 1. Backward compatible to 1600, CL = 11 (-125). 2. Backward compatible to 1866, CL = 13 (-107). 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.

Page 3

Table 2: Addressing Parameter 1 Gig x 4 512 Meg x 8 256 Meg x 16 Configuration 128 Meg x 4 x 8 banks 64 Meg x 8 x 8 banks 32 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 64K (A[15:0]) 64K (A[15:0]) 32K (A[14:0]) Bank address 8 (BA[2:0]) 8 (BA[2:0]) 8 (BA[2:0]) Column address 2K (A[11, 9:0]) 1K (A[9:0]) 1K (A[9:0]) Page size 1KB 1KB 2KB Figure 1: DDR3L Part Numbers Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 4

Contents Important Notes and Warnings ....................................................................................................................... 11 State Diagram ................................................................................................................................................ 12 Functional Description ................................................................................................................................... 13 Industrial Temperature ............................................................................................................................... 13 Automotive Temperature ............................................................................................................................ 13 General Notes ............................................................................................................................................ 14 Functional Block Diagrams ............................................................................................................................. 15 Ball Assignments and Descriptions ................................................................................................................. 17 Package Dimensions ....................................................................................................................................... 23 Electrical Specifications .................................................................................................................................. 29 Absolute Ratings ......................................................................................................................................... 29 Input/Output Capacitance .......................................................................................................................... 30 Thermal Characteristics .................................................................................................................................. 31 Electrical Specifications – IDD Specifications and Conditions ............................................................................ 33 Electrical Characteristics – Operating IDD Specifications .................................................................................. 44 Electrical Specifications – DC and AC .............................................................................................................. 49 DC Operating Conditions ........................................................................................................................... 49 Input Operating Conditions ........................................................................................................................ 50 DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 54 DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 57 DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 59 ODT Characteristics ....................................................................................................................................... 60 1.35V ODT Resistors ................................................................................................................................... 61 ODT Sensitivity .......................................................................................................................................... 62 ODT Timing Definitions ............................................................................................................................. 62 Output Driver Impedance ............................................................................................................................... 66 34 Ohm Output Driver Impedance .............................................................................................................. 67 DDR3L 34 Ohm Driver ................................................................................................................................ 68 DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 69 DDR3L Alternative 40 Ohm Driver ............................................................................................................... 70 DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 70 Output Characteristics and Operating Conditions ............................................................................................ 72 Reference Output Load ............................................................................................................................... 75 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 75 Slew Rate Definitions for Differential Output Signals .................................................................................... 77 Speed Bin Tables ............................................................................................................................................ 78 Electrical Characteristics and AC Operating Conditions ................................................................................... 83 Command and Address Setup, Hold, and Derating .......................................................................................... 103 Data Setup, Hold, and Derating ...................................................................................................................... 110 Commands – Truth Tables ............................................................................................................................. 118 Commands ................................................................................................................................................... 121 DESELECT ................................................................................................................................................ 121 NO OPERATION ........................................................................................................................................ 121 ZQ CALIBRATION LONG ........................................................................................................................... 121 ZQ CALIBRATION SHORT .......................................................................................................................... 121 ACTIVATE ................................................................................................................................................. 121 READ ........................................................................................................................................................ 121 WRITE ...................................................................................................................................................... 122 PRECHARGE ............................................................................................................................................. 123 REFRESH .................................................................................................................................................. 123 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 5

SELF REFRESH .......................................................................................................................................... 124 DLL Disable Mode ..................................................................................................................................... 125 Input Clock Frequency Change ...................................................................................................................... 129 Write Leveling ............................................................................................................................................... 131 Write Leveling Procedure ........................................................................................................................... 133 Write Leveling Mode Exit Procedure ........................................................................................................... 135 Initialization ................................................................................................................................................. 136 Voltage Initialization/Change ........................................................................................................................ 138 VDD Voltage Switching ............................................................................................................................... 139 Mode Registers .............................................................................................................................................. 140 Mode Register 0 (MR0) ................................................................................................................................... 141 Burst Length ............................................................................................................................................. 141 Burst Type ................................................................................................................................................. 142 DLL RESET ................................................................................................................................................ 143 Write Recovery .......................................................................................................................................... 144 Precharge Power-Down (Precharge PD) ...................................................................................................... 144 CAS Latency (CL) ....................................................................................................................................... 144 Mode Register 1 (MR1) ................................................................................................................................... 146 DLL Enable/DLL Disable ........................................................................................................................... 146 Output Drive Strength ............................................................................................................................... 147 OUTPUT ENABLE/DISABLE ...................................................................................................................... 147 TDQS Enable ............................................................................................................................................. 147 On-Die Termination .................................................................................................................................. 148 WRITE LEVELING ..................................................................................................................................... 148 POSTED CAS ADDITIVE Latency ................................................................................................................ 148 Mode Register 2 (MR2) ................................................................................................................................... 149 CAS Write Latency (CWL) ........................................................................................................................... 150 AUTO SELF REFRESH (ASR) ....................................................................................................................... 150 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 150 SRT vs. ASR ............................................................................................................................................... 151 DYNAMIC ODT ......................................................................................................................................... 151 Mode Register 3 (MR3) ................................................................................................................................... 151 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 152 MPR Functional Description ...................................................................................................................... 153 MPR Register Address Definitions and Bursting Order ................................................................................. 154 MPR Read Predefined Pattern .................................................................................................................... 159 MODE REGISTER SET (MRS) Command ........................................................................................................ 159 ZQ CALIBRATION Operation ......................................................................................................................... 160 ACTIVATE Operation ..................................................................................................................................... 161 READ Operation ............................................................................................................................................ 163 WRITE Operation .......................................................................................................................................... 174 DQ Input Timing ....................................................................................................................................... 182 PRECHARGE Operation ................................................................................................................................. 184 SELF REFRESH Operation .............................................................................................................................. 184 Extended Temperature Usage ........................................................................................................................ 186 Power-Down Mode ........................................................................................................................................ 187 RESET Operation ........................................................................................................................................... 195 On-Die Termination (ODT) ............................................................................................................................ 197 Functional Representation of ODT ............................................................................................................. 197 Nominal ODT ............................................................................................................................................ 197 Dynamic ODT ............................................................................................................................................... 199 Dynamic ODT Special Use Case ................................................................................................................. 199 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 6

Functional Description .............................................................................................................................. 199 Synchronous ODT Mode ................................................................................................................................ 205 ODT Latency and Posted ODT .................................................................................................................... 205 Timing Parameters .................................................................................................................................... 205 ODT Off During READs .............................................................................................................................. 208 Asynchronous ODT Mode .............................................................................................................................. 210 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 212 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 214 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 216 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 7

List of Figures Figure 1: DDR3L Part Numbers ........................................................................................................................ 2 Figure 2: Simplified State Diagram ................................................................................................................. 12 Figure 3: 1 Gig x 4 Functional Block Diagram .................................................................................................. 15 Figure 4: 512 Meg x 8 Functional Block Diagram ............................................................................................. 16 Figure 5: 256 Meg x 16 Functional Block Diagram ........................................................................................... 16 Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 17 Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 18 Figure 8: 78-Ball FBGA – x4, x8 (RH) ............................................................................................................... 23 Figure 9: 78-Ball FBGA – x4, x8 (RG) ............................................................................................................... 24 Figure 10: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................. 25 Figure 11: 96-Ball FBGA – x16 (HA) ................................................................................................................. 26 Figure 12: 96-Ball FBGA – x16 (LY) .................................................................................................................. 27 Figure 13: 96-Ball FBGA – x16 (TW) ................................................................................................................ 28 Figure 14: Thermal Measurement Point ......................................................................................................... 31 Figure 15: DDR3L 1.35V Input Signal .............................................................................................................. 53 Figure 16: Overshoot ..................................................................................................................................... 54 Figure 17: Undershoot ................................................................................................................................... 55 Figure 18: VIX for Differential Signals .............................................................................................................. 55 Figure 19: Single-Ended Requirements for Differential Signals ........................................................................ 55 Figure 20: Definition of Differential AC-Swing and tDVAC ............................................................................... 56 Figure 21: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 58 Figure 22: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 59 Figure 23: ODT Levels and I-V Characteristics ................................................................................................ 60 Figure 24: ODT Timing Reference Load .......................................................................................................... 63 Figure 25: tAON and tAOF Definitions ............................................................................................................ 64 Figure 26: tAONPD and tAOFPD Definitions ................................................................................................... 64 Figure 27: tADC Definition ............................................................................................................................. 65 Figure 28: Output Driver ................................................................................................................................ 66 Figure 29: DQ Output Signal .......................................................................................................................... 73 Figure 30: Differential Output Signal .............................................................................................................. 74 Figure 31: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 75 Figure 32: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 76 Figure 33: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 77 Figure 34: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 106 Figure 35: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 107 Figure 36: Tangent Line for tIS (Command and Address – Clock) .................................................................... 108 Figure 37: Tangent Line for tIH (Command and Address – Clock) .................................................................... 109 Figure 38: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 114 Figure 39: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 115 Figure 40: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 116 Figure 41: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 117 Figure 42: Refresh Mode ............................................................................................................................... 124 Figure 43: DLL Enable Mode to DLL Disable Mode ........................................................................................ 126 Figure 44: DLL Disable Mode to DLL Enable Mode ........................................................................................ 127 Figure 45: DLL Disable tDQSCK .................................................................................................................... 128 Figure 46: Change Frequency During Precharge Power-Down ........................................................................ 130 Figure 47: Write Leveling Concept ................................................................................................................. 131 Figure 48: Write Leveling Sequence ............................................................................................................... 134 Figure 49: Write Leveling Exit Procedure ....................................................................................................... 135 Figure 50: Initialization Sequence ................................................................................................................. 137 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 8

Figure 51: VDD Voltage Switching .................................................................................................................. 139 Figure 52: MRS to MRS Command Timing (tMRD) ......................................................................................... 140 Figure 53: MRS to nonMRS Command Timing (tMOD) .................................................................................. 141 Figure 54: Mode Register 0 (MR0) Definitions ................................................................................................ 142 Figure 55: READ Latency .............................................................................................................................. 145 Figure 56: Mode Register 1 (MR1) Definition ................................................................................................. 146 Figure 57: READ Latency (AL = 5, CL = 6) ....................................................................................................... 149 Figure 58: Mode Register 2 (MR2) Definition ................................................................................................. 149 Figure 59: CAS Write Latency ........................................................................................................................ 150 Figure 60: Mode Register 3 (MR3) Definition ................................................................................................. 152 Figure 61: Multipurpose Register (MPR) Block Diagram ................................................................................. 153 Figure 62: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 155 Figure 63: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 156 Figure 64: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 157 Figure 65: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 158 Figure 66: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 160 Figure 67: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 161 Figure 68: Example: tFAW ............................................................................................................................. 162 Figure 69: READ Latency .............................................................................................................................. 163 Figure 70: Consecutive READ Bursts (BL8) .................................................................................................... 165 Figure 71: Consecutive READ Bursts (BC4) .................................................................................................... 165 Figure 72: Nonconsecutive READ Bursts ....................................................................................................... 166 Figure 73: READ (BL8) to WRITE (BL8) .......................................................................................................... 166 Figure 74: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 167 Figure 75: READ to PRECHARGE (BL8) .......................................................................................................... 167 Figure 76: READ to PRECHARGE (BC4) ......................................................................................................... 168 Figure 77: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 168 Figure 78: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 168 Figure 79: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 170 Figure 80: Data Strobe Timing – READs ......................................................................................................... 171 Figure 81: Method for Calculating tLZ and tHZ ............................................................................................... 172 Figure 82: tRPRE Timing ............................................................................................................................... 172 Figure 83: tRPST Timing ............................................................................................................................... 173 Figure 84: tWPRE Timing .............................................................................................................................. 175 Figure 85: tWPST Timing .............................................................................................................................. 175 Figure 86: WRITE Burst ................................................................................................................................ 176 Figure 87: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 177 Figure 88: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 177 Figure 89: Nonconsecutive WRITE to WRITE ................................................................................................. 178 Figure 90: WRITE (BL8) to READ (BL8) .......................................................................................................... 178 Figure 91: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 179 Figure 92: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 180 Figure 93: WRITE (BL8) to PRECHARGE ........................................................................................................ 181 Figure 94: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 181 Figure 95: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 182 Figure 96: Data Input Timing ........................................................................................................................ 183 Figure 97: Self Refresh Entry/Exit Timing ...................................................................................................... 185 Figure 98: Active Power-Down Entry and Exit ................................................................................................ 189 Figure 99: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 189 Figure 100: Precharge Power-Down (Slow-Exit Mode) Entry and Exit .............................................................. 190 Figure 101: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ........................................... 190 Figure 102: Power-Down Entry After WRITE .................................................................................................. 191 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 9

Figure 103: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 191 Figure 104: REFRESH to Power-Down Entry .................................................................................................. 192 Figure 105: ACTIVATE to Power-Down Entry ................................................................................................. 192 Figure 106: PRECHARGE to Power-Down Entry ............................................................................................. 193 Figure 107: MRS Command to Power-Down Entry ......................................................................................... 193 Figure 108: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 194 Figure 109: RESET Sequence ......................................................................................................................... 196 Figure 110: On-Die Termination ................................................................................................................... 197 Figure 111: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 202 Figure 112: Dynamic ODT: Without WRITE Command .................................................................................. 202 Figure 113: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 203 Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 204 Figure 115: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 204 Figure 116: Synchronous ODT ...................................................................................................................... 206 Figure 117: Synchronous ODT (BC4) ............................................................................................................. 207 Figure 118: ODT During READs .................................................................................................................... 209 Figure 119: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 211 Figure 120: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 213 Figure 121: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 215 Figure 122: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 217 Figure 123: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 217 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

Page 10

List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 19 Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 21 Table 5: Absolute Maximum Ratings .............................................................................................................. 29 Table 6: DDR3L Input/Output Capacitance .................................................................................................... 30 Table 7: Thermal Characteristics .................................................................................................................... 31 Table 8: Thermal Impedance ......................................................................................................................... 32 Table 9: Timing Parameters Used for IDD Measurements – Clock Units ............................................................ 33 Table 10: IDD0 Measurement Loop .................................................................................................................. 34 Table 11: IDD1 Measurement Loop .................................................................................................................. 35 Table 12: IDD Measurement Conditions for Power-Down Currents ................................................................... 36 Table 13: IDD2N and IDD3N Measurement Loop ................................................................................................ 37 Table 14: IDD2NT Measurement Loop .............................................................................................................. 37 Table 15: IDD4R Measurement Loop ................................................................................................................ 38 Table 16: IDD4W Measurement Loop ............................................................................................................... 39 Table 17: IDD5B Measurement Loop ................................................................................................................ 40 Table 18: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 41 Table 19: IDD7 Measurement Loop .................................................................................................................. 42 Table 20: IDD Maximum Limits Die Rev. E for 1.35/1.5V Operation ................................................................... 44 Table 21: IDD Maximum Limits Die Rev. N for 1.35V/1.5V Operation ................................................................ 45 Table 22: IDD Maximum Limits Die Rev. P for 1.35V/1.5V Operation ................................................................. 47 Table 23: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 49 Table 24: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 50 Table 25: DDR3L 1.35V Input Switching Conditions – Command and Address ................................................. 51 Table 26: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 52 Table 27: DDR3L Control and Address Pins ..................................................................................................... 54 Table 28: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 54 Table 29: DDR3L 1.35V – Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ... 56 Table 30: Single-Ended Input Slew Rate Definition .......................................................................................... 57 Table 31: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 59 Table 32: On-Die Termination DC Electrical Characteristics ............................................................................ 60 Table 33: 1.35V RTT Effective Impedance ........................................................................................................ 61 Table 34: ODT Sensitivity Definition .............................................................................................................. 62 Table 35: ODT Temperature and Voltage Sensitivity ........................................................................................ 62 Table 36: ODT Timing Definitions .................................................................................................................. 63 Table 37: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 63 Table 38: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 67 Table 39: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 68 Table 40: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.35V ..................................... 68 Table 41: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.45V ..................................... 68 Table 42: DDR3L 34 Ohm Driver IOH/IOL Characteristics: VDD = VDDQ = DDR3L@1.283 ..................................... 69 Table 43: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 69 Table 44: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 69 Table 45: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 70 Table 46: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 70 Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 71 Table 48: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 72 Table 49: DDR3L Differential Output Driver Characteristics ............................................................................ 73 Table 50: DDR3L Differential Output Driver Characteristics VOX(AC) ................................................................. 74 4Gb: x4, x8, x16 DDR3L SDRAM Description 09005aef85af8fa8 4Gb_DDR3L.pdf - Rev. R 09/18 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2017 Micron Technology, Inc. All rights reserved.

MT41K256M16TW-093:P Reviews

Average User Rating
5 / 5 (146)
★ ★ ★ ★ ★
5 ★
131
4 ★
15
3 ★
0
2 ★
0
1 ★
0

Write a Review

Not Rated
Thanks for Your Review!

Kolt*****ccoy

May 29, 2020

All items individually packed in anti static bags and properly labeled.

Luk*****Costa

May 20, 2020

Used it on my system it works perfect as I need.

Juni*****Gupta

May 18, 2020

Fantastic quality products with fair and prompt shipping. Would save much time crossing all the features. Thank you for all your effort.

Slo*****Virk

May 11, 2020

Didn’t need so many but it was cheap. I did have to solder extra wire on each end to make fit better but exactly you need of your looking for this particular mod.

Zecha*****Salgado

May 8, 2020

2nd time buying these - quite good. Very fast shipping

Rei*****avala

April 30, 2020

They work great and I hope to find more used for the extra ones.

Aliv*****huja

April 25, 2020

Happy with purchase, would do business again

Alexan*****ndoval

April 16, 2020

Always the correct parts in the correct amounts are received. Fantastic Quality Control and Great Selection. Heisener has became to be one of my best suppliers for many years now.

Maj*****Bath

April 15, 2020

These are great for projects with the kids or doing any type of DIY projects. The case is nice to keep everything separated. Very nice.

Arma*****Branch

April 13, 2020

Easy transaction. Very pleased with goods in perfect condition would recommend Heisener company.

MT41K256M16TW-093:P Guarantees

Service Guarantee

Service Guarantees

We guarantee 100% customer satisfaction.

Our experienced sales team and tech support team back our services to satisfy all our customers.

Quality Guarantee

Quality Guarantees

We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

MT41K256M16TW-093:P Packaging

Verify Products
Customized Labels
Professional Packaging
Sealing
Packing
Insepction

MT41K256M16TW-093:P Related Products

T540D687M003BH8505WAFL T540D687M003BH8505WAFL KEMET, CAP TANT POLY 680UF 3V 2917, 2917 (7343 Metric), - View
T540B107M004AH85107280 T540B107M004AH85107280 KEMET, CAP TANT POLY 100UF 4V 1411, 1411 (3528 Metric), - View
hotMT29F64G08CBAAAWP:A MT29F64G08CBAAAWP:A Micron Technology Inc., IC FLASH 64GBIT 48TSOP, 48-TFSOP (0.724", 18.40mm Width), - View
R5F52318BDFP#30 R5F52318BDFP#30 Renesas Electronics America, IC MCU 32BIT 512KB FLASH 100LQFP, 100-LQFP, - View
PIC24EP128MC202-E/SS PIC24EP128MC202-E/SS Microchip Technology, IC MCU 16BIT 128KB FLASH 28SSOP, 28-SSOP (0.209", 5.30mm Width), - View
SSB-LXA100SRW SSB-LXA100SRW Lumex Opto/Components Inc., LED LT BAR 2CHP LOW-INT RED DIFF, -, - View
SMBJ120D-M3/H SMBJ120D-M3/H Vishay Semiconductor Diodes Division, TVS DIODE 120VWM 190VC DO214AA, DO-214AA, SMB, - View
RNCF0603BKE169K RNCF0603BKE169K Stackpole Electronics Inc., RES SMD 169K OHM 0.1% 1/10W 0603, 0603 (1608 Metric), - View
CRCW0402162RFKTD CRCW0402162RFKTD Vishay Dale, RES SMD 162 OHM 1% 1/16W 0402, 0402 (1005 Metric), - View
TVP00DZ-25-37AA TVP00DZ-25-37AA Amphenol Aerospace Operations, CONN RCPT HSG MALE 37POS PNL MT, -, - View
RBB90DHBN RBB90DHBN Sullins Connector Solutions, CONN EDGE DUAL FMALE 180POS .050, -, - View
REC5-1205DRW/H6/C/SMD REC5-1205DRW/H6/C/SMD Recom Power, CONV DC/DC 5W 9-18VIN +/-05VOUT, 24-SMD Module, 18 Leads, - View
Payment Methods
Delivery Services

Quick Inquiry

MT41K256M16TW-093:P

Certified Quality

Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

View the Certificates

Do you have any question about MT41K256M16TW-093:P?

+86-755-83210559 ext. 811 SalesDept@heisener.com heisener007 2354944915 Send Message

MT41K256M16TW-093:P Tags

  • MT41K256M16TW-093:P
  • MT41K256M16TW-093:P PDF
  • MT41K256M16TW-093:P datasheet
  • MT41K256M16TW-093:P specification
  • MT41K256M16TW-093:P image
  • Micron Technology Inc.
  • Micron Technology Inc. MT41K256M16TW-093:P
  • buy MT41K256M16TW-093:P
  • MT41K256M16TW-093:P price
  • MT41K256M16TW-093:P distributor
  • MT41K256M16TW-093:P supplier
  • MT41K256M16TW-093:P wholesales

MT41K256M16TW-093:P is Available in