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NJU3718G

hot NJU3718G

NJU3718G

For Reference Only

Part Number NJU3718G
Manufacturer NJR Corporation/NJRC
Description IC 20BIT SRL TO PRL CONVTR SO28
Datasheet NJU3718G Datasheet
Package 28-SOIC
In Stock 457 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 13 - Dec 18 (Choose Expedited Shipping)
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NJU3718G

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NJU3718G Specifications

ManufacturerNJR Corporation/NJRC
CategoryIntegrated Circuits (ICs) - Interface - Serializers, Deserializers
Datasheet NJU3718G Datasheet
Package28-SOIC
Series-
FunctionDeserializer
Input TypeSerial
Output TypeParallel
Number of Inputs1
Number of Outputs20
Voltage - Supply4.5 V ~ 5.5 V
Operating Temperature-25°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case28-SOIC

NJU3718G Datasheet

Page 1

Page 2

NJU3718 Ver.2003-11-18 20-BIT SERIAL TO PARALLEL CONVERTER GENERAL DESCRIPTION The NJU3718 is a 20-bit serial to parallel converter especially applying to MPU outport expander. The effective outport assignment of MPU is available as the connection between NJU3718 and MPU using only 4 lines. The serial data synchronizing with 5MHz or more clock can be input to the serial data input terminal and the data are output from parallel output buffer through serial in parallel out shift register and parallel data latches. Furthermore, the NJU3718 outputs the serial data from SO terminal through the shift register. Therefore, it connects with other SIPO ICs like as NJU3711 in cascade for expanding the parallel conversion outputs. The hysteresis input circuit realizes wide noise margin and the high drive-ability output buffer (25mA) can drive LED directly. FEATURES 20-Bit Serial In Parallel Out Hysteresis Input 0.5V typ Operating Voltage 5V±10% Maximum Operating Frequency 5MHz and more Output Current 25mA C-MOS Technology Package Outline SDIP28/SOP28/SDMP30 BLOCK DIAGRAM PA P P9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 P10 P11 P12 P13 P14 VSS NC P15 P16 P17 P18 P19 P20 SO NJU S hi ft R eg is te r Controller Circuit La tc h C irc ui t DATA CLK STB CLRCKAGE OUTLINE IN NJU3718M NJU3718G NJU3718L 37 CONFIGURATION - 1 - 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 VDD P8 P7 P6 P5 P4 P3 NC VSS P2 P1 CLR STB CLK DATA P9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P8 P7 P6 P5 P4 P3 VSS P2 P1 CLR STB CLK DATA P10 P11 P12 P13 P14 VSS P15 P16 P17 P18 P19 P20 SO 18M NJU3718L/G P1 P2 P3 P19 P20 SO

Page 3

NJU3718 - 2 - Ver.2003-11-18 TERMINAL DESCRIPTION No. SDIP28/SOP28 No. SDMP30 SYMBOL I/O FUNCTION 1 1 P9 O 2 2 P10 O 3 3 P11 O 4 4 P12 O 5 5 P13 O 6 6 P14 O Parallel Conversion Data Output Terminals 7 7 VSS - GND - 8 NC - Non Connection 8 9 P15 O 9 10 P16 O 10 11 P17 O 11 12 P18 O 12 13 P19 O 13 14 P20 O Parallel Conversion Data Output Terminals 14 15 SO O Serial Data Output Terminal 15 16 DATA I Serial Data Input Terminal 16 17 CLK I Clock Signal Input Terminal 17 18 STB I Strobe Signal Input Terminal 18 19 CLR I Clear Signal Input Terminal 19 20 P1 O 20 21 P2 O Parallel Conversion Data Output Terminals 21 22 VSS - GND - 23 NC - Non Connection 22 24 P3 O 23 25 P4 O 24 26 P5 O 25 27 P6 O 26 28 P7 O 27 29 P8 O Parallel Conversion Data Output Terminals 28 30 VDD - Power Supply Terminal (4.5 to 5.5V)

Page 4

NJU3555 718 - 3 - Ver.2003-11-18 FUNCTIONAL DESCRIPTION (1) Reset When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion output are "L" level. Normally, the CLR terminal should be "H" level. (2) Data Transmission In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal. When the STB terminal is changed to "L" level, the data in the shift register are transferred to the latches. Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore, the clock signal should be controlled for data order. (3) Cascade Connection The serial data input from DATA terminal is output from the SO terminal through internal shift register unrelated with the CLR and STB status. Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure to protect the noise. CLK STB CLR OPERATION X X L All of latches are reset (the data in the shift register is no change). All of parallel conversion outputs are "L". H H The serial data into the DATA terminal are inputted to the shift register. In this stage, the data in the latch is not changed. L H The data in the shift register is transferred to the latch. And the data in the latch is output from the parallel conversion output terminals. L H When the clock signal is inputted into the CLK terminal in state of the STB="L" and CLR="H", the data is shifted in the shift register and latched data is also changed in accordance with the shift register. Note 1) X: Don’t care

Page 5

NJU3718 - 4 - Ver.2003-11-18 TIMING CHART CLK CLR STB DATA P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 SO

Page 6

NJU3555 718 - 5 - Ver.2003-11-18 ABSOLUTE MAXIMUM RATINGS (Ta=25° C) PARAMETER SYMBOL RATINGS UNIT Supply Voltage Range VDD -0.5 ~ +7.0 V Input Voltage Range VI VSS-0.5 ~ VDD+0.5 V Output Voltage Range VO VSS-0.5 ~ VDD+0.5 V Output Current IO ±25 mA VO=7V, VI=0V 10 (max) Output Short Current (SO Terminal) (Note 5) IOS VO=0V, VI=7V -10 (max) mA VO=7V, VI=0V 20 (max) Output Short Current (P1~P20 Terminals) (Note 5) IOSD VO=0V, VI=7V -20 (max) mA Power Dissipation PD 700 (SDIP) 500 (SOP) 700 (SDMP) mW Operating Temperature Range Topr -25 ~ +85 ° C Storage Temperature Range Tstg -65 ~+150 ° C Note 2) All voltage are relative to VSS=0V reference. Note 3) Do not exceed the absolute maximum ratings, otherwise the stress may cause a permanent damage to the IC. It is also recommended that the IC be used in the range specified in the DC electrical characteristics, or the electrical stress may cause malfunctions and impact on the reliability. Note 4) To stabilize the IC operation, place decoupling capacitor between VDD and VSS. Note 5) VDD=7V, VSS=0V, less than 1 second per pin. DC ELECTRICAL CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=25° C, unless otherwise noted) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT Operating Voltage VDD 4.5 - 5.5 V Operating Current IDDS VIH=VDD, VIL=VSS - - 0.1 mA High-level Output Voltage VOH IOH=-0.4mA 4.0 - VDD V Low-level Output Voltage VOL IOL=+3.2mA SO Terminal VSS - 0.4 V High-level Input Voltage VIH 0.7VDD - VDD V Low-level Input Voltage VIL VSS - 0.3VDD V Input Leakage Current ILI VI=0~VDD -10 - 10 µA IOH=-25mA VDD-1.5 - VDD IOH=-15mA VDD-1.0 - VDD High-level Output Voltage (Note 6) VOHD IOH=-10mA P1~P20 Terminals VDD-0.5 - VDD V IOL=+25mA VSS - 1.5 IOL=+15mA VSS - 0.8 Low-level Output Voltage (Note 6) VOLD IOL=+10mA P1~P20 Terminals VSS - 0.4 V Note 6) Specified value represent output current per pin. When use, total current consideration and less than power dissipation in rating operation should be required.

Page 7

NJU3718 - 6 - Ver.2003-11-18 SWITCHING CHARACTERISTICS (VDD=4.5~5.5V, VSS=0V, Ta=25° C, unless otherwise noted) PARAMETER SYMBOL CONDITION MIN TYP MAX UNIT Set-Up Time tSD DATA-CLK 20 - - ns Hold Time tHD CLK-DATA 20 - - ns Set-Up Time tSSTB STB-CLK 30 - - ns Hold Time tHSTB CLK-STB 30 - - ns tpd O CLK-SO - - 70 ns tpd PCK CLK-P1~P20 - - 100 ns tpd PSTB STB-P1~P20 - - 80 ns Output Delay Time tpd PCLR CLR-P1~P20 - - 80 ns Maximum Operating Frequency fMAX 5 - - MHz Note 7) COUT=50pF

Page 8

NJU3555 718 - 7 - Ver.2003-11-18 SWITCHING CHARACTERISTICS TEST WAVEFORM fMAX tpd O CLK tSSTB tSD tHD tHSTB DATA STB CLK SO CLK P1~P20 STB tpd PCK L H P1~P20 tpd PSTB CLK STB H P1~P20 tpd PCLR CLR DATA

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