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P5P2305AF-1H08SR

hot P5P2305AF-1H08SR

P5P2305AF-1H08SR

For Reference Only

Part Number P5P2305AF-1H08SR
Manufacturer ON Semiconductor
Description IC BUFFER ZERO DELAY 3.3V 8-SOIC
Datasheet P5P2305AF-1H08SR Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 921 piece(s)
Unit Price $ 0.5642 *
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P5P2305AF-1H08SR

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P5P2305AF-1H08SR Specifications

ManufacturerON Semiconductor
CategoryIntegrated Circuits (ICs) - Clock/Timing - Clock Generators, PLLs, Frequency Synthesizers
Datasheet P5P2305AF-1H08SR Datasheet
Package8-SOIC (0.154", 3.90mm Width)
Series-
TypeZero Delay Buffer
PLLYes
InputClock
OutputClock
Number of Circuits1
Ratio - Input:Output1:5
Differential - Input:OutputNo/No
Frequency - Max133MHz
Divider/MultiplierNo/No
Voltage - Supply3 V ~ 3.6 V
Operating Temperature-40°C ~ 85°C
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

P5P2305AF-1H08SR Datasheet

Page 1

Page 2

ASM5P2305A, ASM5P2309A 3.3 V Zero Delay Buffer Description ASM5P2309A is a versatile, 3.3 V zero−delay buffer designed to distribute high−speed clocks. It accepts one reference input and drives out nine low−skew clocks. It is available in a 16−pin package. The ASM5P2305A is the eight−pin version of the ASM5P2309A. It accepts one reference input and drives out five low−skew clocks. The −1H version of the ASM5P230xA operates at up to 133 MHz frequencies, and has higher drive than the −1 devices. All parts have on−chip PLLs that lock to an input clock on the REF. The PLL feedback is on−chip and is obtained from the CLKOUT. http://onsemi.com ASM5P2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2309A and ASM5P2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 pS. All outputs have less than 200 pS of cycle−to−cycle jitter. The input and output propagation delay is guaranteed to be less than ±350 pS, and the output to output skew is guaranteed to be less than 200 pS. The ASM5P2309A and the ASM5P2305A are available in two different configurations, as shown in the ordering information table. The ASM5P2305A−1 / ASM5P2309A−1 is the base part. The ASM5P2305A−1H / ASM5P2309A−1H is the high drive version of SOIC−8 S SUFFIX CASE 751BD SOIC−16 S SUFFIX CASE 751BG TSSOP−8 T SUFFIX CASE 948AL TSSOP−16 T SUFFIX CASE 948AN the −1 and its rise and fall times are faster than −1 part. PIN CONFIGURATIONS 1 Features • 10 MHz to 133 MHz Operating Range, Compatible with CPU and PCI Bus Frequencies • Zero Input−output Propagation Delay • Multiple Low−skew Outputs ♦ Output−output Skew less than 200 pS ♦ Device−device Skew less than 700 pS ♦ One Input Drives 9 Outputs, Grouped as 4 + 4 + 1 (ASM5P2309A) ♦ One Input Drives 5 Outputs (ASM5P2305A) • Less than 200 pS Cycle−to−Cycle Jitter is Compatible with Pentium® Based Systems • Test Mode to Bypass PLL (ASM5P2309A Only, Refer to Select Input Decoding Table) • Packaging Information: ASM5P2309A: 16−pin SOIC, TSSOP ASM5P2305A: 8−pin SOIC, TSSOP • Commercial and Industrial Temperature Range • 3.3 V Operation REF CLK CLK1 GND REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 ASM5P2305A (Top View) 1 ASM5P2309A (Top View) CLKOUT CLK4 VDD CLK3 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 • Advanced 0.35 � CMOS Technology • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 4 1 Publication Order Number: ASM5P2305A/D

Page 3

ASM5P2305A, ASM5P2309A http://onsemi.com 2 R E F− In pu t t o C LK A / C LK B D el ay (p S ) REF PLL MUX CLKOUT CLKA1 REF PLL ASM5P2305A CLKOUT CLK1 CLK2 CLK3 CLK4 ASM5P2309A S2 Select Input S1 Decoding CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4 Figure 1. Block Diagram Table 1. SELECT INPUT DECODING FOR ASM5P2309A S2 S1 Clock A1 − A4 Clock B1 − B4 CLKOUT (Note 1) Output Source PLL Shut−Down 0 0 Three−state Three−state Driven PLL N 0 1 Driven Three−state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input−output delay. For applications requiring zero input−output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input−output delay. 1500 1000 500 0 −500 −1000 −30 −25 −20 −15 −10 −5 0 5 10 15 20 25 30 −1500 Figure 2. Output Load Difference: CLKOUT Load − CLKA/CLKB Load (pF)

Page 4

ASM5P2305A, ASM5P2309A http://onsemi.com 3 Table 2. PIN DESCRIPTION FOR ASM5P2305A Pin # Pin Name Description 1 REF (Note 2) Input reference clock frequency, 5 V−tolerant input 2 CLK2 (Note 3) Buffered clock output 3 CLK1 (Note 3) Buffered clock output 4 GND Ground 5 CLK3 (Note 3) Buffered clock output 6 VDD 3.3 V supply 7 CLK4 (Note 3) Buffered clock output 8 CLKOUT (Note 3) Buffered clock output, internal feedback on this pin Table 3. PIN DESCRIPTION FOR ASM5P2309A Pin # Pin Name Description 1 REF (Note 2) Input reference clock frequency, 5 V tolerant input 2 CLKA1 (Note 3) Buffered clock output, bank A 3 CLKA2 (Note 3) Buffered clock output, bank A 4 VDD 3.3 V supply 5 GND Ground 6 CLKB1 (Note 3) Buffered clock output, bank B 7 CLKB2 (Note 3) Buffered clock output, bank B 8 S2 (Note 4) Select input, bit 2 9 S1 (Note 4) Select input, bit 1 10 CLKB3 (Note 3) Buffered clock output, bank B 11 CLKB4 (Note 3) Buffered clock output, bank B 12 GND Ground 13 VDD 3.3 V supply 14 CLKA3 (Note 3) Buffered clock output, bank A 15 CLKA4 (Note 3) Buffered clock output, bank A 16 CLKOUT (Note 3) Buffered output, internal feedback on this pin 2. Weak pull−down. 3. Weak pull−down on all outputs. 4. Weak pull−up on these inputs.

Page 5

ASM5P2305A, ASM5P2309A http://onsemi.com 4 Table 4. ABSOLUTE MAXIMUM RATINGS Parameter Min Max Unit Supply Voltage to Ground Potential −0.5 +4.6 V DC Input Voltage (Except REF) −0.5 VDD + 0.5 V DC Input Voltage (REF) −0.5 7 V Storage Temperature −65 +150 °C Max. Soldering Temperature (10 sec) 260 °C Junction Temperature 150 °C Static Discharge Voltage (As per JEDEC STD22− A114−B) 2000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. OPERATING CONDITIONS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H)) Parameter Description Min Max Unit VDD Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) Commercial temperature 0 70 °C Industrial temperature −40 85 CL Load Capacitance, below 100 MHz 30 pF Load Capacitance, from 100 MHz to 133 MHz 10 pF CIN Input Capacitance 7 pF Table 6. ELECTRICAL CHARACTERISTICS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H)) Parameter Description Test Conditions Min Typ Max Unit VIL Input LOW Voltage (Note 5) 0.8 V VIH Input HIGH Voltage (Note 5) 2.2 V IIL Input LOW Current VIN = 0 V 50 �A IIH Input HIGH Current VIN = VDD 100 �A VOL Output LOW Voltage (Note 6) IOL = 8 mA (−1) IOL = 12 mA (−1H) 0.4 V VOH Output HIGH Voltage (Note 6) IOH = −8 mA (−1) IOH = −12 mA (−1H) 2.4 V IDD Supply Current Commercial temp. Unloaded outputs at 66.67 MHz, SEL inputs at VDD 30 mA Industrial temp. 32 5. REF input has a threshold voltage of VDD /2. 6. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Page 6

ASM5P2305A, ASM5P2309A http://onsemi.com 5 Table 7. SWITCHING CHARACTERISTICS (for ASM5P2305A (−1, −1H) and ASM5P2309A (−1, −1H) (Notes 7, 8) Parameter Test Conditions Min Typ Max Unit Output Frequency 30 pF load 10 pF load 10 10 100 133 MHz Duty Cycle (Note 9) Measured at 1.4 V, FOUT > 50 MHz 40 50 60 % Measured at VDD /2, FOUT ≤ 50 MHz 45 50 55 Output Rise Time (Note 9) Measured between 0.8 V and 2.0 V (−1) 2.25 nS (−1H) 1.5 2 Output Fall Time (Note 9) Measured between 2.0 V and 0.8 V (−1) 2.25 nS (−1H) 1.5 2 Output−to−output skew (Note 9) All outputs equally loaded 200 pS Delay, REF Rising Edge to CLKOUT Rising Edge (Note 9) Measured at VDD /2 0 ±350 pS Device−to−Device Skew (Note 9) Measured at VDD/2 on the CLKOUT pins of the device 0 700 pS Cycle−to−cycle Jitter (Note 9) Measured at 66.67 MHz, loaded outputs 200 pS PLL Lock Time (Note 9) Stable power supply, valid clock presented on REF pin 1.0 mS 7. For all measurements use Test Circuit #1. 8. All parameters are specified with loaded outputs. 9. Parameter is guaranteed by design and characterization. Not 100% tested in production. TEST CIRCUIT #1 +3.3 V 0.1 �F VDD ASM5P2305A ASM5P2309A GND 22 Q 22 Q CLK OUT CLOAD CLK A / CLK B CLOAD Figure 3. Test Circuit

Page 7

ASM5P2305A, ASM5P2309A http://onsemi.com 6 Switching Waveforms t1 t2 1.4 V 1.4 V 1.4 V OUTPUT Figure 4. Duty Cycle Timing 2 V 0.8 V 2 V 0.8 V VDD OUTPUT 0 V t3 t4 Figure 5. All Outputs Rise/Fall Time 1.4 V OUTPUT 1.4 V OUTPUT t5 Figure 6. Output−Output Skew VDD/2 INPUT OUTPUT VDD/2 t6 Figure 7. Input−Output Propagation Delay VDD/2 CLKOUT, Device1 CLKOUT, Device2 VDD/2 t7 Figure 8. Device−Device Skew

Page 8

http://onsemi.com 7 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS SYMBOL MIN NOM MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E PIN # 1 IDENTIFICATION TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.

Page 9

http://onsemi.com 8 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS SYMBOL MIN NOM MAX A 1.20 A1 0.05 0.15 A2 0.80 0.90 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 0.60 0.75 θ 0º 8º TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O b E1 E e TOP VIEW D A2 A 81 c A1 L1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.

Page 10

http://onsemi.com 9 ASM5P2305A, ASM5P2309A PACKAGE DIMENSIONS SYMBOL MIN NOM MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º SOIC−16, 150 mils CASE 751BG−01 ISSUE O E1 E PIN#1 IDENTIFICATION TOP VIEW D h A 8 c e b L A1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.

P5P2305AF-1H08SR Reviews

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December 21, 2019

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October 26, 2019

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August 17, 2019

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July 14, 2019

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July 12, 2019

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