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PE43701MLI

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PE43701MLI

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Part Number PE43701MLI
Manufacturer Peregrine Semiconductor
Description IC RF DSA 7BIT 50 OHM 32QFN
Datasheet PE43701MLI Datasheet
Package 32-VFQFN Exposed Pad
In Stock 323 piece(s)
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PE43701MLI Specifications

ManufacturerPeregrine Semiconductor
CategoryRF/IF and RFID - Attenuators
Datasheet PE43701MLIDatasheet
Package32-VFQFN Exposed Pad
SeriesUltraCMOS?, HaRP?
Attenuation Value0dB ~ 31.75dB
Tolerance±0.2dB
Frequency Range9kHz ~ 6GHz
Power (Watts)-
Impedance50 Ohm
Package / Case32-VFQFN Exposed Pad

PE43701MLI Datasheet

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Page 1 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. The PE43701 is a HaRP™-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA covers a 31.75 dB attenuation range in 0.25 dB steps. The Peregrine 50Ω RF DSA provides a parallel or serial- addressable CMOS control interface. It maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change with VDD due to on-board regulator. This next generation Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. The PE43701 is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Product Specification 50 Ω RF Digital Attenuator 7-bit, 31.75 dB, 9 kHz - 4.0 GHz Product Description Figure 2. Functional Schematic Diagram PE43701 Features  HaRP™-enhanced UltraCMOS™ device  Attenuation: 0.25 dB steps to 31.75 dB  High Linearity: Typical +59 dBm IIP3  Excellent low-frequency performance  3.3 V or 5.0 V Power Supply Voltage  Fast switch settling time  Programming Modes:  Direct Parallel  Latched Parallel  Serial-Addressable: Program up to eight addresses 000 - 111  High-attenuation state @ power-up (PUP)  CMOS Compatible  No DC blocking capacitors required  Packaged in a 32-lead 5x5x0.85 mm QFN Figure 1. Package Type 32-lead 5x5x0.85 mm QFN Package Control Logic Interface RF Input RF Output Switched Attenuator Array Serial In LE CLK A0 A1 A2 Parallel Control 7 P/S OB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 2 of 13 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 │ UltraCMOS™ RFIC Solutions -0.25 0.00 0.25 0.50 0 4 8 12 16 20 24 28 32 Attenuation Setting (dB) S te p E rr o r (d B ) 200 MHz 900 MHz 1800 MHz 2200 MHz 3000 MHz Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V Figure 5. 0.25 dB Major State Bit Error Figure 3. 0.25 dB Step Error vs. Frequency* Performance Plots 900 MHz 1800 MHz 2200 MHz 3800 MHz 5 10 15 20 25 300 35 5 10 15 20 25 30 0 35 Attenuation State A tt en ua tio n d B 0.25-dB PE43701 Attenuation Figure 4. 0.25dB Attenuation vs. Attenuation State Parameter Test Conditions Frequency Min Typical Max Units Frequency Range 9 kHz 4.0 GHz Attenuation Range 0.25 dB Step 0 – 31.75 dB Insertion Loss 9 kHz ≤ 4 GHz 1.9 2.4 dB Attenuation Error 0 dB - 7.75 dB Attenuation settings 8 dB - 31.75 dB Attenuation settings 0 dB - 31.75 dB Attenuation settings 9 kHz < 3 GHz 9 kHz < 3 GHz 3 GHz ≤ 4 GHz ±(0.2+1.5%) ±(0.15+4%) ±(0.25+4.5%) dB dB dB Return Loss 9 kHz - 4 GHz 18 dB Relative Phase All States 9 kHz - 4 GHz 44 deg P1dB (note 1) Input 20 MHz - 4 GHz 30 32 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 59 dBm Typical Spurious Value 1MHz -110 dBm Video Feed Through 10 mVpp Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns Settling Time RF settled to within 0.05 dB of final value RBW = 5 MHz, Averaging ON. 4 25 µs *Monotonicity is held so long as Step-Error does not cross below -0.25 Figure 6. 0.25 dB Attenuation Error vs. Frequency Note 1. Please note Maximum Operating Pin (50Ω) of +23dBm as shown in Table 3. -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0 1000 2000 3000 4000 Frequency (MHz) A tte n u a tio n E rr o r (d B ) 0.25dB State 0.5dB State 1dB State 2dB State 4dB State 8dB State 16dB State 31.75dB State -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) A tte n u a tio n E rr o r (d B ) 200 MHz 900 MHz 1800 MHz 2200 MHZ 3000 MHz 4000 MHzO SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 3 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. -70 -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6 7 8 9 Frequency (GHz) R e tu rn L o s s ( d B ) 0dB 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -40 -35 -30 -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 8 9Frequency (GHz) R e tu rn L o s s (d B ) -40C 25C 85C Figure 9. Output Return Loss vs. Attenuation: T = +25C Figure 7. Insertion Loss vs. Temperature Figure 8. Input Return Loss vs. Attenuation: T = +25C Figure 10. Input Return Loss vs. Temperature: 16dB State Figure 11. Output Return Loss vs. Temperature: 16dB State Figure 12. Relative Phase vs. Frequency -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 Frequency (GHz) In se rt io n L o ss ( d B m ) -40C +25C +85C -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 5 6 7 8 9 Frequency (GHz) R e tu rn L o s s ( d B ) 0dB 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0 1 2 3 4 5 6 7 8 9Frequency (GHz) R e tu rn L o s s (d B ) -40C 25C 85C 0 20 40 60 80 100 120 0 1 2 3 4 5 6 7 8 Frequency (GHz) R e la ti v e P h a s e E rr o r (D e g ) 0dB 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dBOB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 4 of 13 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 │ UltraCMOS™ RFIC Solutions 30 35 40 45 50 55 60 65 70 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Frequency (MHz) In p u t IP 3 ( d B m ) 0dB 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) A tte n u a tio n E rr o r (d B ) +25 C -40 C +85 C -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) A tte nu at io n E rr or ( dB ) +25 C -40 C +85 C 0 5 10 15 20 25 30 35 -40 -20 0 20 40 60 80 Temperature (Deg. C) P ha se ( de g) 900 MHz 1800 MHz 3000 MHz Figure 15. Attenuation Error vs. Attenuation Setting: 1800 MHz Figure 13. Relative Phase vs. Temperature: 31.75dB State Figure 14. Attenuation Error vs. Attenuation Figure 16. Attenuation Error vs. Attenuation Setting: 3000 MHz Figure 17. Input IP3 vs. Frequency -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 4.0 8.0 12.0 16.0 20.0 24.0 28.0 32.0 Attenuation Setting (dB) A tte n u at io n E rr or ( dB ) +25 C -40 C +85 C O SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 5 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 161514131211109 Exposed Solder pad NC VDD P/S A0 GND GND RF1 GND G N D G N D G N D G N D G N D G N D G N D G N D CLK LE A1 A2 GND GND RF2 GND C 0. 25 C 0. 5 C 1 C 2 C 4 C 8 C 16 S I Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD- sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating. Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Figure 18. Pin Configuration (Top View) Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Switching Frequency The PE43701 has a maximum 25 kHz switching rate. Switching rate is defined to be the speed at which the DSA can be toggled across attenuation states. Pin No. Pin Name Description 1 N/C No Connect 2 VDD Power supply pin 3 P/S Serial/Parallel mode select 4 A0 Address Bit A0 connection 5, 6, 8-17, 19, 20 GND Ground 7 RF1 RF1 port 18 RF2 RF2 port 21 A2 Address Bit A2 connection 22 A1 Address Bit A1 connection 23 LE Serial interface Latch Enable input 24 CLK Serial interface Clock input 25 SI Serial interface Data input 26 C16 (D6) Parallel control bit, 16 dB 27 C8 (D5) Parallel control bit, 8 dB 28 C4 (D4) Parallel control bit, 4 dB 29 C2 (D3) Parallel control bit, 2 dB 30 C1 (D2) Parallel control bit, 1 dB 31 C0.5 (D1) Parallel control bit, 0.5 dB 32 C0.25 (D0) Parallel control bit, 0.25 dB Paddle GND Ground for proper operation Table 2. Pin Descriptions Moisture Sensitivity Level The Moisture Sensitivity Level rating for the PE43701 in the 5x5 QFN package is MSL1. Note: Ground C0.25, C0.5, C1, C2, C4, C8, C16 if not in use. OB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 6 of 13 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 │ UltraCMOS™ RFIC Solutions 0.0 5.0 10.0 15.0 20.0 25.0 30.0 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08 1.0E+09 Hz P in d B m Table 3. Operating Ranges Table 4. Absolute Maximum Ratings Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Symbol Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 6.0 V VI Voltage on any Digital input -0.3 5.8 V TST Storage temperature range -65 150 °C VESD ESD voltage (HBM)1 ESD voltage (Machine Model) 500 100 V V PIN Input power (50Ω) 9 kHz ≤ 20 MHz 20 MHz ≤ 4 GHz See fig. 19 +23 dBm dBm Parameter Min Typ Max Units VDD Power Supply Voltage 3.0 3.3 V IDD Power Supply Current 70 350 μA Digital Input High 2.6 5.5 V PIN Input power (50Ω): 9 kHz ≤ 20 MHz 20 MHz ≤ 4 GHz See fig. 19 +23 dBm dBm TOP Operating temperature range -40 25 85 °C Digital Input Low 0 1 V Digital Input Leakage1 15 μA VDD Power Supply Voltage 5.0 5.5 V Note 1. Input leakage current per Control pin Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7) Figure 19. Maximum Power Handling Capability: Z0 = 50 Ω OB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 7 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Table 6. Latch and Clock Specifications Table 5. Control Voltage State Bias Condition Low 0 to +1.0 Vdc at 2 µA (typ) High +2.6 to +5 Vdc at 10 µA (typ) Table 7. Parallel Truth Table Table 10. Serial-Addressable Register Map Latch Enable Function 0 Shift Register Clocked ↑ Contents of shift register transferred to attenuator core Shift Clock ↑ X Parallel Control Setting Attenuation Setting RF1-RF2 D6 D5 D4 D3 D2 D1 D0 L L L L L L L Reference I.L. L L L L L L H 0.25 dB L L L L L H L 0.5 dB L L L L H L L 1 dB L L L H L L L 2 dB L L H L L L L 4 dB L H L L L L L 8 dB H L L L L L L 16 dB H H H H H H H 31.75 dB Address Word Address Setting A7 (MSB) A6 A5 A4 A3 A2 A1 A0 X X X X X L L L 000 X X X X X L L H 001 X X X X X L H L 010 X X X X X L H H 011 X X X X X H L L 100 X X X X X H L H 101 X X X X X H H L 110 X X X X X H H H 111 Table 8. Address Word Truth Table Attenuation Word D7 D6 D5 D4 D3 D2 D1 D0 (LSB) L L L L L L L L Reference I.L. L L L L L L L H 0.25 dB L L L L L H L L 1 dB L L L L H L L L 2 dB L L L H L L L L 4 dB L L H L L L L L 8 dB L H L L L L L L 16 dB L H H H H H H H 31.75 dB Attenuation Setting RF1-RF2 L L L L L L H L 0.5 dB Table 9. Attenuation Word Truth Table Q15 Q14 Q13 Q12 Q11 Q10 A7 A6 A5 A4 A3 A2 Q9 Q8 Q7 Q6 Q5 Q4 A1 A0 D7 D6 D5 D4 Q3 Q2 Q1 Q0 D3 D2 D1 D0 Address Word Attenuation Word LSB (first in) MSB (last in) Bits can either be set to logic high or logic low Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state at address 3: Address word: XXXXX011 Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001 Serial Input: XXXXX01101001001 D7 must be set to logic low OB SO ET E RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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Product Specification PE43701 Page 8 of 13 ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0243-06 │ UltraCMOS™ RFIC Solutions Programming Options Parallel/Serial-Addressable Selection Either a parallel or serial-addressable interface can be used to control the PE43701. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial- addressable interface. Parallel Mode Interface The parallel interface consists of seven CMOS- compatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 21 (Parallel Interface Timing Diagram), Table 12 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 21) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial-addressable interface is a 16-bit serial-in, parallel-out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8-bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 20 illustrates an example timing diagram for programming a state. It is required that all parallel control inputs be grounded when the DSA is used in serial- addressable Mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the Attenuation Word. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the serial-addressable register is illustrated in Table 10. The serial-addressable timing diagram is illustrated in Fig. 20. Power-up Control Settings The PE43701 will always initialize to the maximum attenuation setting (31.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct- parallel mode, the DSA can be preset to any state within the 31.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (31.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state). Dynamic operation between serial-addressable and parallel programming modes is possible. If the DSA powers up in serial-addressable mode (P/ S = HIGH), all the parallel control inputs DI[6:0] must be set to logic low. Prior to toggling to parallel mode, the DSA must be programmed serially to ensure D[7] is set to logic low. If the DSA powers up in either latched or direct- parallel mode, all parallel pins DI[6:0] must be set to logic low prior to toggling to serial-addressable mode (P/S = HIGH), and held low until the DSA has been programmed serially to ensure bit D[7] is set to logic low. The sequencing is only required once on power- up. Once completed, the DSA may be toggled between serial-addressable and parallel programming modes at will. OB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

Page 10

Product Specification PE43701 Page 9 of 13 Document No. 70-0243-06 │ www.psemi.com ©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Table 12. Parallel and Direct Interface AC Characteristics Table 11. Serial-Addressable Interface AC Characteristics VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified VDD = 3.3 or 5.0 V, -40° C < TA < 85° C, unless otherwise specified Figure 20. Serial-Addressable Timing Diagram Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram Symbol Parameter Min Max Unit FCLK Serial clock frequency - 10 MHz TCLKH Serial clock HIGH time 30 - ns TCLKL Serial clock LOW time 30 - ns TLESU Last serial clock rising edge setup time to Latch Enable rising edge 10 - ns TLEPW Latch Enable min. pulse width 30 - ns TSISU Serial data setup time 10 - ns TSIH Serial data hold time 10 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TASU Address setup time 100 - ns TAH Address hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns Symbol Parameter Min Max Unit TLEPW Latch Enable minimum pulse width 30 - ns TDISU Parallel data setup time 100 - ns TDIH Parallel data hold time 100 - ns TPSSU Parallel/Serial setup time 100 - ns TPSIH Parallel/Serial hold time 100 - ns TPD Digital register delay (internal) - 10 ns TDIPD Digital register delay (internal, direct mode only) - 5 ns VALID TDISU TDIH DI[6:0] LE P/S TPSSU TPSH TLEPW VALIDDO[6:0] TDIPD TPD A[2]A[1]A[0] TSISU TCLKL TLEPW TSIH TCLKH SI CLK LE P/S TLESU TPSSU TPSIH VALID TASU ADD[2:0] TAIH DO[6:0] VALID DI[6:0] TPD TDISU TDIH D[6]D[5]D[4]D[3]D[2]D[1]D[0] D[7] D[7] must be set to logic low Bits can either be set to logic high or logic low OB SO LE TE RE PL AC E W ITH P E4 37 12 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com

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