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S25FL132K0XNFB010

S25FL132K0XNFB010

S25FL132K0XNFB010

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Part Number S25FL132K0XNFB010
Manufacturer Cypress Semiconductor Corp
Description IC FLASH 32M SPI 108MHZ 8WSON
Datasheet S25FL132K0XNFB010 Datasheet
Package 8-WDFN Exposed Pad
In Stock 2,934 piece(s)
Unit Price $ 3.0400 *
Lead Time To be Confirmed
Estimated Delivery Time Dec 6 - Dec 11 (Choose Expedited Shipping)
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Part Number # S25FL132K0XNFB010 (Memory) is manufactured by Cypress Semiconductor Corp and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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S25FL132K0XNFB010 Specifications

ManufacturerCypress Semiconductor Corp
CategoryIntegrated Circuits (ICs) - Memory
Datasheet S25FL132K0XNFB010Datasheet
Package8-WDFN Exposed Pad
SeriesAutomotive, AEC-Q100, FL1-K
Memory TypeNon-Volatile
Memory FormatFLASH
TechnologyFLASH - NOR
Memory Size32Mb (4M x 8)
Memory InterfaceSPI - Quad I/O
Clock Frequency108MHz
Write Cycle Time - Word, Page3ms
Access Time-
Voltage - Supply2.7 V ~ 3.6 V
Operating Temperature-40°C ~ 105°C (TA)
Mounting TypeSurface Mount
Package / Case8-WDFN Exposed Pad
Supplier Device Package8-WSON (6x8)

S25FL132K0XNFB010 Datasheet

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S25FL116K/S25FL132K/S25FL164K 16-Mbit (2 Mbyte)/32-Mbit (4 Mbyte)/ 64-Mbit (8 Mbyte), 3.0 V, SPI Flash Memory Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 002-00497 Rev. *H Revised May 19, 2017 This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede the S25FL1-K family. These are the factory-recommended migration paths. Please refer to the S25FL-L Family datasheets for specifications and ordering information. Features  Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Command subset and footprint compatible with S25FL-K  Read – Normal Read (Serial): – 50 MHz clock rate (40 °C to +85 °C/105 °C) – Fast Read (Serial): – 108 MHz clock rate (40 °C to +85 °C/105 °C) – Dual Read: – 108 MHz clock rate (40 °C to +85 °C/105 °C) – Quad Read: – 108 MHz clock rate (40 °C to +85 °C/105 °C) – 54 MB/s maximum continuous data transfer rate (40 °C to +85 °C/105 °C) – Efficient Execute-In-Place (XIP) – Continuous and wrapped read modes – Serial Flash Discoverable Parameters (SFDP)  Program – Serial-input Page Program (up to 256 bytes) – Program Suspend and Resume  Erase – Uniform sector erase (4 kB) – Uniform block erase (64 kB) – Chip erase – Erase Suspend and Resume  Cycling Endurance – 100K Program-Erase cycles, minimum  Data Retention – 20-year data retention, minimum  Security – Three 256-byte Security Registers with OTP protection – Low supply voltage protection of the entire memory – Pointer-based security protection feature (S25FL132K and S25FL164K) – Top / Bottom relative Block Protection Range, 4 kB to all of memory – 8-Byte Unique ID for each device – Non-volatile Status Register bits control protection modes – Software command protection – Hardware input signal protection – Lock-Down until power cycle protection – OTP protection of security registers  90 nm Floating Gate Technology  Single Supply Voltage – 2.7 V to 3.6 V (Industrial, Industrial Plus, and Extended temperature range) – 2.6 V to 3.6 V (Extended temperature range)  Temperature Ranges – Industrial (40 °C to +85 °C) – Industrial Plus (40 °C to +105 °C) – Automotive, AEC-Q100 Grade 3 (–40°C to +85°C) – Automotive, AEC-Q100 Grade 2 (–40°C to +105°C))  Package Options – S25FL116K – 8-lead SOIC (150 mil) – SOA008 – 8-lead SOIC (208 mil) – SOC008 – 8-contact WSON 5 mm x 6 mm – WND008 – 24-ball BGA 6 mm  8 mm – FAB024 and FAC024 – KGD / KGW – S25FL132K – 8-lead SOIC (150 mil) – SOA008 – 8-lead SOIC (208 mil) – SOC008 – 8-contact USON 4 mm  4 mm – UNF008 – 8-contact WSON 5 mm  6 mm – WND008 – 24-ball BGA 6 mm  8 mm – FAB024 and FAC024 – KGD / KGW – S25FL164K – 8-lead SOIC (208 mil) – SOC008 – 16-lead SOIC (300 mil) – SO3016 – 8-contact WSON 5 mm  6 mm – WND008 – 24-ball BGA 6 mm  8 mm – FAB024 and FAC024 No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 2 of 90 S25FL116K/S25FL132K/S25FL164K Logic Block Diagram Performance Summary Maximum Read Rates (VCC = 2.7 V to 3.6 V, 85 °C/105 °C) Command Clock Rate (MHz) Mbytes/s Read 50 6.25 Fast Read 108 13.5 Dual Read 108 27 Quad Read 108 54 Typical Program and Erase Rates (VCC = 2.7 V to 3.6 V, 85 °C/105 °C) Operation kbytes/s Page Programming (256-byte page buffer) 365 4-kbyte Sector Erase 81 64-kbyte Sector Erase 131 Typical Current Consumption (VCC = 2.7 V to 3.6 V, 85 °C/105 °C) Operation Current (mA) Serial Read 50 MHz 7 Serial Read 108 MHz 12 Dual Read 108 MHz 14 Quad Read 108 MHz 16 Program 20 Erase 20 Standby 0.015 Deep-Power Down 0.002 Memory Control Logic Data Path X D ec o de rs CS# SCK SI/IO0 SO/IO1 HOLD#/IO3 WP#/IO2 I/O Y Decoders Data Latch No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 3 of 90 S25FL116K/S25FL132K/S25FL164K Contents 1. General Description..................................................... 4 1.1 Migration Notes.............................................................. 5 1.2 Glossary......................................................................... 6 1.3 Other Resources............................................................ 7 2. Signal Descriptions ..................................................... 8 2.1 Input / Output Summary................................................. 8 2.2 Address and Data Configuration.................................... 9 2.3 Serial Clock (SCK) ......................................................... 9 2.4 Chip Select (CS#) .......................................................... 9 2.5 Serial Input (SI) / IO0 ..................................................... 9 2.6 Serial Output (SO) / IO1................................................. 9 2.7 Write Protect (WP#) / IO2 .............................................. 9 2.8 HOLD# / IO3 ................................................................ 10 2.9 Core and I/O Signal Voltage Supply (VCC) .................. 10 2.10 Supply and Signal Ground (VSS) ................................. 10 2.11 Not Connected (NC) .................................................... 10 2.12 Reserved for Future Use (RFU)................................... 10 2.13 Do Not Use (DNU) ....................................................... 11 2.14 Block Diagrams............................................................ 11 3. Signal Protocols......................................................... 12 3.1 SPI Clock Modes ......................................................... 12 3.2 Command Protocol ...................................................... 12 3.3 Interface States............................................................ 16 3.4 Status Register Effects on the Interface ...................... 19 3.5 Data Protection ............................................................ 19 4. Electrical Characteristics .......................................... 20 4.1 Absolute Maximum Ratings ......................................... 20 4.2 Thermal Resistance ..................................................... 21 4.3 Operating Ranges........................................................ 21 4.4 DC Electrical Characteristics ....................................... 22 4.5 AC Measurement Conditions ....................................... 23 4.6 Power-Up Timing ......................................................... 24 4.7 Power-On (Cold) Reset................................................ 25 4.8 AC Electrical Characteristics........................................ 25 5. Physical Interface ...................................................... 29 5.1 Connection Diagrams .................................................. 29 5.2 Physical Diagrams ........................................................ 31 6. Address Space Maps.................................................. 38 6.1 Overview....................................................................... 38 6.2 Flash Memory Array...................................................... 38 6.3 Security Registers......................................................... 39 6.4 Security Register 0 — Serial Flash Discoverable Parameters (SFDP — JEDEC JESD216B) ...................................... 39 6.5 Status Registers ........................................................... 49 6.6 Device Identification...................................................... 59 7. Functional Description ............................................... 60 7.1 SPI Operations ............................................................. 60 7.2 Write Protection ............................................................ 61 7.3 Status Registers ........................................................... 61 8. Commands .................................................................. 62 8.1 Configuration and Status Commands........................... 64 8.2 Program and Erase Commands ................................... 67 8.3 Read Commands.......................................................... 70 8.4 Reset Commands ......................................................... 75 8.5 ID and Security Commands.......................................... 77 8.6 Set Block / Pointer Protection (39h) — S25FL132K and S25FL164K ................................... 81 9. Data Integrity ............................................................... 83 9.1 Erase Endurance .......................................................... 83 9.2 Data Retention.............................................................. 83 9.3 Initial Delivery State ...................................................... 83 10. Ordering Information .................................................. 84 11. Revision History.......................................................... 87 Document History Page 87 Sales, Solutions, and Legal Information .......................... 90 Worldwide Sales and Design Support ...........................90 Products ........................................................................90 PSoC® Solutions ..........................................................90 Cypress Developer Community .....................................90 Technical Support .........................................................90No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 4 of 90 S25FL116K/S25FL132K/S25FL164K 1. General Description The S25FL1-K of non-volatile flash memory devices connect to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (Quad I/O or QIO) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO. The SPI-MIO protocols use only 4 to 6 signals:  Chip Select (CS#)  Serial Clock (SCK) – IO0 (SI) – IO1 (SO) – IO2 (WP#) – IO3 (HOLD#)  Serial Data The SIO protocol uses Serial Input (SI) and Serial Output (SO) for data transfer. The DIO protocols use IO0 and IO1 to input or output two bits of data in each clock cycle. The Write Protect (WP#) input signal option allows hardware control over data protection. Software controlled commands can also manage data protection. The HOLD# input signal option allows commands to be suspended and resumed on any clock cycle. The QIO protocols use all of the data signals (IO0 to IO3) to transfer 4 bits in each clock cycle. When the QIO protocols are enabled the WP# and HOLD# inputs and features are disabled. Clock frequency of up to 108 MHz is supported, allowing data transfer rates up to:  Single bit data path = 13.5 Mbytes/s  Dual bit data path = 27 Mbytes/s  Quad bit data path = 54 Mbytes/s Executing code directly from flash memory is often called execute-In-Place or XIP. By using S25FL1-K devices at the higher clock rates supported, with QIO commands, the command read transfer rate can match or exceed traditional x8 or x16 parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically. The Continuous Read Mode allows for random memory access with as few as 8-clocks of overhead for each access, providing efficient XIP operation. The Wrapped Read mode provides efficient instruction or data cache refill via a fast read of the critical byte that causes a cache miss, followed by reading all other bytes in the same cache line in a single read command. The S25FL1-K:  Support JEDEC standard manufacturer and device type identification.  Program pages of 256 bytes each. One to 256 bytes can be programmed in each Page Program operation. Pages can be erased in groups of 16 (4-kB aligned sector erase), groups of 256 (64-kB aligned block erase), or the entire chip (chip erase).  The S25FL1-K devices operate on a single 2.6V/2.7V to 3.6V power supply and all devices are offered in space-saving packages.  Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data. No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 5 of 90 S25FL116K/S25FL132K/S25FL164K 1.1 Migration Notes 1.1.1 Features Comparison The S25FL1-K is command set and footprint compatible with prior generation FL-K and FL-P families. Notes: 1. S25FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB. 2. S25FL1-K family devices can erase 4-kB sectors in groups of 64 kB. 3. S25FL-P has either 64-kB or 256-kB uniform sectors depending on an ordering option. 4. Refer to individual data sheets for further details. 1.1.2 Known Feature Differences from Prior Generations 1.1.2.1 Secure Silicon Region (OTP) The size and format (address map) of the One Time Program area is the same for the S25FL1-K and the S25FL-K but different for the S25FL-P. Table 1. FL Generations Comparison Parameter S25FL1-K S25FL-K S25FL-P Technology Node 90 nm 90 nm 90 nm Architecture Floating Gate Floating Gate MirrorBit® Release Date In Production In Production In Production Density 16 Mbit - 64 Mbit 4 Mbit - 128 Mbit 32 Mbit - 256 Mbit Bus Width x1, x2, x4 x1, x2, x4 x1, x2, x4 Supply Voltage 2.6V / 2.7V - 3.6V 2.7V - 3.6V 2.7V - 3.6V Normal Read Speed 6 MB/s (50 MHz) 6 MB/s (50 MHz) 5 MB/s (40 MHz) Fast Read Speed 13.5 MB/s (108 MHz) 13 MB/s (104 MHz) 13 MB/s (104 MHz) Dual Read Speed 27 MB/s (108 MHz) 26 MB/s (104 MHz) 20 MB/s (80 MHz) Quad Read Speed 54 MB/s (108 MHz at 85°C/105°C) 52 MB/s (104 MHz) 40 MB/s (80 MHz) Program Buffer Size 256B 256B 256B Page Programming Time (typ.) 700 µs (256B) 700 µs (256B) 1500 µs (256B) Program Suspend / Resume Yes Yes No Erase Sector Size 4 kB / 64 kB 4 kB / 32 kB / 64 kB 64 kB / 256 kB Parameter Sector Size N/A N/A 4 kB Sector Erase Time (typ.) 50 ms (4 kB), 500 ms (64 kB) 30 ms (4 kB), 150 ms (64 kB) 500 ms (64 kB) Erase Suspend / Resume Yes Yes No OTP Size 768B (3 x 256B) 768B (3 x 256B) 506B Operating Temperature -40°C to +85°C / +105°C -40°C to +85°C -40°C to +85°C / +105°C N t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 6 of 90 S25FL116K/S25FL132K/S25FL164K 1.1.2.2 Commands Not Supported The following S25FL-K and S25FL-P commands are not supported:  Quad Page PGM (32h)  Half-Block Erase 32K (52h)  Word read Quad I/O (E7)  Octal Word Read Quad I/O (E3h)  MFID dual I/O (92h)  MFID quad I/O (94h)  Read Unique ID (4Bh) 1.1.2.3 New Features The S25FL1-K introduces new features to low density SPI category memories:  Variable read latency (number of dummy cycles) for faster initial access time or higher clock rate read commands  Industrial Plus and Extended temperature range  Volatile configuration option in addition to legacy non-volatile configuration 1.2 Glossary  Command. All information transferred between the host system and memory during one period while CS# is low. This includes the instruction (sometimes called an operation code or opcode) and any required address, mode bits, latency cycles, or data.  Flash. The name for a type of Electrical Erase Programmable Read Only Memory (EEPROM) that erases large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.  High. A signal voltage level ≥ VIH or a logic level representing a binary one (1).  Instruction. The 8-bit code indicating the function to be performed by a command (sometimes called an operation code or opcode). The instruction is always the first 8 bits transferred from host system to the memory in any command.  Low. A signal voltage level  VIL or a logic level representing a binary zero (0).  LSB. Least Significant Bit. Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value.  MSB. Most Significant Bit. Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value.  Non-Volatile. No power is needed to maintain data stored in the memory.  OPN. Ordering Part Number. The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device.  Page. 256-byte aligned and length group of data.  PCB. Printed Circuit Board.  Register Bit References. Are in the format: Register_name[bit_number] or Register_name[bit_range_MSB: bit_range_LSB].  Sector. Erase unit size; all sectors are physically 4-kbytes aligned and length. Depending on the erase command used, groups of physical sectors may be erased as a larger logical sector of 64 kbytes.  Write. An operation that changes data within volatile or non-volatile registers bits or non-volatile flash memory. When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified – as a single operation. The non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data. No t R ec om me de d f or Ne w De sig n

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Document Number: 002-00497 Rev. *H Page 7 of 90 S25FL116K/S25FL132K/S25FL164K 1.3 Other Resources 1.3.1 Cypress Flash Memory Roadmap www.cypress.com/product-roadmaps/cypress-flash-memory-roadmap 1.3.2 Links to Software www.cypress.com/software-and-drivers-cypress-flash-memory 1.3.3 Links to Application Notes www.cypress.com/cypressappnotes No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 8 of 90 S25FL116K/S25FL132K/S25FL164K Hardware Interface Serial Peripheral Interface with Multiple Input / Output (SPI-MIO) Many memory devices connect to their host system with separate parallel control, address, and data signals that require a large number of signal connections and larger package size. The large number of connections increase power consumption due to so many signals switching and the larger package increases cost. The S25FL1-K reduces the number of signals for connection to the host system by serially transferring all control, address, and data information over 4 to 6 signals. This reduces the cost of the memory package, reduces signal switching power, and either reduces the host connection count or frees host connectors for use in providing other features. The S25FL1-K uses the industry standard single bit Serial Peripheral Interface (SPI) and also supports commands for two bit (Dual) and four bit (Quad) wide serial transfers. This multiple width interface is called SPI Multi-I/O or SPI-MIO. 2. Signal Descriptions 2.1 Input / Output Summary Note: 1. A signal name ending with the # symbol is active when low. Table 2. Signal List Signal Name Type Description SCK Input Serial Clock. CS# Input Chip Select. SI (IO0) I/O Serial Input for single bit data commands. IO0 for Dual or Quad commands. SO (IO1) I/O Serial Output for single bit data commands. IO1 for Dual or Quad commands. WP# (IO2) I/O Write Protect in single bit or Dual data commands. IO2 in Quad mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. HOLD# (IO3) I/O Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad commands. VCC Supply Core and I/O Power Supply. VSS Supply Ground. NC Unused Not Connected. No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC must not have voltage levels higher than VCC. RFU Reserved Reserved for Future Use. No device internal signal is currently connected to the package connector but there is potential future use of the connector for a signal. It is recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced features in compatible footprint devices. DNU Reserved Do Not Use. Do not use these connections for PCB signal routing channels. Do not connect any host system signal to this connection. No t R ec om me nd ed fo r N ew D es ign

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Document Number: 002-00497 Rev. *H Page 9 of 90 S25FL116K/S25FL132K/S25FL164K 2.2 Address and Data Configuration Traditional SPI single bit wide commands (Single or SIO) send information from the host to the memory only on the SI signal. Data may be sent back to the host serially on the Serial Output (SO) signal. Dual or Quad Output commands send information from the host to the memory only on the SI signal. Data will be returned to the host as a sequence of bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Dual or Quad Input / Output (I/O) commands send information from the host to the memory as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. Data is returned to the host similarly as bit pairs on IO0 and IO1 or four bit (nibble) groups on IO0, IO1, IO2, and IO3. 2.3 Serial Clock (SCK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCK signal. Data output changes after the falling edge of SCK. 2.4 Chip Select (CS#) The chip select signal indicates when a command for the device is in process and the other signals are relevant for the memory device. When the CS# signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode. Driving the CS# input to logic low state enables the device, placing it in the Active Power mode. After Power-Up, a falling edge on CS# is required prior to the start of any command. 2.5 Serial Input (SI) / IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 - an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 2.6 Serial Output (SO) / IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. SO becomes IO1, an input and output during Dual and Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 2.7 Write Protect (WP#) / IO2 When WP# is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data modification while WP# remains Low. The WP# function is not available when the Quad mode is enabled (QE) in Status Register-2 (SR2[1]=1). The WP# function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not used for Quad mode. No t R ec om me nd ed fo r N ew D es ign

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  • Cypress Semiconductor Corp S25FL132K0XNFB010
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