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S912XEP100W1MAG

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S912XEP100W1MAG

For Reference Only

Part Number S912XEP100W1MAG
Manufacturer NXP
Description IC MCU 16BIT 1MB FLASH 144LQFP
Datasheet S912XEP100W1MAG Datasheet
Package 144-LQFP
In Stock 231 piece(s)
Unit Price $ 17.5922 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 4 - Dec 9 (Choose Expedited Shipping)
Request for Quotation

Part Number # S912XEP100W1MAG (Embedded - Microcontrollers) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

For S912XEP100W1MAG specifications/configurations, quotation, lead time, payment terms of further enquiries please have no hesitation to contact us. To process your RFQ, please add S912XEP100W1MAG with quantity into BOM. Heisener.com does NOT require any registration to request a quote of S912XEP100W1MAG.

S912XEP100W1MAG Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet S912XEP100W1MAGDatasheet
Package144-LQFP
SeriesHCS12X
Core ProcessorHCS12X
Core Size16-Bit
Speed50MHz
ConnectivityCAN, EBI/EMI, I2C, IrDA, SCI, SPI
PeripheralsLVD, POR, PWM, WDT
Number of I/O119
Program Memory Size1MB (1M x 8)
Program Memory TypeFLASH
EEPROM Size4K x 8
RAM Size64K x 8
Voltage - Supply (Vcc/Vdd)1.72 V ~ 5.5 V
Data ConvertersA/D 24x12b
Oscillator TypeExternal
Operating Temperature-40°C ~ 125°C (TA)
Mounting Type-
Package / Case144-LQFP
Supplier Device Package144-LQFP (20x20)

S912XEP100W1MAG Datasheet

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HCS12X Microcontrollers freescale.com MC9S12XEP100 Reference Manual Covers MC9S12XE Family MC9S12XEP100RMV1 Rev. 1.25 02/2013

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To provide the most up-to-date information, the document revision on the World Wide Web is the most current. A printed copy may be an earlier revision. To verif, refer to: freescale.com This document contains information for the complete S12XE-Family and thus includes a set of separate FTM module sections to cover the whole family. A full list of family members and options is included in the appendices. This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual. Revision History. Refer to module section revision history tables for more information. Date Revision Description Sep, 2008 1.18 Updated NVM timing parameter section for brownout case Specified time delay from RESET to start of CPU code execution Added NVM patch Part IDs Enhanced ECT GPIO / timer function transitioning description Dec, 2008 1.19 Updated 208MAPBGA thermal parameters Revised TIM flag clearing procedure Corrected CRG register address Added maskset identifier suffix for ATMC fab Fixed typos Aug, 2009 1.20 Added 208MAPBGA disclaimer Added VREAPI to PT5. Added LVR Note to electricals. Updates to TIM/ECT/XGATE/SCI/MSCAN (see embedded rev. history) Apr, 2010 1.21 FTM section (see FTM revision history) PIM section (see PIM revision history) May, 2010 1.22 ECT and TIM sections (see ECT, TIM revision history tables) BDM Alternate clock source defined in device overview Sep, 2010 1.23 Added S12XEG256 option. Updated MSCAN section Aug, 2012 1.24 Added bandgap voltage to electricals Added new maskset and Part ID numbers Minor updates to MSCAN,SCI and S12XINT sections Removed BGA disclaimer Feb, 2013 1.25 Updated MSCAN section Formatting updates and minor corrections in PWM, CRG, BDM, DBG sections Updated Ordering Information

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Chapter 1 Device Overview MC9S12XE-Family. . . . . . . . . . . . . . . . . . . . .27 Chapter 2 Port Integration Module (S12XEP100PIMV1) . . . . . . . . . . . . . .89 Chapter 3 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . .187 Chapter 4 Memory Protection Unit (S12XMPUV1) . . . . . . . . . . . . . . . . .227 Chapter 5 External Bus Interface (S12XEBIV4) . . . . . . . . . . . . . . . . . . . .241 Chapter 6 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 Chapter 7 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . .279 Chapter 8 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . .305 Chapter 9 Security (S12XE9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 Chapter 10 XGATE (S12XGATEV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) . . . . . .469 Chapter 12 Pierce Oscillator (S12XOSCLCPV2) . . . . . . . . . . . . . . . . . . . .499 Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . .503 Chapter 14 Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . .527 Chapter 15 Inter-Integrated Circuit (IICV3) Block Description. . . . . . . . .579 Chapter 16 Scalable Controller Area Network (S12MSCANV3) . . . . . . . .605 Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2) . . . . . . . . . . . . . .659 Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2) . . . . . . . . . . . . . .677 Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . .691 Chapter 20 Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . .723 Chapter 21 Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . .761 Chapter 22 Timer Module (TIM16B8CV2) Block Description . . . . . . . . . .787 Chapter 23 Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . .815 Chapter 24 128 KByte Flash Module (S12XFTM128K2V1) . . . . . . . . . . . .832 Chapter 25 256 KByte Flash Module (S12XFTM256K2V1) . . . . . . . . . . . .891MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor 3

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Chapter 26 384 KByte Flash Module (S12XFTM384K2V1) . . . . . . . . . . . .953 Chapter 27 512 KByte Flash Module (S12XFTM512K3V1) . . . . . . . . . . .1016 Chapter 28 768 KByte Flash Module (S12XFTM768K4V2) . . . . . . . . . . .1077 Chapter 29 1024 KByte Flash Module (S12XFTM1024K5V2) . . . . . . . . .1140 Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .1201 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1258 Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1260 Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1268 Appendix E Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . .1271 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1322MC9S12XE-Family Reference Manual Rev. 1.25 4 Freescale Semiconductor

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Chapter 1 Device Overview MC9S12XE-Family 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.1.5 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.2.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.4.4 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 1.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1.7 ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.7.1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.7.2 ADC0 Channel[17] Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.8 ADC1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 1.9 MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.10 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.10.1 Temperature Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.11 BDM Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.12 S12XEPIM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 1.13 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Chapter 2 Port Integration Module (S12XEPIMV1) 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89MC9S12XE-Family Reference Manual Rev. 1.25 Freescale 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2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 2.3.7 Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 2.3.8 Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.3.9 Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.3.10 Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 2.3.11 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.3.12 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 2.3.13 S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . 114 2.3.14 S12X_EBI ports Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.3.15 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 2.3.16 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 2.3.17 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.3.18 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 2.3.19 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.3.20 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 2.3.21 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 2.3.22 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.3.23 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 2.3.24 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.3.25 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 2.3.26 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 2.3.27 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 2.3.28 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 2.3.29 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 2.3.30 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.3.31 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 2.3.32 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 2.3.33 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.3.34 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 2.3.35 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 2.3.36 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 2.3.37 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2.3.38 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 2.3.39 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 2.3.40 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 2.3.41 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134MC9S12XE-Family Reference Manual Rev. 1.25 8 Freescale Semiconductor

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2.3.42 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 2.3.43 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 2.3.44 Module Routing Register (MODRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 2.3.45 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 2.3.46 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 2.3.47 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 2.3.48 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 2.3.49 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 2.3.50 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 2.3.51 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 2.3.52 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 2.3.53 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 2.3.54 Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 2.3.55 Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 2.3.56 Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 2.3.57 Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.3.58 Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 2.3.59 Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 2.3.60 Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 2.3.61 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 2.3.62 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.3.63 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 2.3.64 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2.3.65 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 2.3.66 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 2.3.67 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.3.68 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 2.3.69 Port AD0 Data Register 0 (PT0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 2.3.70 Port AD0 Data Register 1 (PT1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 2.3.71 Port AD0 Data Direction Register 0 (DDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 2.3.72 Port AD0 Data Direction Register 1 (DDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 2.3.73 Port AD0 Reduced Drive Register 0 (RDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 2.3.74 Port AD0 Reduced Drive Register 1 (RDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 2.3.75 Port AD0 Pull Up Enable Register 0 (PER0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 2.3.76 Port AD0 Pull Up Enable Register 1 (PER1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2.3.77 Port AD1 Data Register 0 (PT0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 2.3.78 Port AD1 Data Register 1 (PT1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2.3.79 Port AD1 Data Direction Register 0 (DDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 2.3.80 Port AD1 Data Direction Register 1 (DDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 2.3.81 Port AD1 Reduced Drive Register 0 (RDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 2.3.82 Port AD1 Reduced Drive Register 1 (RDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 2.3.83 Port AD1 Pull Up Enable Register 0 (PER0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.84 Port AD1 Pull Up Enable Register 1 (PER1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 2.3.85 Port R Data Register (PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 2.3.86 Port R Input Register (PTIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164MC9S12XE-Family Reference Manual Rev. 1.25 Freescale Semiconductor 9

S912XEP100W1MAG Reviews

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Ange***** Weiss

November 18, 2020

Very Quick,no problems - Thank you.

Beth*****Jain

November 17, 2020

High level customer service, and quick response.

Jayd*****hmidt

November 14, 2020

Well packaged and good condition with the parts, arrived on time, good customer service.

Alis*****tuart

November 5, 2020

Received the parts, and all parts are in tight packaging without any problems, professional seller.

Alis*****ntura

October 29, 2020

Item works as described, fast delivery, nice contact!

Lis*****arson

October 29, 2020

They are great as I need, I give 5 stars.

Terr*****Curtis

October 24, 2020

very pleased with item, thank you.

Ary*****Mora

October 19, 2020

I am satisfied with Heisener company

S912XEP100W1MAG Guarantees

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We provide 90 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.

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