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SI1403CDL-T1-GE3

hot SI1403CDL-T1-GE3

SI1403CDL-T1-GE3

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Part Number SI1403CDL-T1-GE3
Manufacturer Vishay Siliconix
Description MOSFET P-CH 20V 2.1A SC-70-6
Datasheet SI1403CDL-T1-GE3 Datasheet
Package 6-TSSOP, SC-88, SOT-363
In Stock 72402 piece(s)
Unit Price $ 0.118 *
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SI1403CDL-T1-GE3 Specifications

ManufacturerVishay Siliconix
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet SI1403CDL-T1-GE3 Datasheet
Package6-TSSOP, SC-88, SOT-363
SeriesTrenchFET?
FET TypeP-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)20V
Current - Continuous Drain (Id) @ 25��C2.1A (Tc)
Drive Voltage (Max Rds On, Min Rds On)2.5V, 4.5V
Vgs(th) (Max) @ Id1.5V @ 250µA
Gate Charge (Qg) (Max) @ Vgs8nC @ 4.5V
Input Capacitance (Ciss) (Max) @ Vds281pF @ 10V
Vgs (Max)��12V
Power Dissipation (Max)600mW (Ta), 900mW (Tc)
Rds On (Max) @ Id, Vgs140 mOhm @ 1.6A, 4.5V
Operating Temperature-55°C ~ 150°C (TJ)
Mounting TypeSurface Mount
Supplier Device PackageSC-70-6 (SOT-363)
Package / Case6-TSSOP, SC-88, SOT-363

SI1403CDL-T1-GE3 Datasheet

Page 1

Page 2

Vishay Siliconix Si1403CDL Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 www.vishay.com 1 P-Channel 20 V (D-S) MOSFET FEATURES • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Load Switch for Portable Devices • DC/DC Converters PRODUCT SUMMARY VDS (V) RDS(on) () ID (A) c Qg (Typ.) - 20 0.140 at VGS = - 4.5 V - 2.1 4 nC0.160 at VGS = - 3.6 V - 1.9 0.222 at VGS = - 2.5 V - 1.6 Ordering Information: Si1403CDL-T1-GE3 (Lead (Pb)-free and Halogen-free) SOT-363 SC-70 (6-LEADS) 6 4 1 2 3 5 Top View D D G D D S Marking Code OE XX Lot Traceability and Date Code Part # Code Y Y S G D P-Channel MOSFET Notes: a. Surface mounted on 1" x 1" FR4 board. b. t = 5 s. c. Based on TC = 25 °C. d. Maximum under steady state conditions is 230 °C/W. ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage VDS - 20 V Gate-Source Voltage VGS ± 12 Continuous Drain Current (TJ = 150 °C) TC = 25 °C ID - 2.1 A TC = 70 °C - 1.6 TA = 25 °C - 1.6a, b TA = 70 °C - 1.3a, b Pulsed Drain Current (10 µs Pulse Width) IDM - 5 Continuous Source-Drain Diode Current TC = 25 °C IS - 1.75 TA = 25 °C - 0.5 a, b Maximum Power Dissipation TC = 25 °C PD 0.9 W TC = 70 °C 0.6 TA = 25 °C 0.6a, b TA = 70 °C 0.4a, b Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambienta, d t  5 s RthJA 180 220 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 115 140

Page 3

www.vishay.com 2 Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 Vishay Siliconix Si1403CDL Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 20 V VDS Temperature Coefficient VDS/TJ ID = - 250 µA - 15 mV/°C VGS(th) Temperature Coefficient VGS(th)/TJ 2.9 Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 0.6 - 1.5 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 12 V - 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 20 V, VGS = 0 V - 1 µA VDS = - 20 V, VGS = 0 V, TJ = 55 °C - 10 On-State Drain Currenta ID(on) VDS 5 V, VGS = - 4.5 V - 2 A Drain-Source On-State Resistancea RDS(on) VGS = - 4.5 V, ID = - 1.6 A 0.116 0.140 VGS = - 3.6 V, ID = - 1.5 A 0.133 0.160 VGS = - 2.5 V, ID = - 0.5 A 0.177 0.222 Forward Transconductancea gfs VDS = - 10 V, ID = - 1.6 A 5 S Dynamicb Input Capacitance Ciss VDS = - 10 V, VGS = 0 V, f = 1 MHz 281 pFOutput Capacitance Coss 73 Reverse Transfer Capacitance Crss 54 Total Gate Charge Qg VDS = - 10 V, VGS = - 4.5 V, ID = - 1.6 A 4 8 nCGate-Source Charge Qgs 0.7 Gate-Drain Charge Qgd 1.4 Gate Resistance Rg f = 1 MHz 2 7 14  Turn-On Delay Time td(on) VDD = - 10 V, RL = 7.7  ID  - 1.3 A, VGEN = - 4.5 V, Rg = 1  18 27 ns Rise Time tr 17 26 Turn-Off Delay Time td(off) 19 30 Fall Time tf 9 18 Turn-On Delay Time td(on) VDD = - 10 V, RL = 7.7  ID  - 1.3 A, VGEN = - 10 V, Rg = 1  5 10 Rise Time tr 10 20 Turn-Off Delay Time td(off) 17 26 Fall Time tf 7 14 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS TC = 25 °C - 1.75 A Pulse Diode Forward Current ISM - 5 Body Diode Voltage VSD IS = - 1.3 A, VGS = 0 V - 0.83 - 1.2 V Body Diode Reverse Recovery Time trr IF = - 2.0 A, dI/dt = 100 A/µs, TJ = 25 °C 12 20 ns Body Diode Reverse Recovery Charge Qrr 4 8 nC Reverse Recovery Fall Time ta 7 ns Reverse Recovery Rise Time tb 5

Page 4

Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 www.vishay.com 3 Vishay Siliconix Si1403CDL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Output Characteristics On-Resistance vs. Drain Current and Gate Voltage Gate Charge 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 VGS = 5 V thru 2.5 V VGS = 1.5 V VGS = 2 V VGS = 1 V VDS - Drain-to-Source Voltage (V) I D - D ra in C u rr e n t (A ) 0.08 0.11 0.14 0.17 0.20 0 1 2 3 4 5 VGS = 3.6 V VGS = 2.5 V VGS = 4.5 V R D S (o n ) - O n -R e s is ta n c e ( Ω ) ID - Drain Current (A) 0 2 4 6 8 10 0 2 4 6 8 10 ID = 1.6 A VDS = 10 V VDS = 16 V VDS = 5 V Qg - Total Gate Charge (nC) V G S - G a te -t o -S o u rc e V o lt a g e ( V ) Transfer Characteristics Capacitance On-Resistance vs. Junction Temperature 0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 TC = 125 °C TC = 25 °C TC = - 55 °C VGS - Gate-to-Source Voltage (V) I D - D ra in C u rr e n t (A ) Crss 0 100 200 300 400 500 0 5 10 15 20 Ciss Coss VDS - Drain-to-Source Voltage (V) C - C a p a c it a n c e ( p F ) 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 - 50 - 25 0 25 50 75 100 125 150 ID = - 1.6 A VGS = 4.5 V VGS = 3.6 V TJ - Junction Temperature (°C) (N o rm a li z e d ) R D S (o n ) - O n -R e s is ta n c e

Page 5

www.vishay.com 4 Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 Vishay Siliconix Si1403CDL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Source-Drain Diode Forward Voltage Threshold Voltage 0.1 1 10 100 0.0 0.3 0.6 0.9 1.2 1.5 TJ = 25 °C TJ = 150 °C VSD - Source-to-Drain Voltage (V) I S - S o u rc e C u rr e n t (A ) 0.50 0.65 0.80 0.95 1.10 1.25 - 50 - 25 0 25 50 75 100 125 150 ID = - 250 μA V G S (t h ) (V ) TJ - Temperature (°C) On-Resistance vs. Gate-to-Source Voltage Single Pulse Power, Junction-to-Ambient 0.00 0.06 0.12 0.18 0.24 0.30 1.0 2.5 4.0 5.5 7.0 8.5 10.0 TJ = 25 °C TJ = 125 °C ID = - 1.6 A R D S (o n ) - O n -R e s is ta n c e ( Ω ) VGS - Gate-to-Source Voltage (V) 0 1 2 3 4 5 0011001.0 0.1 Time (s) P o w e r (W ) 1 Safe Operating Area, Junction-to-Ambient 10 0.1 0.1 1 10 1 TA = 25 °C Single Pulse 1 ms 0.01 1 s, 10 s DC 100 10 ms 100 ms 100 μs BVDSS Limited VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified I D - D ra in C u rr e n t (A )

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Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 www.vishay.com 5 Vishay Siliconix Si1403CDL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Current Derating* 0.0 0.5 1.0 1.5 2.0 2.5 0 25 50 75 100 125 150 TC - Case Temperature (°C) I D - D ra in C u rr e n t (A ) Power Derating, Junction-to-Foot 0.0 0.3 0.6 0.9 1.2 0 25 50 75 100 125 150 TC - Case Temperature (°C) P o w e r (W ) Power Derating, Junction-to-Ambient 0.0 0.2 0.4 0.6 0.8 0 25 50 75 100 125 150 TA - Ambient Temperature (°C) P o w e r (W )

Page 7

www.vishay.com 6 Document Number: 67093 S10-2541-Rev. A, 08-Nov-10 Vishay Siliconix Si1403CDL TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67093. Normalized Thermal Transient Impedance, Junction-to-Ambient 10-3 10-2 1 10 100010-110-4 100 0.2 0.1 Square Wave Pulse Duration (s) N o rm a li z e d E ff e c ti v e T ra n s ie n t T h e rm a l Im p e d a n c e 0.1 0.01 t1 t2 Notes: PDM 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 230 °C/W 3. TJM - TA = PDMZthJA (t) t1 t2 4. Surface Mounted Duty Cycle = 0.5 Single Pulse 0.02 0.05 1 Normalized Thermal Transient Impedance, Junction-to-Foot 10-3 10-2 01110-110-4 0.2 0.1 Duty Cycle = 0.5 Square Wave Pulse Duration (s) N o rm a li z e d E ff e c ti v e T ra n s ie n t T h e rm a l Im p e d a n c e 1 0.1 0.01 0.05 Single Pulse 0.02

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L c EE1 e D e1 A2 A A1 1 -A- b -B- 2 3 6 5 4 Package Information Vishay Siliconix Document Number: 71154 06-Jul-01 www.vishay.com 1         Dim Min Nom Max Min Nom Max A 0.90 – 1.10 0.035 – 0.043 A1 – – 0.10 – – 0.004 A2 0.80 – 1.00 0.031 – 0.039 b 0.15 – 0.30 0.006 – 0.012 c 0.10 – 0.25 0.004 – 0.010 D 1.80 2.00 2.20 0.071 0.079 0.087 E 1.80 2.10 2.40 0.071 0.083 0.094 E1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65BSC 0.026BSC e1 1.20 1.30 1.40 0.047 0.051 0.055 L 0.10 0.20 0.30 0.004 0.008 0.012 7Nom 7Nom ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550

Page 9

AN813 Vishay Siliconix Document Number: 71236 12-Dec-03 www.vishay.com 1 Single-Channel LITTLE FOOT SC-70 3-Pin and 6-Pin MOSFET Recommended Pad Pattern and Thermal Peformance INTRODUCTION BASIC PAD PATTERNS This technical note discusses pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for single-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 350 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these single devices with a range of on-resistance specifications and in both traditional 3-pin and new 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance compared to the 3-pin package. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the single-channel SC-70 device in both 3-pin and 6-pin configurations. The pin-out of the 6-pin device allows the use of four pins as drain leads, which helps to reduce on-resistance and junction-to-ambient thermal resistance. SOT-323 SC-70 (3-LEADS) 1 2 3 Top View G S D SOT-363 SC-70 (6-LEADS) 6 4 1 2 3 5 Top View D D G FIGURE 1. For package dimensions see outline drawings: SC-70 (3-Leads) (http://www.vishay.com/doc?71153) SC-70 (6-Leads) (http://www.vishay.com/doc?71154) See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the basic pad layout and dimensions for the 3-pin SC-70 and the 6-pin SC-70. These pad patterns are sufficient for the low-power applications for which this package is intended. Increasing the pad pattern has little effect on thermal resistance for the 3-pin device, reducing it by only 10% to 15%. But for the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 35% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). The availability of four drain leads rather than the traditional single drain lead allows a better thermal path from the package to the PCB and external environment. EVALUATION BOARDS FOR THE SINGLE SC70-3 AND SC70-6 Figure 2 shows the 3-pin and 6-pin SC-70 evaluation boards (EVB). Both measure 0.6 inches by 0.5 inches. Their copper pad traces are the same as described in the previous section, Basic Pad Patterns. Both boards allow interrogation from the outer pins to 6-pin DIP connections, permitting test sockets to be used in evaluation testing. The thermal performance of the single SC-70 has been measured on the EVB for both the 3-pin and 6-pin devices, the results shown in Figures 3 and 4. The minimum recommended footprint on the evaluation board was compared with the industry standard of 1-inch square FR4 PCB with copper on both sides of the board. FIGURE 2. Front of Board SC70-3 Front of Board SC70-6Back of Board, SC70-3 and SC70-6 ChipFET ChipFET vishay.com

Page 10

AN813 Vishay Siliconix www.vishay.com 2 Document Number: 71236 12-Dec-03 THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 3-pin SC-70 measured as junction-to-foot thermal resistance is 285C/W typical, 340C/W maximum. Junction-to-foot thermal resistance for the 6-pin SC70-6 is 105C/W typical, 130C/W maximum — a nearly two-thirds reduction compared with the 3-pin device. The “foot” is the drain lead of the device as it connects with the body. This improved performance is obtained by the increase in drain leads from one to four on the 6-pin SC-70. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) The typical RθJAfor the single 3-pin SC-70 is 360C/W steady state, compared with 180C/W for the 6-pin SC-70. Maximum ratings are 430C/W for the 3-pin device versus 220C/W for the 6-pin device. All figures are based on the 1-inch square FR4 test board.The following table shows how the thermal resistance impacts power dissipation for the two different pin-outs at two different ambient temperatures. SC-70 (3-PIN) Room Ambient 25 C Elevated Ambient 60 C PD  TJ(max)  TA RJA PD  150oC  25oC 360oCW PD  347 mW PD  TJ(max)  TA RJA PD  150oC  60oC 360oCW PD  250 mW SC-70 (6-PIN) Room Ambient 25 C Elevated Ambient 60 C PD  TJ(max)  TA RJA PD  150oC  25oC 180oCW PD  694 mW PD  TJ(max)  TA RJA PD  150oC  60oC 180oCW PD  500 mW NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.5 W. Testing To aid comparison further, Figures 3 and 4 illustrate single-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of the thermal performance variation between the two packages. The measured steady state values of RθJA for the single 3-pin and 6-pin SC-70 are as follows: LITTLE FOOT SC-70 3-Pin 6-Pin 1) Minimum recommended pad pattern (see Figure 4) on the EVB. 410.31C/W 329.7C/W 2) Industry standard 1” square PCB with maximum copper both sides. 360C/W 211.8C/W The results show that designers can reduce thermal resistance RθJA on the order of 20% simply by using the 6-pin device rather than the 3-pin device. In this example, a 80C/W reduction was achieved without an increase in board area. If increasing board size is an option, a further 118C/W reduction could be obtained by utilizing a 1-inch square PCB area. Time (Secs) FIGURE 3. Comparison of SC70-3 and SC70-6 on EVB T he rm al R es is ta nc e (C /W ) 0 1 400 80 160 100 1000 240 1010-110-210-310-410-5 0.5 in x 0.6 in EVB 3-pin 320 Time (Secs) FIGURE 4. Comparison of SC70-3 and SC70-6 on 1” Square FR4 PCB T he rm al R es is ta nc e (C /W ) 0 1 400 80 160 100 1000 240 1010-110-210-310-410-5 1” Square FR4 PCB 320 6-pin 3-pin 6-pin

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