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SI6415DQ-T1-E3

hot SI6415DQ-T1-E3

SI6415DQ-T1-E3

For Reference Only

Part Number SI6415DQ-T1-E3
Manufacturer Vishay Siliconix
Description MOSFET P-CH 30V 6.5A 8-TSSOP
Datasheet SI6415DQ-T1-E3 Datasheet
Package 8-TSSOP (0.173", 4.40mm Width)
In Stock 3620 piece(s)
Unit Price $ 0.7192 *
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SI6415DQ-T1-E3

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SI6415DQ-T1-E3 Specifications

ManufacturerVishay Siliconix
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet SI6415DQ-T1-E3 Datasheet
Package8-TSSOP (0.173", 4.40mm Width)
SeriesTrenchFET?
FET TypeP-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)30V
Drive Voltage (Max Rds On, Min Rds On)4.5V, 10V
Vgs(th) (Max) @ Id1V @ 250µA (Min)
Gate Charge (Qg) (Max) @ Vgs70nC @ 10V
Vgs (Max)��20V
Power Dissipation (Max)1.5W (Ta)
Rds On (Max) @ Id, Vgs19 mOhm @ 6.5A, 10V
Operating Temperature-55°C ~ 150°C (TJ)
Mounting TypeSurface Mount
Supplier Device Package8-TSSOP
Package / Case8-TSSOP (0.173", 4.40mm Width)

SI6415DQ-T1-E3 Datasheet

Page 1

Page 2

Vishay Siliconix Si6415DQ Document Number: 70639 S-80682-Rev. C, 31-Mar-08 www.vishay.com 1 P-Channel 30-V (D-S) MOSFET FEATURES • Halogen-free • TrenchFET® Power MOSFETs PRODUCT SUMMARY VDS (V) RDS(on) (Ω) ID (A) - 30 0.019 at VGS = - 10 V ± 6.5 0.030 at VGS = - 4.5 V ± 5.2 Si6415DQ D S S G 1 2 3 4 8 7 6 5 D S S D TSSOP-8 Top View Ordering Information: Si6415DQ-T1 Si6415DQ-T1-GE3 (Lead (Pb)-free and Halogen-free) S* G D P-Channel MOSFET * Source Pins 2, 3, 6 and 7 must be tied common. Notes: a. Surface Mounted on FR4 board, t ≤ 10 s. * Pb containing terminations are not RoHS compliant, exemptions may apply. ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol Limit Unit Drain-Source Voltage VDS - 30 V Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C) a TA = 25 °C ID ± 6.5 A TA = 70 °C ± 5.2 Pulsed Drain Current IDM ± 30 Continuous Source Current (Diode Conduction)a IS - 1.5 Maximum Power Dissipationa TA = 25 °C PD 1.5 W TA = 70 °C 1.0 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Limit Unit Maximum Junction-to-Ambienta RthJA 83 °C/W Available Pb-free RoHS* COMPLIANT

Page 3

www.vishay.com 2 Document Number: 70639 S-80682-Rev. C, 31-Mar-08 Vishay Siliconix Si6415DQ Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1.0 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 30 V, VGS = 0 V - 1 µA VDS = - 30 V, VGS = 0 V, TJ = 55 °C - 25 On-State Drain Currenta ID(on) VDS = - 5 V, VGS = - 10 V - 20 A Drain-Source On-State Resistancea RDS(on) VGS = - 10 V, ID = - 6.5 A 0.015 0.019 Ω VGS = - 4.5 V, ID = - 5.2 A 0.022 0.030 Forward Transconductancea gfs VDS = - 15 V, ID = - 6.5 A 18.5 S Diode Forward Voltagea VSD IS = - 1.5 A, VGS = 0 V - 0.75 - 1.2 V Dynamicb Total Gate Charge Qg VDS = - 15 V, VGS = - 10 V, ID = - 6.5 A 47 70 nCGate-Source Charge Qgs 9.5 Gate-Drain Charge Qgd 8 Turn-On Delay Time td(on) VDD = - 15 V, RL = 15 Ω ID ≅ - 1 A, VGEN = - 10 V, RG = 6 Ω 16 30 ns Rise Time tr 17 30 Turn-Off Delay Time td(off) 73 110 Fall Time tf 31 60 Source-Drain Reverse Recovery Time trr IF = - 1.5 A, di/dt = 100 A/µs 40 60

Page 4

Document Number: 70639 S-80682-Rev. C, 31-Mar-08 www.vishay.com 3 Vishay Siliconix Si6415DQ TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Output Characteristics On-Resistance vs. Drain Current Gate Charge 0 5 10 15 20 25 30 0 2 4 6 8 10 VGS = 10 thru 4 V 3 V VDS - Drain-to-Source Voltage (V) - D ra in C u rr e n t (A ) I D 0 0.007 0.014 0.021 0.028 0.035 0 6 12 18 24 30 V GS = 4.5 V V GS = 10 V - O n -R e s is ta n c e ( Ω ) R D S (o n ) ID - Drain Current (A) 0 2 4 6 8 10 0 10 20 30 40 50 - G a te -t o -S o u rc e V o lt a g e ( V ) Qg - Total Gate Charge (nC) V G S VDS = 15 V ID = 6.5 A Transfer Characteristics Capacitance On-Resistance vs. Junction Temperature 0 5 10 15 20 25 30 0 1 2 3 4 5 VGS - Gate-to-Source Voltage (V) - D ra in C u rr e n t (A ) I D TC = 125 °C - 55 °C 25 °C 0 900 1800 2700 3600 4500 0 6 12 18 24 30 Crss Coss Ciss VDS - Drain-to-Source Voltage (V) C - C a p a c it a n c e ( p F ) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 - 50 - 25 0 25 50 75 100 125 150 VGS = 10 V ID = 6.5 A TJ - Junction Temperature (°C) (N o rm a liz e d ) - O n -R e s is ta n c e R D S (o n )

Page 5

www.vishay.com 4 Document Number: 70639 S-80682-Rev. C, 31-Mar-08 Vishay Siliconix Si6415DQ TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70639. Source-Drain Diode Forward Voltage Threshold Voltage 1.25 1.50 1 10 20 VSD - Source-to-Drain Voltage (V) - S o u rc e C u rr e n t (A ) I S 0.00 0.25 0.50 0.75 1.00 TJ = 25 °C TJ = 150 °C - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0.8 - 50 - 25 0 25 50 75 100 125 150 ID = 250 µA TJ - Temperature (°C) V a ri a n c e ( V ) V G S (t h ) On-Resistance vs. Gate-to-Source Voltage Single Pulse Power 0 0.02 0.04 0.06 0.08 0.10 0 2 4 6 8 10 ID = 6.5 A R D S (o n ) VGS - Gate-to-Source Voltage (V) 0 50 60 20 30 40 10 P o w e r ( W ) 0.01 1 10 30 Time (s) 0.1 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 0.1 0.01 10-4 10-3 10-2 10-1 1 10 30 Duty Cycle = 0.5 0.2 0.1 0.05 0.02 Single Pulse 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 83 °C/W 3. TJM - TA = PDMZthJA (t) t1 t2 t1 t2 Notes: 4. Surface Mounted PDM Square Wave Pulse Duration (s) N o rm a liz e d E ff e c ti v e T ra n s ie n t T h e rm a l I m p e d a n c e

Page 6

E 1 E C R 0.10 (4 Corners) B R 0.10 Corners) A A 2 A 1 D L L1 K1 0 .2 5 ( G a g e P la n e ) e Package Information Vishay Siliconix Document Number: 71201 06-Jul-01 www.vishay.com 1  JEDEC Part Number: MO-153     Dim Min Nom Max A – – 1.20 A1 0.05 0.10 0.15 A2 0.80 1.00 1.05 B 0.19 0.28 0.30 C – 0.127 – D 2.90 3.00 3.10 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e – 0.65 – L 0.45 0.60 0.75 L1 0.90 1.00 1.10 Y – – 0.10 K1 0 3 6 ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5844

Page 7

AN1001 Vishay Siliconix Document Number: 70571 12-Dec-03 www.vishay.com 1 LITTLE FOOT TSSOP-8 The Next Step in Surface-Mount Power MOSFETs Wharton McDaniel and David Oldham When Vishay Siliconix introduced its LITTLE FOOT MOSFETs, it was the first time that power MOSFETs had been offered in a true surface-mount package, the SOIC. LITTLE FOOT immediately found a home in new small form factor disk drives, computers, and cellular phones. The new LITTLE FOOT TSSOP-8 power MOSFETs are the natural evolutionary response to the continuing demands of many markets for smaller and smaller packages. LITTLE FOOT TSSOP-8 MOSFETs have a smaller footprint and a lower profile than LITTLE FOOT SOICs, while maintaining low rDS(on) and high thermal performance. Vishay Siliconix has accomplished this by putting one or two high-density MOSFET die in a standard 8-pin TSSOP package mounted on a custom leadframe. THE TSSOP-8 PACKAGE LITTLE FOOT TSSOP-8 power MOSFETs require approximately half the PC board area of an equivalent LITTLE FOOT device (Figure 1). In addition to the reduction in board area, the package height has been reduced to 1.1 mm. Top View Side View Figure 1. An TSSOP-8 Package Next to a SOIC-8 Package with Views from Both Top and Side This is the low profile demanded by applications such as PCMCIA cards. It reduces the power package to the same height as many resistors and capacitors in 0805 and 0605 sizes. It also allows placement on the “passive” side of the PC board. The standard pinouts of the LITTLE FOOT TSSOP-8 packages have been changed from the standard established by LITTLE FOOT. This change minimizes the contribution of interconnection resistance to rDS(on) and maximizes the transfer of heat out of the package. Figure 2 shows the pinouts for a single-die TSSOP. Notice that both sides of the package have Source and Drain connections, whereas LITTLE FOOT has the Source and Gate connections on one side of the package, and the Drain connections are on the opposite side. Figure 2. Pinouts for Single Die TSSOP Drain Source Source Gate Source Source Drain Drain Figure 3 shows the standard pinouts for a dual-die TSSOP-8. In this case, the connections for each individual MOSFET occupy one side. Figure 3. Pinouts for Dual-Die TSSOP Drain 1 Source 1 Source 1 Gate 1 Source 2 Source 2 Drain 2 Gate 2

Page 8

AN1001 Vishay Siliconix www.vishay.com 2 Document Number: 70571 12-Dec-03 Because the TSSOP has a fine pitch foot print, the pad layout is somewhat more demanding than the layout of the SOIC. Careful attention must be paid to silkscreen-to-pad and soldermask-to-pad clearances. Also, fiduciary marks may be required. The design and spacing of the pads must be dealt with carefully. The pads must be sized to hold enough solder paste to form a good joint, but should not be so large or so placed as to extend under the body, increasing the potential for solder bridging. The pad pattern should allow for typical pick and place errors of 0.25 mm. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the recommended pad pattern for PC board layout. THERMAL ISSUES LITTLE FOOT TSSOP MOSFETs have been given thermal ratings using the same methods used for LITTLE FOOT. The maximum thermal resistance junction-to-ambient is 83C/W for the single die and 125C/W for dual-die parts. TSSOP relies on a leadframe similar to LITTLE FOOT to remove heat from the package. The single- and dual-die leadframes are shown in Figure 4. Figure 4. Leadframe b) 8-Pin Dual-Pad TSSOP a) 8-Pin Single-Pad TSSOP The MOSFETs are characterized using a single pulse power test. For this test the device mounted on a one-square-inch piece of copper clad FR-4 PC board, such as those shown in Figure 5. The single pulse power test determines the maximum amount of power the part can handle for a given pulse width and defines the thermal resistance junction-to-ambient. The test is run for pulse widths ranging from approximately 10 ms to 100 seconds. The thermal resistance at 30 seconds is the rated thermal resistance for the part. This rating was chosen to allow comparison of packages and leadframes. At longer pulse widths, the PC board thermal charateristics become dominant, making all parts look the same. Figure 5. The actual test is based on dissipating a known amount of power in the device for a known period of time so the junction temperature is raised to 150C. The starting and ending junction temperatures are determined by measuring the forward drop of the body diode. The thermal resistance for that pulse width is defined by the temperature rise of the junction above ambient and the power of the pulse, Tja/P. Figure 6 shows the single pulse power curve of the Si6436DQ laid over the curve of the Si9936DY to give a comparison of the thermal performance. The die in the two devices have equivalent die areas, making this a comparison of the packaging. This comparison shows that the TSSOP package performs as well as the SOIC out to 150 ms, with long-term performance being 0.5 W less. Although the thermal performance is less, LITTLE FOOT TSSOP will operate in a large percentage of applications that are currently being served by LITTLE FOOT. 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0.1 1 10 100 P ow er ( W ) Time (Sec.) Si6436 Si9936 Figure 6. Comparison of Thermal Performance CONCLUSION TSSOP power MOSFETs provide a significant reduction in PC board footprint and package height, allowing reduction in board size and application where SOICs will not fit. This is accomplished using a standard IC package and a custom leadframe, combining small size with good power handling capability. For the TSSOP-8 package outline visit: http://www.vishay.com/doc?71201 For the SOIC-8 package outline visit: http://www.vishay.com/doc?71192

Page 9

AN806 Vishay Siliconix Document Number: 70738 17-Dec-03 www.vishay.com 1 Mounting LITTLE FOOT TSSOP-8 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFET, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT TSSOP-8 power MOSFET package footprint. In converting the footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. In the case of the TSSOP-8 package, the thermal connections are very simple. Pins 1, 5, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In the dual package, pins 1 and 8 are the two drains. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins also provide the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. FIGURE 1. Single MOSFET TSSOP-8 Pad Pattern with Copper Spreading 0.032 0.8 0.018 0.45 0.284 7.6 0.073 1.78 0.118 3.54 0.026 0.66 0.122 3.1 The pad patterns with copper spreading for the single-MOSFET TSSOP-8 (Figure 1) and dual-MOSFET TSSOP-8 (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose. FIGURE 2. Dual MOSFET TSSOP-8 Pad Pattern with Copper Spreading 0.026 0.66 0.284 7.6 0.032 0.8 0.122 3.1 0.091 1.65 0.073 1.78 0.018 0.45 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

Page 10

Application Note 826 Vishay Siliconix Document Number: 72611 www.vishay.com Revision: 21-Jan-08 27 A P P L I C A T I O N N O T E RECOMMENDED MINIMUM PADS FOR TSSOP-8 0 .2 6 2 (6 .6 5 5 ) Recommended Minimum Pads Dimensions in Inches/(mm) 0.092 (2.337) 0 .1 8 2 (4 .6 2 3 ) 0 .0 4 0 (1 .0 1 6 ) 0.026 (0.660) 0.014 (0.356) 0.012 (0.305) Return to Index Return to Index

SI6415DQ-T1-E3 Reviews

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Gwend*****Perez

February 11, 2020

EXACTLY what I was looking for -- one piece with a low forward voltage drop to isolate some DC power sources. They work fantastic!

Cast*****Lowe

January 26, 2020

Rec today in good order & condition . Thanks for speedy delivery.Regards.

Mart*****ines

January 3, 2020

They work great and I hope to find more used for the extra ones.

Andr*****rtega

December 25, 2019

Wow super fast delivery, product as described good company!

Rub*****Mutti

December 4, 2019

The order process is easy and user friendly, very helpful customer service, always fast shipping.

Cassa*****Ganesan

September 22, 2019

Awesome components selection and availability. Ordering process is easy. They don't spam me after the purchase.

Yehu*****eeks

September 8, 2019

A well designed product that fit my custom PCB's perfectly. Easy to use. Sturdy construction. Highly recommend to all PCB builders.

Dami*****enson

June 28, 2019

2nd time buying these - quite good. Very fast shipping

Anni*****orona

June 16, 2019

Can't speak to the long term reliability as of yet, but they seem to be of decent quality and I don't expect any issues.

Kor*****ugar

June 7, 2019

This is the best online shop to order electronic components. From a 30 cent item up to industrial, Customer Service is great. This company is so reliable and super easy to work with and ask questions. One CS agent even stayed after hours to get me an answer!

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