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SI8441AB-D-IS

hot SI8441AB-D-IS

SI8441AB-D-IS

For Reference Only

Part Number SI8441AB-D-IS
Manufacturer Silicon Labs
Description DGTL ISO 2.5KV GEN PURP 16SOIC
Datasheet SI8441AB-D-IS Datasheet
Package 16-SOIC (0.295", 7.50mm Width)
In Stock 18886 piece(s)
Unit Price $ 1.88 *
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SI8441AB-D-IS

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SI8441AB-D-IS Specifications

ManufacturerSilicon Labs
CategoryIsolators - Digital Isolators
Datasheet SI8441AB-D-IS Datasheet
Package16-SOIC (0.295", 7.50mm Width)
SeriesAutomotive, AEC-Q100
TechnologyCapacitive Coupling
TypeGeneral Purpose
Isolated PowerNo
Number of Channels4
Inputs - Side 1/Side 23/1
Channel TypeUnidirectional
Voltage - Isolation2500Vrms
Common Mode Transient Immunity (Min)25kV/µs (Typ)
Data Rate1Mbps
Propagation Delay tpLH / tpHL (Max)35ns, 35ns
Pulse Width Distortion (Max)25ns
Rise / Fall Time (Typ)3.8ns, 2.8ns
Voltage - Supply2.7 V ~ 5.5 V
Operating Temperature-40°C ~ 125°C
Package / Case16-SOIC (0.295", 7.50mm Width)
Supplier Device Package16-SOIC

SI8441AB-D-IS Datasheet

Page 1

Page 2

No t R ec om m en de d fo r N ew D es ign s Rev. 1.7 4/18 Copyright © 2018 by Silicon Laboratories Si8440/41/42/45 Si8440/41/42/45 LOW-POWER QUAD-CHANNEL DIGITAL ISOLATOR Features Applications Safety Regulatory Approvals Description Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages when compared to legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges throughout their service life. For ease of design, only VDD bypass capacitors are required. Data rates up to 150 Mbps are supported, and all devices achieve worst-case propagation delays of less than 10 ns. All products are safety certified by UL, CSA, and VDE and support withstand voltages of up to 2.5 kVrms. These devices are available in 16-pin wide- and narrow-body SOIC packages.  High-speed operation DC to 150 Mbps  No start-up initialization required  Wide Operating Supply Voltage: 2.70–5.5 V  Wide Operating Supply Voltage: 2.70–5.5V  Ultra low power (typical) 5 V Operation: < 1.6 mA per channel at 1 Mbps < 6 mA per channel at 100 Mbps 2.70 V Operation: < 1.4 mA per channel at 1 Mbps < 4 mA per channel at 100 Mbps  High electromagnetic immunity  Up to 2500 VRMS isolation  60-year life at rated working voltage  Precise timing (typical) <10 ns worst case 1.5 ns pulse width distortion 0.5 ns channel-channel skew 2 ns propagation delay skew 6 ns minimum pulse width  Transient Immunity 25 kV/µs  AEC-Q100 qualified  Wide temperature range –40 to 125 °C at 150 Mbps  RoHS-compliant packages SOIC-16 wide body SOIC-16 narrow body  Industrial automation systems  Hybrid electric vehicles  Isolated switch mode supplies  Isolated ADC, DAC  Motor control  Power inverters  Communications systems  UL 1577 recognized Up to 2500 VRMS for 1 minute  CSA component notice 5A approval IEC 60950-1, 61010-1 (reinforced insulation)  VDE certification conformity IEC 60747-5-2 (VDE0884 Part 2) Ordering Information: See page 26.

Page 3

Si8440/41/42/45 Rev. 1.7 2 No t R ec om m en de d fo r N ew D es ign s TABLE OF CONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.4. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3. Errata and Design Migration Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.1. Enable Pin Causes Outputs to Go Low (Revision C Only) . . . . . . . . . . . . . . . . . . . .24 3.2. Power Supply Bypass Capacitors (Revision C and Revision D) . . . . . . . . . . . . . . . .24 3.3. Latch Up Immunity (Revision C Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 6. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 10. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 10.1. 16-Pin Wide Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11. Top Marking: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 11.1. 16-Pin Narrow Body SOIC Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Page 4

Si8440/41/42/45 Rev. 1.7 3 No t R ec om m en de d fo r N ew D es ign s 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit Ambient Operating Temperature* TA 150 Mbps, 15 pF, 5 V –40 25 125 ºC Supply Voltage VDD1 2.70 — 5.5 V VDD2 2.70 — 5.5 V *Note: The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 2. Absolute Maximum Ratings1 Parameter Symbol Min Typ Max Unit Storage Temperature2 TSTG –65 — 150 °C Ambient Temperature Under Bias TA –40 — 125 °C Supply Voltage (Revision C)3 VDD1, VDD2 –0.5 — 5.75 V Supply Voltage (Revision D)3 VDD1, VDD2 –0.5 — 6.0 V Input Voltage VI –0.5 — VDD + 0.5 V Output Voltage VO –0.5 — VDD + 0.5 V Output Current Drive Channel IO — — 10 mA Lead Solder Temperature (10 s) — — 260 °C Maximum Isolation Voltage (1 s) — — 3600 VRMS Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may degrade performance. 2. VDE certifies storage temperature from –40 to 150 °C. 3. See "5. Ordering Guide" on page 26 for more information.

Page 5

Si8440/41/42/45 4 Rev. 1.7 No t R ec om m en de d fo r N ew D es ign s Table 3. Electrical Characteristics (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 4.8 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V Input Leakage Current IL — — ±10 µA Output Impedance1 ZO — 85 —  Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at Supply) Si8440Ax, Bx and Si8445Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.5 2.5 5.7 2.6 2.3 3.8 8.6 3.9 mA Si8441Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.8 2.5 4.9 3.6 2.7 3.8 7.4 5.4 mA Si8442Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8440Ax, Bx and Si8445Bx VDD1 VDD2 — — 3.6 3.0 5.4 3.9 mA Si8441Ax, Bx VDD1 VDD2 — — 3.5 3.4 5.3 5.1 mA Si8442Ax, Bx VDD1 VDD2 — — 3.6 3.6 5.4 5.4 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.

Page 6

Si8440/41/42/45 Rev. 1.7 5 No t R ec om m en de d fo r N ew D es ign s 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8440Bx, Si8445Bx VDD1 VDD2 — — 3.6 4.0 5.4 5.6 mA Si8441Bx VDD1 VDD2 — — 3.7 4.1 5.5 5.7 mA Si8442Bx VDD1 VDD2 — — 4.2 4.2 5.9 5.9 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8440Bx, Si8445Bx VDD1 VDD2 — — 3.8 19.4 5.7 24.3 mA Si8441Bx VDD1 VDD2 — — 8.0 15.8 10 19.8 mA Si8442Bx VDD1 VDD2 — — 11.8 11.8 14.8 14.8 mA Timing Characteristics Si844xAx Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Propagation Delay tPHL, tPLH See Figure 2 — — 35 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 2 — — 25 ns Propagation Delay Skew2 tPSK(P-P) — — 40 ns Channel-Channel Skew tPSK — — 35 ns Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.

Page 7

Si8440/41/42/45 6 Rev. 1.7 No t R ec om m en de d fo r N ew D es ign s Si844xBx Maximum Data Rate 0 — 150 Mbps Minimum Pulse Width — — 6.0 ns Propagation Delay tPHL, tPLH See Figure 2 3.0 6.0 9.5 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 2 — 1.5 2.5 ns Propagation Delay Skew2 tPSK(P-P) — 2.0 3.0 ns Channel-Channel Skew tPSK — 0.5 1.8 ns All Models Output Rise Time tr CL = 15 pF See Figure 2 — 3.8 5.0 ns Output Fall Time tf CL = 15 pF See Figure 2 — 2.8 3.7 ns Common Mode Transient Immunity CMTI VI = VDD or 0 V — 25 — kV/µs Enable to Data Valid3 ten1 See Figure 1 — 5.0 8.0 ns Enable to Data Tri-State3 ten2 See Figure 1 — 7.0 9.2 ns Start-up Time3,4 tSU — 15 40 µs Table 3. Electrical Characteristics (Continued) (VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.

Page 8

Si8440/41/42/45 Rev. 1.7 7 No t R ec om m en de d fo r N ew D es ign s Figure 1. ENABLE Timing Diagram Figure 2. Propagation Delay Timing ENABLE OUTPUTS ten1 ten2 Typical Input tPLH tPHL Typical Output tr tf 90% 10% 90% 10% 1.4 V 1.4 V

Page 9

Si8440/41/42/45 8 Rev. 1.7 No t R ec om m en de d fo r N ew D es ign s Table 4. Electrical Characteristics (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit High Level Input Voltage VIH 2.0 — — V Low Level Input Voltage VIL — — 0.8 V High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 – 0.4 3.1 — V Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V Input Leakage Current IL — — ±10 µA Output Impedance1 ZO — 85 —  Enable Input High Current IENH VENx = VIH — 2.0 — µA Enable Input Low Current IENL VENx = VIL — 2.0 — µA DC Supply Current (All inputs 0 V or at supply) Si8440Ax, Bx and Si8445Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.5 2.5 5.7 2.6 2.3 3.8 8.6 3.9 mA Si8441Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 1.8 2.5 4.9 3.6 2.7 3.8 7.4 5.4 mA Si8442Ax, Bx VDD1 VDD2 VDD1 VDD2 All inputs 0 DC All inputs 0 DC All inputs 1 DC All inputs 1 DC — — — — 2.3 2.3 4.5 4.5 3.5 3.5 6.8 6.8 mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8440Ax, Bx and Si8445Bx VDD1 VDD2 — — 3.6 3.0 5.4 3.9 mA Si8441Ax, Bx VDD1 VDD2 — — 3.5 3.4 5.3 5.1 mA Si8442Ax, Bx VDD1 VDD2 — — 3.6 3.6 5.4 5.4 mA Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.

Page 10

Si8440/41/42/45 Rev. 1.7 9 No t R ec om m en de d fo r N ew D es ign s 10 Mbps Supply Current (All inputs = 5 MHz square wave, CI = 15 pF on all outputs) Si8440Bx, Si8445Bx VDD1 VDD2 — — 3.6 4.0 5.4 5.6 mA Si8441Bx VDD1 VDD2 — — 3.7 4.1 5.5 5.7 mA Si8442Bx VDD1 VDD2 — — 4.2 4.2 5.9 5.9 mA 100 Mbps Supply Current (All inputs = 50 MHz square wave, CI = 15 pF on all outputs) Si8440Bx, Si8445Bx VDD1 VDD2 — — 3.6 14 5.5 17.5 mA Si8441Bx VDD1 VDD2 — — 6.4 11.4 8.0 14.5 mA Si8442Bx VDD1 VDD2 — — 8.6 8.6 10.8 10.8 mA Timing Characteristics Si844xAx Maximum Data Rate 0 — 1.0 Mbps Minimum Pulse Width — — 250 ns Propagation Delay tPHL,tPLH Se Figure 2 — — 35 ns Pulse Width Distortion |tPLH - tPHL| PWD See Figure 2 — — 25 ns Propagation Delay Skew2 tPSK(P-P) — — 40 ns Channel-Channel Skew tPSK — — 35 ns Table 4. Electrical Characteristics (Continued) (VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA = –40 to 125 °C; applies to narrow and wide-body SOIC packages) Parameter Symbol Test Condition Min Typ Max Unit Notes: 1. The nominal output impedance of an isolator driver channel is approximately 85 , ±40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. See "3. Errata and Design Migration Guidelines" on page 24 for more details. 4. Start-up time is the time period from the application of power to valid data at the output.

SI8441AB-D-IS Reviews

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December 29, 2020

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November 27, 2019

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October 26, 2019

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October 24, 2019

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September 21, 2019

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May 27, 2019

Excellent sales and service. Thank you. Buy with confidence.

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April 17, 2019

As I said before, your crew rock's keep up the fantastic work as we need you out there.

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December 25, 2018

Received Quickly. Excellent Communication. Capacitors Look Excellent

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December 7, 2018

Quality electronic components plus fast response.Thank you.

Dav*****Floyd

September 6, 2018

They worked as I expected. I'll definitely purchase again. Thank you!

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