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SPC5604BF2MLH6

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SPC5604BF2MLH6

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Part Number SPC5604BF2MLH6
Manufacturer NXP
Description IC MCU 32BIT 512KB FLASH 64LQFP
Datasheet SPC5604BF2MLH6 Datasheet
Package 64-LQFP
In Stock 394 piece(s)
Unit Price $ 9.7147 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 3 - Jun 8 (Choose Expedited Shipping)
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Part Number # SPC5604BF2MLH6 (Embedded - Microcontrollers) is manufactured by NXP and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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SPC5604BF2MLH6 Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet SPC5604BF2MLH6Datasheet
Package64-LQFP
SeriesMPC56xx Qorivva
Core Processore200z0h
Core Size32-Bit
Speed64MHz
ConnectivityCAN, I2C, LIN, SCI, SPI
PeripheralsDMA, POR, PWM, WDT
Number of I/O45
Program Memory Size512KB (512K x 8)
Program Memory TypeFLASH
EEPROM Size4K x 16
RAM Size32K x 8
Voltage - Supply (Vcc/Vdd)3 V ~ 5.5 V
Data ConvertersA/D 12x10b
Oscillator TypeInternal
Operating Temperature-40°C ~ 125°C (TA)
Mounting Type-
Package / Case64-LQFP
Supplier Device Package64-LQFP (10x10)

SPC5604BF2MLH6 Datasheet

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Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5604BC Rev. 13, 01/2015 © Freescale Semiconductor, Inc., 2009-2015. All rights reserved. This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MPC5604B/C TBD MAPBGA–225 15 mm x 15 mm QFN12 ##_mm_x_##mm SOT-343R ##_mm_x_##mm PKG-TBD ## mm x ## mm 208 MAPBGA (17 x 17 x 1.7 mm) 144 LQFP (20 x 20 x 1.4 mm) 100 LQFP (14 x 14 x 1.4 mm) 64 LQFP (10 x 10 x 1.4 mm) Features • Single issue, 32-bit CPU core complex (e200z0) — Compliant with the Power Architecture® embedded category — Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. • Up to 512 KB on-chip code flash supported with the flash controller and ECC • 64 (4 × 16) KB on-chip data flash memory with ECC • Up to 48 KB on-chip SRAM with ECC • Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity • Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources • Frequency modulated phase-locked loop (FMPLL) • Crossbar switch architecture for concurrent access to peripherals, flash memory, or RAM from multiple bus masters • Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) • Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) • 10-bit analog-to-digital converter (ADC) • 3 serial peripheral interface (DSPI) modules • Up to 4 serial communication interface (LINFlex) modules MPC5604B/C Microcontroller Data Sheet • Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers • 1 inter IC communication interface (I2C) module • Up to 123 configurable general purpose pins supporting input and output operations (package dependent) • Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds • Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution • 1 System Module Timer (STM) • Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard • Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) • On-chip voltage regulator (VREG) for regulation of input supply for all internal levels

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MPC5604B/C Microcontroller Data Sheet, Rev. 13 Freescale Semiconductor2 Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 Pad configuration during reset phases . . . . . . . . . . . . . 11 2.3 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.7 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .30 2.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . .30 2.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.11.1 NVUSRO[PAD3V5V] field description . . . . . . . .30 2.11.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.11.3 NVUSRO[WATCHDOG_EN] field description . .31 2.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .32 2.13 Recommended operating conditions . . . . . . . . . . . . . .33 2.14 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Package thermal characteristics . . . . . . . . . . . .35 2.14.2 Power considerations . . . . . . . . . . . . . . . . . . . .36 2.15 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . .36 2.15.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.15.2 I/O input DC characteristics . . . . . . . . . . . . . . . .37 2.15.3 I/O output DC characteristics. . . . . . . . . . . . . . .38 2.15.4 Output pin transition times. . . . . . . . . . . . . . . . .40 2.15.5 I/O pad current specification . . . . . . . . . . . . . . .41 2.16 RESET electrical characteristics. . . . . . . . . . . . . . . . . .46 2.17 Power management electrical characteristics. . . . . . . .48 2.17.1 Voltage regulator electrical characteristics . . . .48 2.17.2 Low voltage detector electrical characteristics .52 2.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.19 Flash memory electrical characteristics . . . . . . . . . . . .56 2.19.1 Program/Erase characteristics . . . . . . . . . . . . . 56 2.19.2 Flash power supply DC characteristics . . . . . . 57 2.19.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . 58 2.20 Electromagnetic compatibility (EMC) characteristics. . 58 2.20.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.20.2 Electromagnetic interference (EMI) . . . . . . . . . 58 2.20.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.21 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 60 2.22 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 62 2.23 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . 64 2.24 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 65 2.25 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 66 2.26 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . 68 2.26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.26.2 Input impedance and ADC accuracy . . . . . . . . 68 2.26.3 ADC electrical characteristics . . . . . . . . . . . . . 73 2.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.27.1 Current consumption . . . . . . . . . . . . . . . . . . . . 75 2.27.2 DSPI characteristics. . . . . . . . . . . . . . . . . . . . . 76 2.27.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . 82 2.27.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . 83 3 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 84 3.1.1 64 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.1.2 100 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.1.3 144 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.1.4 208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . 93 4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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In tro d u c tio n M P C 560 4B /C M icro co n tro lle r D ata S h ee t, R ev. 13 F re escale S em ico nductor 3 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture® embedded category. The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. Table 1. MPC5604B/C device comparison1 Feature Device MPC56 02BxLH MPC56 02BxLL MPC56 02BxLQ MPC56 02CxLH MPC56 02CxLL MPC56 03BxLH MPC56 03BxLL MPC56 03BxLQ MPC56 03CxLH MPC56 03CxLL MPC56 04BxLH MPC56 04BxLL MPC56 04BxLQ MPC56 04CxLH MPC56 04CxLL MPC5604 BxMG CPU e200z0h Execution speed2 Static – up to 64 MHz Code Flash 256 KB 384 KB 512 KB Data Flash 64 KB (4 × 16 KB) RAM 24 KB 32 KB 28 KB 40 KB 32 KB 48 KB MPU 8-entry ADC (10-bit) 12 ch 28 ch 36 ch 8 ch 28 ch 12 ch 28 ch 36 ch 8 ch 28 ch 12 ch 28 ch 36 ch 8 ch 28 ch 36 ch CTU Yes Total timer I/O3 eMIOS 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit

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M P C 560 4B /C M icro co n tro lle r D ata S h ee t, R ev. 13 In tro d u ctio n F re escale S em ico nductor 4 Block diagram Figure 1 shows a top-level block diagram of the MPC5604B/C device series. • PWM + MC + IC/OC4 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch • PWM + IC/OC4 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch • IC/OC4 — 3 ch 6 ch — 3 ch — 3 ch 6 ch — 3 ch — 3 ch 6 ch — 3 ch 6 ch SCI (LINFlex) 35 4 SPI (DSPI) 2 3 2 3 2 3 2 3 2 3 2 3 CAN (FlexCAN) 26 5 6 37 5 6 26 37 5 6 I2C 1 32 kHz oscillator Yes GPIO8 45 79 123 45 79 45 79 123 45 79 45 79 123 45 79 123 Debug JTAG Nexus2+ Package 64 LQFP 100 LQFP 144 LQFP 64 LQFP 100 LQFP 64 LQFP 100 LQFP 144 LQFP 64 LQFP 100 LQFP 64 LQFP 100 LQFP 144 LQFP 64 LQFP 100 LQFP 208 MAPBGA9 1 Feature set dependent on selected peripheral multiplexing—table shows example implementation. 2 Based on 125 °C ambient operating temperature. 3 See the eMIOS section of the device reference manual for information on the channel configuration and functions. 4 IC – Input Capture; OC – Output Compare; PWM – Pulse Width Modulation; MC – Modulus counter. 5 SCI0, SCI1 and SCI2 are available. SCI3 is not available. 6 CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7 CAN0, CAN3 and either CAN1 or CAN4 are available. CAN2, CAN5 and CAN6 are not available 8 I/O count based on multiplexing with peripherals. 9 208 MAPBGA available only as development package for Nexus2+. Table 1. MPC5604B/C device comparison1 (continued) Feature Device MPC56 02BxLH MPC56 02BxLL MPC56 02BxLQ MPC56 02CxLH MPC56 02CxLL MPC56 03BxLH MPC56 03BxLL MPC56 03BxLQ MPC56 03CxLH MPC56 03CxLL MPC56 04BxLH MPC56 04BxLL MPC56 04BxLQ MPC56 04CxLH MPC56 04CxLL MPC5604 BxMG

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Introduction MPC5604B/C Microcontroller Data Sheet, Rev. 13 Freescale Semiconductor 5 Figure 1. MPC5604B/C block diagram Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the presence and number of blocks vary by device and package. 3 x DSPI FMPLL Nexus 2+ Nexus SRAM SIUL Reset control 48 KB External IMUX GPIO and JTAG pad control JTAG port Nexus port e200z0h Interrupt requests 64 -b it 2 x 3 C ro ss b a r S w itc h 6 x FlexCAN Peripheral bridge interrupt request Interrupt request I/O Clocks Instructions Data Voltage regulator NMI SWT PITSTM NMI SIUL . . . . . . . . .. . . INTC I2C . . . 4 x LINFlex 2 x eMIOS 36 Ch. ADC M P U CMU SRAM Flash Code Flash 512 KB Data Flash 64 KB MC_PCUMC_MEMC_CGMMC_RGM BAM CTU RTC SSCM (Master) (Master) (Slave) (Slave) (Slave) controllercontroller Legend: ADC Analog-to-Digital Converter BAM Boot Assist Module FlexCAN Controller Area Network CMU Clock Monitor Unit CTU Cross Triggering Unit DSPI Deserial Serial Peripheral Interface eMIOS Enhanced Modular Input Output System FMPLL Frequency-Modulated Phase-Locked Loop I2C Inter-integrated Circuit Bus IMUX Internal Multiplexer INTC Interrupt Controller JTAG JTAG controller LINFlex Serial Communication Interface (LIN support) ECSM Error Correction Status Module MC_CGM Clock Generation Module MC_ME Mode Entry Module MC_PCU Power Control Unit MC_RGM Reset Generation Module MPU Memory Protection Unit Nexus Nexus Development Interface (NDI) Level NMI Non-Maskable Interrupt PIT Periodic Interrupt Timer RTC Real-Time Clock SIUL System Integration Unit Lite SRAM Static Random-Access Memory SSCM System Status Configuration Module STM System Timer Module SWT Software Watchdog Timer WKPU Wakeup Unit MPU ECSM from peripheral registers blocks WKPU Interrupt request with wakeup functionality

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MPC5604B/C Microcontroller Data Sheet, Rev. 13 Introduction Freescale Semiconductor6 Table 2. MPC5604B/C series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to-digital converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Deserial serial peripheral interface (DSPI) Provides a synchronous serial interface for communication with external devices Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access (eDMA) Performs complex data transfers with minimal intervention from a host processor via “n” programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol Frequency-modulated phase-locked loop (FMPLL) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINFlex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called “power domains” which are controlled by the PCU Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device

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Package pinouts and signal descriptions MPC5604B/C Microcontroller Data Sheet, Rev. 13 Freescale Semiconductor 7 2 Package pinouts and signal descriptions 2.1 Package pinouts The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual. Nexus development interface (NDI) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) System integration unit (SIU) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) Provides storage for program code, constants, and variables System status configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR (Automotive Open System Architecture) and operating system tasks Software watchdog timer (SWT) Provides protection from runaway code Wakeup unit (WKPU) The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width. Table 2. MPC5604B/C series block summary (continued) Block Function

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MPC5604B/C Microcontroller Data Sheet, Rev. 13 Package pinouts and signal descriptions Freescale Semiconductor8 Figure 2. MPC560xB LQFP 64-pin configuration Figure 3. MPC560xC LQFP 64-pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 PB[3] PC[9] PA[2] PA[1] PA[0] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC P C [7 ] P A [1 5 ] P A [1 4 ] P A [4 ] P A [1 3 ] P A [1 2 ] V D D _ LV V S S _ LV X TA L V S S _ H V E X TA L V D D _ H V P B [9 ] P B [8 ] P B [1 0 ] P B [4 ] P B [2 ] P C [8 ] P C [4 ] P C [5 ] P H [9 ] P C [0 ] V S S _ LV V D D _L V V D D _H V V S S _ H V P C [1 ] P H [1 0 ] P A [6 ] P A [5 ] P C [2 ] P C [3 ] 64 LQFP Top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 PB[3] PC[9] PA[2] PA[1] PA[0] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] PA[11] PA[10] PA[9] PA[8] PA[7] PF[14] PF[15] PG[0] PG[1] PA[3] PB[15] PB[14] PB[11] PB[7] VDD_HV_ADC VSS_HV_ADC P C [7 ] P A [1 5 ] P A [1 4 ] P A [4 ] P A [1 3 ] P A [1 2 ] V D D _ LV V S S _ LV X TA L V S S _ H V E X TA L V D D _ H V P B [9 ] P B [8 ] P B [1 0 ] P B [4 ] P B [2 ] P C [8 ] P C [4 ] P C [5 ] P H [9 ] P C [0 ] V S S _ LV V D D _ LV V D D _ H V V S S _ H V P C [1 ] P H [1 0 ] P A [6 ] P A [5 ] P C [2 ] P C [3 ] 64 LQFP Top view

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Package pinouts and signal descriptions MPC5604B/C Microcontroller Data Sheet, Rev. 13 Freescale Semiconductor 9 Figure 4. LQFP 100-pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 10 0 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC P C [7 ] P A [1 5] P A [1 4] P A [4 ] P A [1 3] P A [1 2] V D D _ LV V S S _ LV X TA L V S S _ H V E X TA L V D D _ H V P B [9 ] P B [8 ] P B [1 0] P D [0 ] P D [1 ] P D [2 ] P D [3 ] P D [4 ] P D [5 ] P D [6 ] P D [7 ] P D [8 ] P B [4 ] P B [2 ] P C [8 ] P C [1 3 ] P C [1 2 ] P E [7 ] P E [6 ] P E [5 ] P E [4 ] P C [4 ] P C [5 ] P E [3 ] P E [2 ] P H [9 ] P C [0 ] V S S _ LV V D D _ LV V D D _ H V V S S _ H V P C [1 ] P H [1 0 ] P A [6 ] P A [5 ] P C [2 ] P C [3 ] P E [1 2] 100 LQFP Note: Availability of port pin alternate functions depends on product selection. Top view

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SPC5604BF2MLH6

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