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SPC5675KFF0MMS2

hot SPC5675KFF0MMS2

SPC5675KFF0MMS2

For Reference Only

Part Number SPC5675KFF0MMS2
Manufacturer NXP
Description IC MCU 32BIT 2MB FLASH 473MAPBGA
Datasheet SPC5675KFF0MMS2 Datasheet
Package 473-LFBGA
In Stock 254 piece(s)
Unit Price $ 44.2081 *
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SPC5675KFF0MMS2 Specifications

ManufacturerNXP
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet SPC5675KFF0MMS2 Datasheet
Package473-LFBGA
SeriesMPC56xx Qorivva
Core Processore200z7d
Core Size32-Bit
Speed180MHz
ConnectivityCAN, EBI/EMI, Ethernet, FlexRay, I2C, LIN, SPI
PeripheralsDMA, POR, PWM, WDT
Program Memory Size2MB (2M x 8)
Program Memory TypeFLASH
EEPROM Size64K x 8
RAM Size512K x 8
Voltage - Supply (Vcc/Vdd)1.14 V ~ 1.32 V
Data ConvertersA/D 34x12b
Oscillator TypeInternal
Operating Temperature-40°C ~ 125°C (TA)
Package / Case473-LFBGA
Supplier Device Package473-MAPBGA (19x19)

SPC5675KFF0MMS2 Datasheet

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TBD MAPBGA–225 15 mm x 15 mm QFN12 ##_mm_x_##mm SOT-343R ##_mm_x_##mm PKG-TBD ## mm x ## mm 257 MAPBGA (14 x 14 mm) 473 MAPBGA (19 x 19 mm) Freescale Semiconductor Data Sheet: Technical Data Document Number: MPC5675K Rev. 8, 10/2013 MPC5675K © Freescale Semiconductor, Inc., 2009–2013. All rights reserved. 1 Introduction 1.1 Document overview This document provides electrical specifications, pin assignments, and package diagrams for the Qorivva MPC5675K series of microcontroller units (MCUs). 1.2 Description The Qorivva MPC5675K microcontroller, a SafeAssure solution, is a 32-bit embedded controller designed for advanced driver assistance systems with RADAR, CMOS imaging, LIDAR and ultrasonic sensors, and multiple 3-phase motor control applications as in hybrid electric vehicles (HEV) in automotive and high temperature industrial applications. A member of Freescale Semiconductor’s Qorivva MPC5500/5600 family, it contains the Book E compliant Power Architecture technology core with Variable Length Encoding (VLE). This core complies with the Power Architecture embedded category, and is 100 percent user mode compatible with the original Power PC user instruction set architecture (UISA). It offers system performance up to four times that of its MPC5561 predecessor, while bringing you the reliability and familiarity of the proven Power Architecture technology. A comprehensive suite of hardware and software development tools is available to help simplify and speed system design. Development support is available from leading tools vendors providing compilers, debuggers and simulation development environments. 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . 18 2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 70 3.3 Recommended operating conditions . . . . . . . . . . . . . . 71 3.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5 Electromagnetic interference (EMI) characteristics . . . 74 3.6 Electrostatic discharge (ESD) characteristics. . . . . . . . 75 3.7 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.8 Power Management Controller (PMC) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.9 Supply current characteristics . . . . . . . . . . . . . . . . . . . 77 3.10 Temperature sensor electrical characteristics . . . . . . . 78 3.11 Main oscillator electrical characteristics . . . . . . . . . . . . 78 3.12 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 79 3.13 16 MHz RC oscillator electrical characteristics. . . . . . . 80 3.14 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 81 3.15 Flash memory electrical characteristics . . . . . . . . . . . . 86 3.16 SRAM memory electrical characteristics . . . . . . . . . . . 88 3.17 GP pads specifications . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.18 PDI pads specifications . . . . . . . . . . . . . . . . . . . . . . . . 91 3.19 DRAM pad specifications . . . . . . . . . . . . . . . . . . . . . . . 94 3.20 RESET characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101 3.21 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.22 Peripheral timing characteristics. . . . . . . . . . . . . . . . . 108 4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . 132 5 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Qorivva MPC5675K Microcontroller Data Sheet

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MPC5675K Microcontroller Data Sheet, Rev. 8 Introduction Freescale Semiconductor2 1.3 Device comparison Table 1. MPC5675K family device comparison Features MPC5673K MPC5674K MPC5675K CPU Type 2 × e200z7d (SoR1) in lock-step or decoupled operation Architecture Harvard Execution speed 0–150 MHz (+2% FM) 0–180 MHz (+2% FM) 0–180 MHz (+2% FM) Nominal platform frequency (in 1:1, 1:2, and 1:3 modes) 0–75 MHz (+2% FM) 0–90 MHz (+2% FM) 0–90 MHz (+2% FM) MMU 64 entries (SoR) Instruction set PPC Yes Instruction set VLE Yes Instruction cache 16 KB, 4-way with EDC (SoR) Data cache 16 KB, 4-way with Parity (SoR) MPU Yes (SoR) Buses Core bus 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data XBAR Master  slave ports Yes (SoR) Memory Static RAM (SRAM) 256 KB (ECC) 384 KB (ECC) 512 KB (ECC) Code flash memory 1 MB2 (ECC) 1.5 MB2 (ECC) 2 MB2 (ECC) Data flash memory 64 KB2 (ECC) Modules Analog-to-Digital Converter (ADC) 257 pin pkg: 4 × 12 bit (22 external channels) 473 pin pkg: 4 × 12 bit (up to 34 external channels) CRC unit 2 (3 contexts each) Cross Triggering Unit (CTU) 2 modules Deserial Serial Peripheral Interface (DSPI) 2 modules (3 chip selects)3 3 modules4 Digital I/Os  16 DRAM Controller (DRAMC) No Yes5 Enhanced Direct Memory Access (eDMA) 2 modules, 32 channels each eTimer 3 modules, 6 channels each

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Introduction MPC5675K Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 3 Modules (cont.) External Bus Interface (EBI) 1 module5 16-bit Data + Address or 32-bit Data with Address bus muxed8 Fast Ethernet Controller (FEC) 1 module Fault Collection and Control Unit (FCCU) 1 module FlexCAN 4 modules (32 message buffers each) FlexPWM 3 modules (each 4 × 3 channels) FlexRay Optional I2C 2 modules6 3 modules Interrupt Controller (INTC) Yes (SoR) LINFlex 3 modules7 4 modules Parallel Data Interface (PDI) 1 module8 Periodic Interrupt Timer (PIT) 1 module, 4 channels Software Watchdog Timer (SWT) Yes (SoR) System Timer Module (STM) Yes (SoR) Temperature sensor 1 module Wakeup Unit (WKPU) Yes Crossbar switch (XBAR) 3 modules, 2 are user-configurable Clocking Clock monitor unit (CMU) 3 modules Frequency-modulated phase-locked loop (FMPLL) 2 modules (system and auxiliary) IRCOSC – 16 MHz 1 XOSC 4–40 MHz 1 Supply Power management unit (PMU) Yes 1.2 V low-voltage detector (LVD12) 1 1.2 V high-voltage detector (HVD12) 1 2.7 V low-voltage detector (LVD27) 4 Debug Nexus Class 3+ (for cores and SRAM ports) Table 1. MPC5675K family device comparison (continued) Features MPC5673K MPC5674K MPC5675K

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MPC5675K Microcontroller Data Sheet, Rev. 8 Introduction Freescale Semiconductor4 Packages MAPBGA 257 pins 473 pins Temperature Ambient See the TA recommended operating condition in the device data sheet 1 Sphere of Replication. 2 Does not include Test or Shadow Flash memory space. 3 DSPI_0 and DSPI_1. 4 DSPI_0 has 8 chip selects; DSPI_1 and DSPI_2 have 4 chip selects each. 5 Available only on 473-pin package. 6 Any two of the three I2C can be chosen. 7 LinFlex_0, LinFlex_1, and LinFlex_2. 8 DDR available only on 473 package. Other modules available as follows: EBI or DDR on 473 package EBI + PDI on 473 package DDR + PDI on 473 package PDI only on 257 package Table 1. MPC5675K family device comparison (continued) Features MPC5673K MPC5674K MPC5675K

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Introduction MPC5675K Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 5 1.4 Block diagram Figure 1 shows a top-level block diagram of the MPC5675K device. Figure 1. MPC5675K block diagram DMA_1 ADC – Analog-to-digital converter BAM – Boot assist module CMU – Clock monitoring unit CRC – Cyclic redundancy check unit CTU – Cross triggering unit DSPI – Deserial serial peripheral interface EBI – External bus interface ECC – Error correction code ECSM – Error correction status module eDMA – Enhanced direct memory access controller FCCU – Fault collection and control unit FEC – Fast Ethernet controller FlexCAN – Controller area network controller FlexPWM – Pulse width modulator module FMPLL – Frequency-modulated phase-locked loop I2C – Inter-integrated circuit controller INTC – Interrupt controller IRCOSC – Internal RC oscillator JTAG – Joint Test Action Group interface MC – Mode entry, clock, reset, and power modules mDDR – Mobile double data rate dynamic RAM PBRIDGE – Peripheral bridge PDI – Parallel data interface PIT – Periodic interrupt timer PMC – Power management controller RC – Redundancy checker RTC – Real time clock SEMA4 – Semaphore unit SIUL – System integration unit Lite SSCM – System status and configuration module STM – System timer module SWT – Software watchdog timer TSENS – Temperature sensor XOSC – Crystal oscillator ECSM_0 STM INTC Crossbar switch (XBAR_2) Crossbar switch (XBAR_1) Memory protection unit PBRIDGE Debug l PBRIDGE S IU L M C W ak eU p A D C A D C X O S C B A M S S C M S e co n d ar y P LL F M P LL IR C O S C C M U C M U C T U P IT F C C U F le xP W M F le xP W M eT im er eT im er eT im er F le xC A N F le xC A N LI N F le x LI N F le x D S P I D S P I D S P I C R C C M U SEMA4 T S E N S PDI A D C A D C C T U F le xP W M LI N F le x LI N F le x F le xC A N F le xC A N DDR Controller I2 C I2 C I2 C C R C DMA_0 Ethernet PFLASHC PFLASHC SRAM with ECC LogicSRAM with ECC Logic PBRIDGE SWT_0 Crossbar switch (XBAR_0) Memory protection unit PMC Redundancy Checker[6] Redundancy Checker[3] Redundancy Checker[4] Redundancy Checker[2] Redundancy Checker[5] Nexus JTAG Interface ECSM_1 STM INTC SEMA4 SWT_1 PMC External Bus 2MB Flash with ECC Logic D-CACHE e200z7d Core_1 I-CACHE VLE SPE2 MMU D-CACHE e200z7d Core_0 I-CACHE VLE SPE2 MMU Redundancy Checker[7] Redundancy Checker[0]

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MPC5675K Microcontroller Data Sheet, Rev. 8 Introduction Freescale Semiconductor6 1.5 Feature list • High-performance e200z7d dual core — 32-bit Power Architecture technology CPU — Up to 180 MHz core frequency — Dual-issue core — Variable length encoding (VLE) — Memory management unit (MMU) with 64 entries — 16 KB instruction cache and 16 KB data cache • Memory available — Up to 2 MB code flash memory with ECC — 64 KB data flash memory with ECC — Up to 512 KB on-chip SRAM with ECC • SIL3/ASILD innovative safety concept: LockStep mode and fail-safe protection — Sphere of replication (SoR) for key components — Redundancy checking units on outputs of the SoR connected to FCCU — Fault collection and control unit (FCCU) — Boot-time built-in self-test for memory (MBIST) and logic (LBIST) triggered by hardware — Boot-time built-in self-test for ADC and flash memory — Replicated safety-enhanced watchdog timer — Silicon substrate (die) temperature sensor — Non-maskable interrupt (NMI) — 16-region memory protection unit (MPU) — Clock monitoring units (CMU) — Power management unit (PMU) — Cyclic redundancy check (CRC) units • Decoupled Parallel mode for high-performance use of replicated cores • Nexus Class 3+ interface • Interrupts — Replicated 16-priority interrupt controller • GPIOs individually programmable as input, output, or special function • 3 general-purpose eTimer units (6 channels each) • 3 FlexPWM units with four 16-bit channels per module • Communications interfaces — 4 LINFlex modules — 3 DSPI modules with automatic chip select generation — 4 FlexCAN interfaces (2.0B Active) with 32 message objects — FlexRay module (V2.1) with dual channel, up to 128 message objects and up to 10 Mbit/s — Fast Ethernet Controller (FEC) — 3 I2C modules • Four 12-bit analog-to-digital converters (ADCs) — 22 input channels — Programmable cross triggering unit (CTU) to synchronize ADC conversion with timer and PWM • External bus interface • 16-bit external DDR memory controller • Parallel digital interface (PDI)

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Introduction MPC5675K Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 7 • On-chip CAN/UART bootstrap loader • Capable of operating on a single 3.3 V voltage supply — 3.3 V-only modules: I/O, oscillators, flash memory — 3.3 V or 5 V modules: ADCs, supply to internal VREG — 1.8–3.3 V supply range: DRAM/PDI • Operating junction temperature range –40 to 150 °C 1.6 Feature details 1.6.1 High-performance e200z7d core processor • Dual 32-bit Power Architecture processor core • Loose or tight core coupling • Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction • Thirty-two 64-bit general-purpose registers (GPRs) • Memory management unit (MMU) with 64-entry fully-associative translation look-aside buffer (TLB) • Branch processing unit • Fully pipelined load/store unit • 16 KB Instruction and 16 KB Data caches per core with line locking — Four way set associative — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data cache parity — Supports EDC for instruction cache • Vectored interrupt support • Signal processing engine 2 (SPE2) auxiliary processing unit (APU) operating on 64-bit general purpose registers • Floating point — IEEE 754 compatible with software wrapper — Single precision in hardware; double precision with software library — Conversion instructions between single precision floating point and fixed point • Long cycle time instructions (except for guarded loads) do not increase interrupt latency in the MPC5675K • To reduce latency, long cycle time instructions are aborted upon interrupt requests • Extensive system development support through Nexus debug module 1.6.2 Crossbar Switch (XBAR) • 32-bit address bus, 64-bit data bus • Simultaneous accesses from different masters to different slaves (there is no clock penalty when a parked master accesses a slave) 1.6.3 Memory Protection Unit (MPU) Each master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.

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MPC5675K Microcontroller Data Sheet, Rev. 8 Introduction Freescale Semiconductor8 • 16-region MPU with concurrent checks against each master access • 32-byte granularity for protected address region 1.6.4 Enhanced Direct Memory Access (eDMA) controller • 32 channels support independent 8-, 16-, 32-bit single value or block transfers • Supports variable-sized queues and circular queues • Source and destination address registers are independently configured to post-increment or remain constant • Each transfer is initiated by a peripheral, CPU, or eDMA channel request • Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer 1.6.5 Interrupt Controller (INTC) • 208 peripheral interrupt requests • 8 software settable sources • Unique 9-bit vector per interrupt source • 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source • Priority elevation for shared resources 1.6.6 Frequency-Modulated Phase-Locked Loop (FMPLL) Two FMPLLs are available on each device. Each FMPLL allows the user to generate high speed system clocks starting from a minimum reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor and output clock divider ratio are software configurable. The FMPLLs have the following major features: • Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator) • Voltage controlled oscillator (VCO) range: 256–512 MHz • Frequency modulation via software control to reduce and control emission peaks — Modulation depth ±2% if centered or 0% to –4% if downshifted via software control register — Modulation frequency: triangular modulation with 25 kHz nominal rate • Option to switch modulation on and off via software interface • Reduced frequency divider (RFD) for reduced frequency operation without re-lock • 2 modes of operation — Normal PLL mode with crystal reference (default) — Normal PLL mode with external reference • Lock monitor circuitry with lock status • Loss-of-lock detection for reference and feedback clocks • Self-clocked mode (SCM) operation • Auxiliary FMPLL — Used for FlexRay due to precise symbol rate requirement by the protocol — Used for motor control periphery and connected IP (A/D digital interface CTU) to allow independent frequencies of operation for PWM and timers as well as jitter-free control — Option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop — Allows running motor control periphery at different (precisely lower, equal, or higher, as required) frequency than the system to ensure higher resolution

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Introduction MPC5675K Microcontroller Data Sheet, Rev. 8 Freescale Semiconductor 9 1.6.7 External Bus Interface (EBI) • Available on 473-pin devices • Data and address options: — 16-bit data and address (non-muxed) — 32-bit data and address (bus-muxed) • MPC5561 324 BGA compatibility mode: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable to 26-bit address bus • Memory controller with support for various memory types — Non-burst and burst mode SDR flash and SRAM — Asynchronous/legacy flash and SRAM • Configurable bus speed modes • Support for 2 MB address space • Chip select and write/byte enable options as presented in the pin-muxing table in the “Signal Description” chapter of the MPC5675K reference manual • Configurable wait states (via chip selects) • Optional automatic CLKOUT gating to save power and reduce EMI 1.6.8 On-chip flash memory • Up to 2 MB code flash memory with ECC • 64 KB data flash memory with ECC • Censorship protection scheme to prevent flash content visibility • Multiple block sizes to support features such as boot block, operating system block, and EEPROM emulation • Read-while-write with multiple partitions • Parallel programming mode to support rapid end-of-line programming • Hardware programming state machine 1.6.9 Cache memory • Harvard architecture cache • 16 KB instruction / 16 KB data • Four-way set-associative Harvard (instruction and data) 256-bit long cache — Two 32-bit fetches per clock — Eight-entry store buffer — Way locking — Supports tag and data cache parity — Supports EDC for instruction cache 1.6.10 On-chip internal static RAM (SRAM) • Up to 512 KB general-purpose SRAM • ECC performs single-bit correction, double-bit error detection — Address included in ECC checkbase

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