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ST7FLITES5Y0B6

hot ST7FLITES5Y0B6

ST7FLITES5Y0B6

For Reference Only

Part Number ST7FLITES5Y0B6
Manufacturer STMicroelectronics
Description IC MCU 8BIT 1KB FLASH 16DIP
Datasheet ST7FLITES5Y0B6 Datasheet
Package 16-DIP (0.300", 7.62mm)
In Stock 701 piece(s)
Unit Price $ 1.1876 *
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ST7FLITES5Y0B6 Specifications

ManufacturerSTMicroelectronics
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet ST7FLITES5Y0B6 Datasheet
Package16-DIP (0.300", 7.62mm)
SeriesST7
Core ProcessorST7
Core Size8-Bit
Speed8MHz
ConnectivitySPI
PeripheralsLVD, POR, PWM, WDT
Number of I/O13
Program Memory Size1KB (1K x 8)
Program Memory TypeFLASH
RAM Size128 x 8
Voltage - Supply (Vcc/Vdd)2.4 V ~ 5.5 V
Data ConvertersA/D 5x10b
Oscillator TypeInternal
Operating Temperature-40°C ~ 85°C (TA)
Package / Case16-DIP (0.300", 7.62mm)

ST7FLITES5Y0B6 Datasheet

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ST7LITE0xY0, ST7LITESxY0 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI■ Memories – 1K or 1.5 Kbytes single voltage Flash Pro- gram memory with read-out protection, In-Cir- cuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, data retention: 20 years at 55 °C. – 128 bytes RAM. – 128 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C. ■ Clock, Reset and Supply Management – 3-level low voltage supervisor (LVD) and aux- iliary voltage detector (AVD) for safe power- on/off procedures – Clock sources: internal 1MHz RC 1% oscilla- tor or external clock – PLL x4 or x8 for 4 or 8 MHz internal clock – Four Power Saving Modes: Halt, Active-Halt, Wait and Slow ■ Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 4 external interrupt lines (on 4 vectors) ■ I/O Ports – 13 multifunctional bidirectional I/O lines – 9 alternate function lines – 6 high sink outputs ■ 2 Timers – One 8-bit Lite Timer (LT) with prescaler in- cluding: watchdog, 1 realtime base and 1 in- put capture. – One 12-bit Auto-reload Timer (AT) with output compare function and PWM ■ 1 Communication Interface – SPI synchronous serial interface ■ A/D Converter – 8-bit resolution for 0 to VDD – Fixed gain Op-amp for 11-bit resolution in 0 to 250 mV range (@ 5V VDD) – 5 input channels ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instruction ■ Development Tools – Full hardware/software development package Device Summary DIP16 SO16 150” QFN20 Features ST7LITESxY0 (ST7SUPERLITE) ST7LITE0xY0 ST7LITES2Y0 ST7LITES5Y0 ST7LITE02Y0 ST7LITE05Y0 ST7LITE09Y0 Program memory - bytes 1K 1K 1.5K 1.5K 1.5K RAM (stack) - bytes 128 (64) 128 (64) 128 (64) 128 (64) 128 (64) Data EEPROM - bytes - - - - 128 Peripherals LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI, 8-bit ADC LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI, 8-bit ADC w/ Op-Amp Operating Supply 2.4V to 5.5V CPU Frequency 1MHz RC 1% + PLLx4/8MHz Operating Temperature -40°C to +85°C Packages SO16 150”, DIP16, QFN20November 2007 Rev 61/124 1

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Table of Contents124 ST7LITE0xY0, ST7LITESxY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392/1242

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Table of Contents10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.3 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 LITE TIMER (LT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 12-BIT AUTORELOAD TIMER (AT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.4 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS . . . . . . . . . . . . . 93 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 102 13.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 112 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 114 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.1 EXECUTION OF BTJX INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD- WARE WATCHDOG OPTION 121 16.3 IN-CIRCUIT DEBUGGING WITH HARDWARE WATCHDOG . . . . . . . . . . . . . . . . . . . 121 16.4 RECOMMENDATIONS WHEN LVD IS ENABLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 16.5 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE . . . . . . . . . . . . 121 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223/124 3

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Table of ContentsTo obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121.4/124 1

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ST7LITE0xY0, ST7LITESxY01 DESCRIPTION The ST7LITE0x and ST7SUPERLITE (ST7LITESx) are members of the ST7 microcon- troller family. All ST7 devices are based on a com- mon industry-standard 8-bit core, featuring an en- hanced instruction set. The ST7LITE0x and ST7SUPERLITE feature FLASH memory with byte-by-byte In-Circuit Pro- gramming (ICP) and In-Application Programming (IAP) capability. Under software control, the ST7LITE0x and ST7SUPERLITE devices can be placed in WAIT, SLOW, or HALT mode, reducing power consump- tion when the application is in idle or standby state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 micro- controllers feature true bit manipulation, 8x8 un- signed multiplication and indirect addressing modes. For easy reference, all parametric data are located in section 13 on page 81. Figure 1. General Block Diagram 8-BIT CORE ALU A D D R E S S A N D D A T A B U S RESET PORT B PORT A SPI 8-BIT ADC w/ WATCHDOG PB4:0 (5 bits) 1 MHz. RC OSC Internal CLOCK CONTROL RAM (128 Bytes) PA7:0 (8 bits) VSS VDD POWER SUPPLY FLASH + PLL x 4 or x 8 LITE TIMER MEMORY DATA EEPROM (128 Bytes) 12-BIT AUTO- RELOAD TIMER LVD/AVD (1 or 1.5K Bytes)5/124 1

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ST7LITE0xY0, ST7LITESxY02 PIN DESCRIPTION Figure 2. 20-Pin QFN Package Pinout Figure 3. 16-Pin SO and DIP Package Pinout k 2 1 3 4 5 7 8 9 10 11 12 13 14 15 17181920 M O S I/ A IN 3 /P B 3 MISO/AIN2/PB2 NC NC NC C L K IN /A IN 4 /P B 4 RESET V D D P B 0 /S S /A IN 0 V S S P A 0 ( H S )/ L T IC PA5 (HS)/ICCDATA PA4 (HS) NC PA3 (HS) PA2 (HS)/ATPWM0 P A 7 M C O /I C C C L K /P A 6 (HS) 20mA High sink capability eix associated external interrupt vector ei1 6SCK/AIN1/PB1 ei2 16 PA1 (HS) e0e3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VSS VDD SS/AIN0/PB0 CLKIN/AIN4/PB4 MOSI/AIN3/PB3 MISO/AIN2/PB2 SCK/AIN1/PB1 RESET PA0 (HS)/LTIC PA1 (HS) PA7 PA6/MCO/ICCCLK PA5 (HS)/ICCDATA PA4 (HS) PA3 (HS) PA2 (HS)/ATPWM0 ei1 ei0 (HS) 20mA high sink capability eix associated external interrupt vector ei2 ei36/124 1

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ST7LITE0xY0, ST7LITESxY0PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply In/Output level: C= CMOS 0.15VDD/0.85VDD with input trigger CT= CMOS 0.3VDD/0.7VDD with input trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain, PP = push-pull Table 1. Device Pin Description Pin n° Pin Name T y p e Level Port / Control Main Function (after reset) Alternate Function Q F N 2 0 S O 1 6 /D IP 1 6 In p u t O u tp u t Input Output fl o a t w p u in t a n a O D P P 18 1 VSS S Ground 19 2 VDD S Main power supply 1 3 RESET I/O CT X X Top priority non maskable interrupt (active low) 20 4 PB0/AIN0/SS I/O CT X ei3 X X X Port B0 ADC Analog Input 0 or SPI Slave Select (active low) 6 5 PB1/AIN1/SCK I/O CT X X X X X Port B1 ADC Analog Input 1 or SPI Clock Caution: No negative current in- jection allowed on this pin. For details, refer to section 13.2.2 on page 82 5 6 PB2/AIN2/MISO I/O CT X X X X X Port B2 ADC Analog Input 2 or SPI Mas- ter In/ Slave Out Data 7 7 PB3/AIN3/MOSI I/O CT X ei2 X X X Port B3 ADC Analog Input 3 or SPI Mas- ter Out / Slave In Data 8 8 PB4/AIN4/CLKIN I/O CT X X X X X Port B4 ADC Analog Input 4 or External clock input 9 9 PA7 I/O CT X ei1 X X Port A7 10 10 PA6 /MCO/ ICCCLK I/O CT X X X X Port A6 Main Clock Output/In Circuit Communication Clock. Caution: During normal opera- tion this pin must be pulled- up, internally or externally (external pull-up of 10k mandatory in noisy environment). This is to avoid en- tering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up 11 11 PA5/ ICCDATA I/O CT HS X X X X Port A5 In Circuit Communication Data 12 12 PA4 I/O CT HS X X X X Port A4 14 13 PA3 I/O CT HS X X X X Port A37/124 1

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ST7LITE0xY0, ST7LITESxY0Note: In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up col- umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 15 14 PA2/ATPWM0 I/O CT HS X X X X Port A2 Auto-Reload Timer PWM0 16 15 PA1 I/O CT HS X X X X Port A1 17 16 PA0/LTIC I/O CT HS X ei0 X X Port A0 Lite Timer Input Capture Pin n° Pin Name T y p e Level Port / Control Main Function (after reset) Alternate Function Q F N 2 0 S O 1 6 /D IP 1 6 In p u t O u tp u t Input Output fl o a t w p u in t a n a O D P P 8/124 1

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ST7LITE0xY0, ST7LITESxY03 REGISTER & MEMORY MAP As shown in Figure 4 and Figure 5, the MCU is ca- pable of addressing 64K bytes of memories and I/ O registers. The available memory locations consist of up to 128 bytes of register locations, 128 bytes of RAM, 128 bytes of data EEPROM and up to 1.5 Kbytes of user program memory. The RAM space in- cludes up to 64 bytes for the stack from 0C0h to 0FFh. The highest address bytes contain the user reset and interrupt vectors. The size of Flash Sector 0 is configurable by Op- tion byte. IMPORTANT: Memory locations marked as “Re- served” must never be accessed. Accessing a re- served area can have unpredictable effects on the device. Figure 4. Memory Map (ST7LITE0x) 0000h RAM Flash Memory (1.5K) Interrupt & Reset Vectors HW Registers 0080h 007Fh 0FFFh (see Table 2) 1000h 107Fh FFE0h FFFFh (see Table 6) 0100h Reserved 00FFh Short Addressing RAM (zero page) 64 Bytes Stack 00C0h 00FFh 0080h 00BFh (128 Bytes) Data EEPROM (128 Bytes) FA00h 1080h F9FFh Reserved FFDFh 1 Kbytes 0.5 Kbytes SECTOR 1 SECTOR 0 1.5K FLASH FFFFh FC00h FBFFh FA00h PROGRAM MEMORY 1000h 1001h RCCR0 RCCR1 see section 7.1 on page 24 FFDEh FFDFh RCCR0 RCCR1 see section 7.1 on page 249/124 1

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