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TS80C31X2-MCB

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TS80C31X2-MCB

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Part Number TS80C31X2-MCB
Manufacturer Microchip Technology
Description IC MCU 8BIT ROMLESS 44PLCC
Datasheet TS80C31X2-MCB Datasheet
Package 44-LCC (J-Lead)
In Stock 30,148 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 12 - Jul 17 (Choose Expedited Shipping)
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Part Number # TS80C31X2-MCB (Embedded - Microcontrollers) is manufactured by Microchip Technology and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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TS80C31X2-MCB Specifications

ManufacturerMicrochip Technology
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet TS80C31X2-MCBDatasheet
Package44-LCC (J-Lead)
Series80C
Core Processor80C51
Core Size8-Bit
Speed40/20MHz
ConnectivityUART/USART
PeripheralsPOR
Number of I/O32
Program Memory Size-
Program Memory TypeROMless
EEPROM Size-
RAM Size128 x 8
Voltage - Supply (Vcc/Vdd)4.5 V ~ 5.5 V
Data Converters-
Oscillator TypeInternal
Operating Temperature0°C ~ 70°C (TA)
Mounting Type-
Package / Case44-LCC (J-Lead)
Supplier Device Package44-PLCC (16.59x16.59)

TS80C31X2-MCB Datasheet

Page 1

Page 2

TS80C31X28-bit CMOS Microcontroller ROMless 1. Description TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscilator and two timer/ counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features ● 80C31 Compatible • 8031 pin and instruction compatible • Four 8-bit I/O ports • Two 16-bit timer/counters • 128 bytes scratchpad RAM ● High-Speed Architecture • 40 MHz @ 5V, 30MHz @ 3V • X2 Speed Improvement capability (6 clocks/ machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) ● Dual Data Pointer ● Asynchronous port reset ● Interrupt Structure with • 5 Interrupt sources, • 4 priority level interrupt system ● Full duplex Enhanced UART • Framing error detection • Automatic address recognition ● Power Control modes • Idle mode • Power-down mode • Power-off Flag ● Once mode (On-chip Emulation) ● Power supply: 4.5-5.5V, 2.7-5.5V ● Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) ● Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1 (13.9 footprint)Rev. C - 15 January, 2001 1

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TS80C31X23. Block Diagram Timer 0 INT RAM 128x8 T 0 T 1 R x D T x D WR RD EA PSEN ALE/ XTAL2 XTAL1 EUART CPU Timer 1 IN T 1 Ctrl IN T 0 (1) (1) C51 CORE (1) (1) (1) (1) Port 0 P 0 Port 1 Port 2 Port 3 Parallel I/O Ports & Ext. Bus P 1 P 2 P 3 IB-bus R E S E T PROG (1)(1) (1): Alternate function of Port 32 Rev. C - 15 January, 2001

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Rev. C - 15 January, 2001 3 TS80C31X2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C31X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • Power and clock control registers: PCON • Interrupt system registers: IE, IP, IPH • Others: CKCON Table 1. All SFRs with their address and their reset value Bit address- able Non Bit addressable 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8h FFh F0h B 0000 0000 F7h E8h EFh E0h ACC 0000 0000 E7h D8h DFh D0h PSW 0000 0000 D7h C8h CFh C0h C7h B8h IP XXX0 0000 SADEN 0000 0000 BFh B0h P3 1111 1111 IPH XXX0 0000 B7h A8h IE 0XX0 0000 SADDR 0000 0000 AFh A0h P2 1111 1111 AUXR1 XXXX XXX0 A7h 98h SCON 0000 0000 SBUF XXXX XXXX 9Fh 90h P1 1111 1111 97h 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 TH0 0000 0000 TH1 0000 0000 CKCON XXXX XXX0 8Fh 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 PCON 00X1 0000 87h 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F reserved

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TS80C31X25. Pin Configuration 5 4 3 2 1 6 44 43 42 41 40 P 1 .4 P 1 .0 P 1 .1 P 1 .3 P 1 .2 V S S 1 /N IC * V C C P 0 .0 /A D 0 P 0 .2 /A D 2 P 0 .1 /A D 1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P 3 .6 /W R P 3 .7 /R D X T A L 2 X T A L 1 V S S P 2 .0 /A 8 P 2 .1 /A 9 P 2 .2 /A 1 0 P 2 .3 /A 1 1 P 2 .4 /A 1 2 43 42 41 40 3944 38 37 36 35 34 P 1 .4 P 1 .0 P 1 .1 P 1 .3 P 1 .2 V S S 1 /N IC * V C C P 0 .0 /A D 0 P 0 .2 /A D 2 P 0 .3 /A D 3 P 0 .1 /A D 1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE PSEN EA NIC* P2.7/A15 P2.5/A13 P2.6/A14 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P 3 .6 /W R P 3 .7 /R D X T A L 2 X T A L 1 V S S P 2 .0 /A 8 P 2 .1 /A 9 P 2 .2 /A 1 0 P 2 .3 /A 1 1 P 2 .4 /A 1 2 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P 0 .3 /A D 3 N IC * N IC * *NIC: No Internal Connection 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 33 32 31 30 29 28 27 26 25 24 23 PQFP44 1 2 3 4 5 6 7 8 9 10 11 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 VQFP44 P1.7 RST P3.0/RxD P3.1/TxD P1.3 1 P1.5 P3.2/INT0 P3.3/INT1 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P0.4 / A4 P0.6 / A6 P0.5 / A5 P0.7 / A7 ALE/PROG PSEN EA/VPP P2.7 / A15 P2.5 / A13 P2.6 / A14 P1.0 / T2 P1.1 / T2EX VCC P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 PDIL/ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 CDIL40 P1.6 P1.4 P1.2 P3.4/T04 Rev. C - 15 January, 2001

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TS80C31X2 Table 2. Pin Description for 40/44 pin packages MNEMONIC PIN NUMBER TYPE NAME AND FUNCTION DIL LCC VQFP 1.4 VSS 20 22 16 I Ground: 0V reference Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and power- down operation P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. P1.0-P1.7 1-8 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. ALE 30 33 27 O (I) Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 31 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifierRev. C - 15 January, 2001 5

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TS80C31X26. TS80C31X2 Enhanced Features In comparison to the original 80C31, the TS80C31X2 implements some new features, which are: • The X2 option. • The Dual Data Pointer. • The 4 level interrupt priority system. • The power-off flag. • The ONCE mode. • Enhanced UART 6.1 X2 Feature The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: ● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ● Save power consumption while keeping same CPU power (oscillator power saving). ● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. ● Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 6.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. Figure 1. Clock Generation Diagram XTAL1 2 CKCON reg X2 state machine: 6 clock cycles. CPU control FOSC FXTAL 0 1 XTAL1:26 Rev. C - 15 January, 2001

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TS80C31X2Figure 2. Mode Switching Waveforms The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. XTAL1:2 XTAL1 CPU clock X2 bit X2 ModeSTD Mode STD ModeRev. C - 15 January, 2001 7

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TS80C31X2 Table 3. CKCON Register CKCON - Clock Control Register (8Fh) Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).8 Rev. C - 15 January, 2001

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TS80C31X2 6.2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer External Data Memory AUXR1(A2H) DPS DPH(83H) DPL(82H) 07 DPTR0 DPTR1Rev. C - 15 January, 2001 9

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July 1, 2020

Very user friendly to find part and specs. Easy to deal with the transaction for different payment types. Thanks!

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June 11, 2020

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June 7, 2020

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May 29, 2020

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May 25, 2020

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May 19, 2020

Wish there were some documentation but I guess if you're buying you kinda should know.

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May 16, 2020

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