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USBLC6-2SC6

hotUSBLC6-2SC6

USBLC6-2SC6

For Reference Only

Part Number USBLC6-2SC6
Manufacturer STMicroelectronics
Description TVS DIODE 5.25VWM 17VC SOT23-6
Datasheet USBLC6-2SC6 Datasheet
Package SOT-23-6
In Stock 1,222,018 piece(s)
Unit Price $ 0.1403 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 1 - Dec 6 (Choose Expedited Shipping)
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Part Number # USBLC6-2SC6 (TVS - Diodes) is manufactured by STMicroelectronics and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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USBLC6-2SC6 Specifications

ManufacturerSTMicroelectronics
CategoryCircuit Protection - TVS - Diodes
Datasheet USBLC6-2SC6Datasheet
PackageSOT-23-6
SeriesUSB
TypeSteering (Rail to Rail)
Unidirectional Channels2
Bidirectional Channels-
Voltage - Reverse Standoff (Typ)5.25V
Voltage - Breakdown (Min)6V
Voltage - Clamping (Max) @ Ipp17V
Current - Peak Pulse (10/1000µs)5A (8/20µs)
Power - Peak Pulse-
Power Line ProtectionYes
ApplicationsEthernet
Capacitance @ Frequency-
Operating Temperature-40°C ~ 125°C (TJ)
Mounting TypeSurface Mount
Package / CaseSOT-23-6
Supplier Device PackageSOT-23-6

USBLC6-2SC6 Datasheet

Page 1

Page 2

October 2011 Doc ID 11265 Rev 5 1/14 14 USBLC6-2 Very low capacitance ESD protection Features ■ 2 data-line protection ■ Protects VBUS ■ Very low capacitance: 3.5 pF max. ■ Very low leakage current: 150 nA max. ■ SOT-666 and SOT23-6L packages ■ RoHS compliant Benefits ■ Very low capacitance between lines to GND for optimized data integrity and speed ■ Low PCB space consumption: 2.9 mm2 max for SOT-666 and 9 mm² max for SOT23-6L ■ Enhanced ESD protection: IEC 61000-4-2 level 4 compliance guaranteed at device level, hence greater immunity at system level ■ ESD protection of VBUS ■ High reliability offered by monolithic integration ■ Low leakage current for longer operation of battery powered devices ■ Fast response time ■ Consistent D+ / D- signal balance: – Very low capacitance matching tolerance I/O to GND = 0.015 pF – Compliant with USB 2.0 requirements Complies with the following standards: ■ IEC 61000-4-2 level 4: – 15 kV (air discharge) – 8 kV (contact discharge) Figure 1. Functional diagram (top view) Applications ■ USB 2.0 ports up to 480 Mb/s (high speed) ■ Compatible with USB 1.1 low and full speed ■ Ethernet port: 10/100 Mb/s ■ SIM card protection ■ Video line protection ■ Portable electronics Description The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet links and video lines. The very low line capacitance secures a high level of signal integrity without compromising in protecting sensitive chips against the most stringently characterized ESD strikes. SOT23-6L USBLC6-2SC6 SOT-666 USBLC6-2P6 1 6 2 5 3 4 I/O1 I/O1 GND VBUS I/O2 I/O2 www.st.com

Page 3

Characteristics USBLC6-2 2/14 Doc ID 11265 Rev 5 1 Characteristics Table 1. Absolute ratings Symbol Parameter Value Unit VPP Peak pulse voltage IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge MIL STD883G-Method 3015-7 15 15 25 kV Tstg Storage temperature range -55 to +150 °C Tj Operating junction temperature range -40 to +125 °C TL Lead solder temperature (10 seconds duration) 260 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter Test conditions Value Unit Min. Typ. Max. IRM Leakage current VRM = 5.25 V 10 150 nA VBR Breakdown voltage between VBUS and GND IR = 1 mA 6 V VF Forward voltage IF = 10 mA 1.1 V VCL Clamping voltage IPP = 1 A, 8/20 µs Any I/O pin to GND 12 V IPP = 5 A, 8/20 µs Any I/O pin to GND 17 V Ci/o-GND Capacitance between I/O and GND VR = 1.65 V 2.5 3.5 pF ΔCi/o-GND 0.015 Ci/o-i/o Capacitance between I/O VR = 1.65 V 1.2 1.7 pF ΔCi/o-i/o 0.04

Page 4

USBLC6-2 Characteristics Doc ID 11265 Rev 5 3/14 Figure 2. Capacitance versus voltage (typical values) Figure 3. Line capacitance versus frequency (typical values) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 C(pF) F=1MHz V =30mV T =25°C OSC RMS j C =I/O-I/Oj C =I/O-GNDO Data line voltage (V) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 1 10 100 1000 C(pF) V =30mV T =25°C OSC RMS j V =0V to 3.3VLINE F(MHz) Figure 4. Relative variation of leakage current versus junction temperature (typical values) Figure 5. Frequency response 1 10 100 25 50 75 100 125 T (°C)j V =5VBUS I [TRM j] / I [TRM j=25°C] 100.0k 1.0M 10.0M 100.0M 1.0G -20.00 -15.00 -10.00 -5.00 0.00 S21(dB) F(Hz)

Page 5

Technical information USBLC6-2 4/14 Doc ID 11265 Rev 5 2 Technical information 2.1 Surge protection The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow: VCL+ = VTRANSIL + VF for positive surges VCL- = - VF for negative surges with: VF = VT + Rd.Ip (VF forward drop voltage) / (VT forward drop threshold voltage) and VTRANSIL = VBR + Rd_TRANSIL.IP Calculation example We assume that the value of the dynamic resistance of the clamping diode is typically: Rd = 0.5 Ω and VT = 1.1 V We assume that the value of the dynamic resistance of the transil diode is typically: Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V For an IEC 61000-4-2 surge Level 4 (Contact Discharge: Vg = 8 kV, Rg = 330 Ω), VBUS = +5 V, and if in first approximation, we assume that: Ip = Vg / Rg = 24 A. So, we find: VCL+ = +31.2 V VCL- = -13 V Note: The calculations do not take into account phenomena due to parasitic inductances. 2.2 Surge protection application example If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GND plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances LVBUS, LI/O and LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to LI/O.dl/dt + LGND.dI/dt. The dI/dt is calculated as: dI/dt = Ip/tr = 24 A/ns The overvoltage due to the parasitic inductances is: LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: VCL+ = +31.2 + 144 + 144 = 319.2 V VCL- = -13.1 - 144 - 144 = -301.1 V

Page 6

USBLC6-2 Technical information Doc ID 11265 Rev 5 5/14 We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some recommendations have to be followed (see 2.3: How to ensure good ESD protection). Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout 2.3 How to ensure good ESD protection While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for layout consideration) VBUS LI/O LVBUS LGND LI/O LGND V pinCC VCL VF I/O pin VTRANSIL V + VTRANSIL F - VF VCL- t = 1 nsr t t t = 1 nsr VCL+ GND pin Data line Positive Surge Negative Surge ESD surge on data line di dt LI/O + LGND di dt di dt -LI/O - LGND di dt di dt V + = V + V + L + L surge > 0CL TRANSIL F I/O GND V = -V - L - L surge > 0CL- F I/O GND di dt di dt di dt di dt di dt Rd.IpVV BRTRANSIL += Figure 7. ESD behavior: layout optimization Figure 8. ESD behavior: measurement conditions Unsuitable layout Optimized layout 1 6 2 5 3 4 1 6 2 5 3 4 +5 V IN OUT TEST BOARD ESD SURGE U S B L C 6 -2 S C 6

Page 7

Technical information USBLC6-2 6/14 Doc ID 11265 Rev 5 Important: A good precaution to take is to put the protection device as close as possible to the disturbance source (generally the connector). 2.4 Crosstalk behavior 2.4.1 Crosstalk phenomenon Figure 11. Crosstalk phenomenon The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ). Figure 9. ESD response to IEC 61000-4-2 (+15 kV air discharge) Figure 10. ESD response to IEC 61000-4-2 (-15 kV air discharge) Vin Vout Vin Vout Line 1 Line 2 VG1 VG2 RG1 RG2 DRIVERS RL1 RL2 RECEIVERS α β+1 12VG1 VG2 α β+2 21VG2 VG1

Page 8

USBLC6-2 Technical information Doc ID 11265 Rev 5 7/14 Figure 12. Analog crosstalk measurements Figure 12. shows the measurement circuit for the analog application. In usual frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see Figure 13.). Figure 13. Analog crosstalk results As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The frequency response (Figure 5.) gives attenuation information and shows that the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable signals like GSM (900 MHz) frequencies, for instance. NETWORK ANALYSER PORT 2NETWORK ANALYSER PORT 1 TEST BOARD Vbus U S B L C 6 -2 S C 6 100.0k 1.0M 10.0M 100.0M 1.0G - 120.00 - 90.00 - 60.00 - 30.00 0.00 dB F (Hz)

Page 9

Technical information USBLC6-2 8/14 Doc ID 11265 Rev 5 2.5 Application examples Figure 14. USB 2.0 port application diagram using USBLC6-2 Figure 15. T1/E1/Ethernet protection HUB- DOWNSTREAM TRANSCEIVER + 5V RS RS RS RS RPD RPD RPD RPD Protecting Bus Switch DEVICE- UPSTREAM TRANSCEIVER + 3.3V SW1 RPU VBUS D+ D- GND VBUS VBUS VBUS RX LS/FS + RX LS/FS + RX LS/FS +RX LS/FS + RX HS + RX HS + RX HS +RX HS + TX HS + TX HS + TX HS +TX HS + TX LS/FS + TX LS/FS + TX LS/FS +TX LS/FS + RS RS USB connector TX LS/FS - TX LS/FS - TX LS/FS -TX LS/FS - RX LS/FS - RX LS/FS - RX LS/FS -RX LS/FS - RX HS - RX HS - RX HS -RX HS - TX HS - TX HS - TX HS -TX HS - GND GND GNDGND SW2 DEVICE- UPSTREAM TRANSCEIVER USBLC6-4SC6 USBLC6-2P6 USBLC6-2SC6 + 3.3V SW1 RPU VBUS D+ D- GNDRS RS USB connectorSW2 OpenClosed then openHigh Speed HS OpenClosedFull Speed FS ClosedOpenLow Speed LS SW2SW1Mode DATA TRANSCEIVER SMP75-8 SMP75-8 Tx Rx +VCC +VCC 100nF 100nF U S B L C 6 -2 S C 6 U S B L C 6 -2 S C 6

Page 10

USBLC6-2 Technical information Doc ID 11265 Rev 5 9/14 2.6 PSpice model Figure 16. shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by the PSpice parameters given in Figure 17. Figure 16. PSpice model Note: This simulation model is available only for an ambient temperature of 27 °C. MODEL = Dlow MODEL = Dhigh VBUS LI/O LGND GND D+in MODEL = Dzener RI/O LI/O D-in RI/O LI/O LI/O RGND RI/O D-out RI/O MODEL = Dlow MODEL = Dhigh LI/O D+out RI/O Figure 17. PSpice parameters Figure 18. USBLC6-2 PCB layout considerations Dlow Dhigh Dzener BV 50 50 7.3 CJ0 0.9p 2.0p 40p IBV 1m 1m 1m M 0.3333 0.3333 0.3333 RS 0.2 0.52 0.84 VJ 0.6 0.6 0.6 TT 0.1u 0.1u 0.1u LI/O 750p RI/O 110m LGND 550p RGND 60m D+in D+out D-out GND USBLC6-2 D-in VBUS 1 C = 100nFBUS

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Leo*****Batta

November 16, 2020

Good quality, buy back and then use, with the newly bought hard disk, very stable, at any time you can check things, not occupy space, very convenient.

Lou*****Carey

November 15, 2020

Your technical assistance and professionalism cannot be complained!

Caleb*****nguez

November 3, 2020

Well packaged and good condition with the parts, arrived on time, good customer service.

Chas*****hmitt

November 2, 2020

Very pleased purchasing experience, would definitely buy again.

Ray*****Heath

October 28, 2020

Great kit, cost half the price of other stores. Includes most items that someone would need.

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