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W78L052C24DL

hot W78L052C24DL

W78L052C24DL

For Reference Only

Part Number W78L052C24DL
Manufacturer Nuvoton Technology Corporation of America
Description IC MCU 8BIT 8KB FLASH 40DIP
Datasheet W78L052C24DL Datasheet
Package 40-DIP
In Stock 360 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Feb 23 - Feb 28 (Choose Expedited Shipping)
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W78L052C24DL

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W78L052C24DL Specifications

ManufacturerNuvoton Technology Corporation of America
CategoryIntegrated Circuits (ICs) - Embedded - Microcontrollers
Datasheet W78L052C24DL Datasheet
Package40-DIP
SeriesW78
Core Processor8051
Core Size8-Bit
Speed24MHz
ConnectivityEBI/EMI, UART/USART
PeripheralsPOR, WDT
Number of I/O32
Program Memory Size8KB (8K x 8)
Program Memory TypeFLASH
RAM Size256 x 8
Voltage - Supply (Vcc/Vdd)2.4 V ~ 5.5 V
Oscillator TypeInternal
Operating Temperature0°C ~ 70°C (TA)
Package / Case40-DIP

W78L052C24DL Datasheet

Page 1

Page 2

W78LE52C/W78L052C 8-BIT MICROCONTROLLER Publication Release Date: April 17, 2007 - 1 - Revision A4 Table of Contents- 1. GENERAL DESCRIPTION ......................................................................................................... 2 2. FEATURES ................................................................................................................................. 2 3. PIN CONFIGURATIONS ............................................................................................................ 3 4. PIN DESCRIPTION..................................................................................................................... 4 5. FUNCTIONAL DESCRIPTION ................................................................................................... 5 6. ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 10 7. SECURITY BITS ....................................................................................................................... 10 8. ABSOLUTE MAXIMUM RATINGS ........................................................................................... 11 9. DC CHARACTERISTICS.......................................................................................................... 12 10. AC CHARACTERISTICS .......................................................................................................... 14 11. TIMING WAVEFORMS............................................................................................................. 17 12. TYPICAL APPLICATION CIRCUITS ........................................................................................ 19 13. PACKAGE DIMENSIONS......................................................................................................... 21 14. REVISION HISTORY................................................................................................................ 23

Page 3

W78LE52C/W78L052C - 2 - 1. GENERAL DESCRIPTION The W78L052C is an 8-bit microcontroller which can accommodate a wider frequency range with low power consumption. The instruction set for the W78L052C is fully compatible with the standard 8051. The W78L052C contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78L052C allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78L052C microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES • Fully static design 8-bit CMOS microcontroller • Wide supply voltage of 2.4V to 5.5V • 256 bytes of on-chip scratchpad RAM • 8 KB electrically erasable/programmable Flash EPROM • 64 KB program memory address space • 64 KB data memory address space • Four 8-bit bi-directional ports • One extra 4-bit bit-addressable I/O port, additional INT2 / INT3 (available on 44-pin PLCC/QFP package) • Three 16-bit timer/counters • One full duplex serial port(UART) • Watchdog Timer • Eight sources, two-level interrupt capability • EMI reduction mode • Built-in power management • Code protection mechanism • Packages: − Lead Free (RoHS) DIP 40: W78L052C24DL − Lead Free (RoHS) PLCC 44: W78L052C24PL − Lead Free (RoHS) PQFP 44: W78L052C24FL

Page 4

W78LE52C/W78L052C Publication Release Date: April 17, 2007 - 3 - Revision A4 3. PIN CONFIGURATIONS

Page 5

W78LE52C/W78L052C - 4 - 4. PIN DESCRIPTION SYMBOL DESCRIPTIONS EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external ROM. It should be kept high to access internal ROM. The ROM address and data will not be presented on the bus if EA pin is high and the program counter is within on-chip ROM area. PSEN PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0 address/ data bus during fetch and MOVC operations. When internal ROM access is performed, no PSEN strobe signal outputs from this pin. ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. RST RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS GROUND: Ground potential VDD POWER SUPPLY: Supply voltage for operation. P0.0−P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory. The Port 0 is also an open-drain port and external pull-ups need to be connected while in programming. P1.0−P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate functions which are described below: T2(P1.0): Timer/Counter 2 external count input T2EX(P1.1): Timer/Counter 2 Reload/Capture control P2.0−P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate functions, which are described below: RXD(P3.0) : Serial Port receiver input TXD(P3.1) : Serial Port transmitter output INT0 (P3.2) : External Interrupt 0 P3.0−P3.7 INT1(P3.3) : External Interrupt 1 T0(P3.4) : Timer 0 External Input T1(P3.5) : Timer 1 External Input WR (P3.6) :External Data Memory Write Strobe RD (P3.7) : External Data Memory Read Strobe P4.0−P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can be used as general I/O port or external interrupt input sources (INT2 /INT3 ).

Page 6

W78LE52C/W78L052C Publication Release Date: April 17, 2007 - 5 - Revision A4 5. FUNCTIONAL DESCRIPTION The W78L052C architecture consists of a core controller surrounded by various registers, five general purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. Timers 0, 1, and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of the W78L052C: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto- reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. New Defined Peripheral In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows: 1. INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Page 7

W78LE52C/W78L052C - 6 - Eight-source interrupt informations: INTERRUPT SOURCE VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.5 - External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3 2. PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are alternative function pins. It can be used as general I/O pins or external interrupt input sources ( INT2 , INT3 ). Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0−P4.3. MOV A, P4 ; Read P4 status to Accumulator. ORL P4.#00000001B ; Set P4.0 to be high state. ANL P4.#11111110B : Clear P4.0 to be low state. 3. Reduce EMI Emission Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space. The AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation circuitry, W78L052C allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 20MHz. The value of R and C1, C2 may need some adjustment while running at lower gain.

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W78LE52C/W78L052C Publication Release Date: April 17, 2007 - 7 - Revision A4 ***AUXR - Auxiliary register (8EH) - - - - - - - AO AO: Turn off ALE output. 4. Power-off Flag ***PCON - Power control (87H) - - - POF GF1 GF0 PD IDL POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software to determine chip reset is a warm boot or cold boot. GF1, GF0: These two bits are general-purpose flag bits for the user. PD: Power down mode bit. Set it to enter power down mode. IDL: Idle mode bit. Set it to enter idle mode. The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system clock. The divider output is selectable and determines the time-out interval. When the time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system monitor. This is important in real-time control applications. In case of power glitches or electro- magnetic interference, the processor may begin to execute errant code. If this is left unchecked the entire system may crash. The watchdog time-out selection will result in different time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are discussed below. Watchdog Timer Control Register Bit: 7 6 5 4 3 2 1 0 ENW CLRW WIDL - - PS2 PS1 PS0 Mnemonic: WDTC Address: 8FH ENW : Enable watch-dog if set. CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under IDLE mode. Default is cleared. PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows:

Page 9

W78LE52C/W78L052C - 8 - PS2 PS1 PS0 PRESCALER SELECT 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 The time-out period is obtained using the following equation: 1 OSC 2 PRESCALER 1000 12 mS14× × × × Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6 (CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next instruction cycle. The Watchdog timer is cleared on reset. OSC 1/12 PRESCALER 14-BIT TIMER CLEAR CLRW EXTERNAL RESET INTERNAL RESET WIDL IDLE ENW Watchdog Timer Block Diagram Typical Watch-Dog time-out period when OSC = 20 MHz PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD 0 0 0 19.66 mS 0 1 0 39.32 mS 0 0 1 78.64 mS 0 1 1 157.28 mS 1 0 0 314.57 mS 1 0 1 629.14 mS 1 1 0 1.25 S 1 1 1 2.50 S

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W78LE52C/W78L052C Publication Release Date: April 17, 2007 - 9 - Revision A4 Clock The W78L052C is designed to be used with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used. This makes the W78L052C relatively insensitive to duty cycle variations in the clock. The W78L052C incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. Power Management Idle Mode The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a reset. Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L052C is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

W78L052C24DL Reviews

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5 / 5 (85)
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76
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Cohe*****itney

November 29, 2019

Diodes okay. Shipped quick and received with well - packed

Myle*****charia

September 3, 2019

DELIVERY AND COMMUNICATION EXTRA SELLER TOP 5 STARS on my list

Ann*****Nagy

August 28, 2019

very pleased with item, thank you.

Ma*****Tank

August 14, 2019

The order process is easy and user friendly, very helpful customer service, always fast shipping.

Aubre*****ormick

July 3, 2019

This help solved the extra electricity flowing back.

Katali*****xander

July 1, 2019

Received the parts, and all parts are in tight packaging without any problems, professional seller.

West*****Vora

June 10, 2019

These are great for projects with the kids or doing any type of DIY projects. The case is nice to keep everything separated. Very nice.

Fin*****ahal

May 26, 2019

You're my good supplier. I appreciate Heisener Electronics on many levels.

Har***** Bedi

January 30, 2019

These did exactly what I needed them to do. Electricity only flows in one direction. Perfect.

Ivan*****arajan

January 29, 2019

Tested one of them and works good.

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