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X1288V14-2.7

hot X1288V14-2.7

X1288V14-2.7

For Reference Only

Part Number X1288V14-2.7
Manufacturer Intersil
Description IC RTC CLK/CALENDAR I2C 14-TSSOP
Datasheet X1288V14-2.7 Datasheet
Package 14-TSSOP (0.173", 4.40mm Width)
In Stock 1153 piece(s)
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X1288V14-2.7

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X1288V14-2.7 Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Clock/Timing - Real Time Clocks
Datasheet X1288V14-2.7 Datasheet
Package14-TSSOP (0.173", 4.40mm Width)
Series-
TypeClock/Calendar
FeaturesAlarm, Leap Year, Supervisor, Watchdog Timer
Time FormatHH:MM:SS:hh (12/24 hr)
Date FormatYY-MM-DD-dd
InterfaceI2C, 2-Wire Serial
Voltage - Supply2.7 V ~ 5.5 V
Voltage - Supply, Battery1.8 V ~ 5.5 V
Current - Timekeeping (Max)10µA ~ 20µA @ 2.7V ~ 5V
Operating Temperature0°C ~ 70°C
Mounting TypeSurface Mount
Package / Case14-TSSOP (0.173", 4.40mm Width)
Supplier Device Package14-TSSOP

X1288V14-2.7 Datasheet

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FN8102 Rev 3.00 April 14, 2006 X1288 2-Wire™ RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM DATASHEETFEATURES • Real Time Clock/Calendar — Tracks time in Hours, Minutes, Seconds and Hundredths of a Second — Day of the Week, Day, Month, and Year • 2 Polled Alarms (Non-volatile) — Settable on the Second, Minute, Hour, Day of the Week, Day, or Month — Repeat Mode (periodic interrupts) • Oscillator Compensation on Chip — Internal feedback resistor and compensation capacitors — 64 position Digitally Controlled Trim Capacitor — 6 digital-frequency adjustment setting to ±30ppm • CPU Supervisor Functions — Power-on Reset, Low Voltage Sense — Watchdog Timer (SW Selectable: 0.25s, 0.75s, 1.75s, off) • Battery Switch or Super Cap Input • 32K x 8 Bits of EEPROM — 128-Byte Page Write Mode — 8 modes of Block Lock™ Protection — Single Byte Write Capability • High Reliability —Data Retention: 100 years —Endurance: 100,000 cycles per byte • 2-Wire™ Interface interoperable with I2C* — 400kHz data transfer rate • Frequency Output (SW Selectable: Off, 1Hz, 100Hz, or 32.768kHz) • Low Power CMOS — 1.25µA Operating Current (Typical) • Small Package Options — 16-Lead SOIC and 14-Lead TSSOP • Pb-Free Plus Anneal Available (RoHS Compliant) APPLICATIONS • Utility Meters • HVAC Equipment • Audio/Video Components • Set Top Box/Television • Modems • Network Routers, Hubs, Switches, Bridges • Cellular Infrastructure Equipment • Fixed Broadband Wireless Equipment • Pagers/PDA • POS Equipment • Test Meters/Fixtures • Office Automation (Copiers, Fax) • Home Appliances • Computer Products • Other Industrial/Medical/Automotive BLOCK DIAGRAM X1 X2 Oscillator Frequency Timer Logic Divider Calendar 8 Control/ Registers 1Hz Time Keeping Registers Alarm Regs Compare M as k RESET Control Decode Logic Alarm (EEPROM) (EEPROM) SCL SDA Serial Interface Decoder 256K EEPROM ARRAYWatchdog Timer Low Voltage Reset Registers Status (SRAM) SelectPHZ/IRQ VCC VBACK 32.768kHz (SRAM) Battery Circuitry Switch OSC CompensationFN8102 Rev 3.00 Page 1 of 27 April 14, 2006

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X1288PIN DESCRIPTIONS X1 X2 VBACK VCC NC PHZ/IRQ NC VSS 1 2 3 4 13 14 12 11 14 Ld TSSOP NC NC SCL NC RESET SDA 5 6 7 9 10 8 16 Ld SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X1 X2 NC VSS NC NC RESET NC VBACK VCC PHZ/IRQ NC SCL NC SDA NC NC = No internal connection Ordering Information PART NUMBER PART MARKING VCC RANGE (V) VTRIP RANGE OPERATING TEMP RANGE (°C) PACKAGE X1288S16-4.5A* X1288S AL 4.5 to 5.5 4.63V±112mV 0 to 70 16 Ld SOIC X1288S16I-4.5A* X1288S AM -40 to +85 16 Ld SOIC X1288V14-4.5A* X1288V AL 0 to 70 14 Ld TSSOP X1288V14Z-4.5A* (Note) X1288V ZAL 0 to 70 14 Ld TSSOP (Pb-free) X1288V14I-4.5A* X1288V AM -40 to +85 14 Ld TSSOP X1288V14IZ-4.5A* (Note) X1288V ZAM -40 to +85 14 Ld TSSOP (Pb-free) X1288S16* X1288S 4.38V±112mV 0 to 70 16 Ld SOIC X1288S16I* X1288S I -40 to +85 16 Ld SOIC X1288V14* X1288V 0 to 70 14 Ld TSSOP X1288V14Z* (Note) X1288V Z 0 to 70 14 Ld TSSOP (Pb-free) X1288V14I* X1288V I -40 to +85 14 Ld TSSOP X1288V14IZ* (Note) X1288V ZI -40 to +85 14 Ld TSSOP (Pb-free) X1288S16-2.7A* X1288S AN 2.7 to 5.5 2.85V±100mV 0 to 70 16 Ld SOIC X1288S16I-2.7A* X1288S AP -40 to +85 16 Ld SOIC X1288V14-2.7A* X1288V AN 0 to 70 14 Ld TSSOP X1288V14Z-2.7A* (Note) X1288V ZAN 0 to 70 14 Ld TSSOP (Pb-free) X1288V14I-2.7A* X1288V AP -40 to +85 14 Ld TSSOP X1288V14IZ-2.7A* (Note) X1288V ZAP -40 to +85 14 Ld TSSOP (Pb-free) X1288S16-2.7* X1288S F 2.65V±100mV 0 to 70 16 Ld SOIC X1288S16I-2.7* X1288S G -40 to +85 16 Ld SOIC X1288V14-2.7* X1288V F 0 to 70 14 Ld TSSOP X1288V14Z-2.7* (Note) X1288V ZF 0 to 70 14 Ld TSSOP (Pb-free) X1288V14I-2.7* X1288V G -40 to +85 14 Ld TSSOP X1288V14IZ-2.7* (Note) X1288V ZG -40 to +85 14 Ld TSSOP (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN8102 Rev 3.00 Page 2 of 27 April 14, 2006

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X1288PIN ASSIGNMENTS Pin Number Symbol Brief DescriptionSOIC TSSOP 1 1 X1 X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1288 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X1 are highly recommended. See Application section for more information. 2 2 X2 X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1288 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X2 are highly recommended. See Application section for more information. 7 6 RESET RESET Output – RESET. This is a reset signal output. This signal notifies a host processor that the watchdog time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pullup resistor is 5k. If unused, tie to ground. 8 7 VSS VSS. 9 8 SDA Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz 2-wire interface speed. 10 9 SCL Serial Clock (SCL). The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). 14 12 PHZ/IRQ Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from the internal oscillator or an interrupt signal output. It is a CMOS output. When used as frequency output, this signal has a frequency of 32.768kHz, 100Hz, 1Hz or inactive. When used as interrupt output, this signal notifies a host processor that an alarm has occurred and an action is required. It is an active LOW output. The control bits for this function are FO1 and FO0 and are found in address 0011h of the Clock Control Memory map. See “Programmable Frequency Output Bits - FO1, FO0” on page 13. 15 13 VBACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. 16 14 VCC VCC.FN8102 Rev 3.00 Page 3 of 27 April 14, 2006

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X1288ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ................... -65°C to +135°C Storage Temperature ........................ -65°C to +150°C Voltage on VCC, VBACK and PHZ/IRQ pin (respect to ground) ............................-0.5V to 7.0V Voltage on SCL, SDA, X1 and X2 pin (respect to ground) ............... -0.5V to 7.0V or 0.5V above VCC or VBACK (whichever is higher) DC Output Current .............................................. 5 mA Lead Temperature (Soldering, 10 sec).............. 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifi- cation is not implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.) OPERATING CHARACTERISTICS Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address Byte are incorrect or until 200nS after a stop ending a read or write operation. (2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC. Symbol Parameter Conditions Min Typ Max Unit Notes VCC Main Power Supply 2.7 5.5 V VBACK Backup Power Supply 1.8 5.5 V VCB Switch to Backup Supply VBACK -0.2 VBACK -0.1 V VBC Switch to Main Supply VBACK VBACK +0.2 V Symbol Parameter Conditions Min Typ Max Unit Notes ICC1 Read Active Supply Current VCC = 2.7V 400 µA 1, 5, 7, 14 VCC = 5.0V 800 µA ICC2 Program Supply Current (nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14 VCC = 5.0V 3.0 mA ICC3 Main Timekeeping Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15 VCC = 5.0V 20 µA IBACK Timekeeping Current – (Low Voltage Sense and Watchdog Timer disabled VBACK = 1.8V 1.25 µA 3, 6, 9, 14, 15 “See Perfor- mance Data”VBACK = 3.3V 1.5 µA ILI Input Leakage Current 10 µA 10 ILO Output Leakage Current 10 µA 10 VIL Input LOW Voltage -0.5 VCC x 0.2 or VBACK x 0.2 V 13 VIH Input HIGH Voltage VCC x 0.7 or VBACK x 0.7 VCC + 0.5 or VBACK + 0.5 V 13 VHYS Schmitt Trigger Input Hysteresis VCC related level .05 x VCC or .05 x VBACK V 13 VOL1 Output LOW Voltage for SDA and RESET VCC = 2.7V 0.4 V 11 VCC = 5.5V 0.4 VOL2 Output LOW Voltage for PHZ/IRQ VCC = 2.7V VCC x 0.3 V 11 VCC = 5.5V VCC x 0.3 VOH2 Output HIGH Voltage for PHZ/IRQ VCC = 2.7V VCC x 0.7 V 12 VCC = 5.5V VCC x 0.7FN8102 Rev 3.00 Page 4 of 27 April 14, 2006

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X1288(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (4) For reference only and not tested. (5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz (6) VCC = 0V (7) VBACK = 0V (8) VSDA = VSCL=VCC, Others = GND or VCC (9) VSDA =VSCL=VBACK, Others = GND or VBACK (10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC (11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V (12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V (13) Threshold voltages based on the higher of Vcc or Vback. (14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C). (15) Typical values are for TA = 25°C Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V Notes: (1) This parameter is not 100% tested. (2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers AC CHARACTERISTICS AC Test Conditions Symbol Parameter Max. Units Test Conditions COUT(1) Output Capacitance (SDA, PHZ/IRQ, RESET) 10 pF VOUT = 0V CIN(1) Input Capacitance (SCL) 10 pF VIN = 0V Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Levels VCC x 0.5 Output Load Standard Output Load SDA 1533 100pF 5.0V For VOL= 0.4V and IOL = 3 mA Equivalent AC Output Load Circuit for VCC = 5V 1316 5.0V PHZ/IRQ 100pF806 FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH VCC = 5.0VFN8102 Rev 3.00 Page 5 of 27 April 14, 2006

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X1288AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.) Notes: (1) This parameter is not 100% tested. (2) Cb = total capacitance of one bus line in pF. TIMING DIAGRAMS Bus Timing Write Cycle Timing Symbol Parameter Min. Max. Units fSCL SCL Clock Frequency 400 kHz tIN Pulse width Suppression Time at inputs 50(1) ns tAA SCL LOW to SDA Data Out Valid 0.9 s tBUF Time the bus must be free before a new transmission can start 1.3 s tLOW Clock LOW Time 1.3 s tHIGH Clock HIGH Time 0.6 s tSU:STA Start Condition Setup Time 0.6 s tHD:STA Start Condition Hold Time 0.6 s tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 s tSU:STO Stop Condition Setup Time 0.6 s tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 +.1Cb(1)(2) 300 ns tF SDA and SCL Fall Time 20 +.1Cb(1)(2) 300 ns Cb Capacitive load for each bus line 400 pF tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR SCL SDA tWC 8th Bit of Last Byte ACK Stop Condition Start ConditionFN8102 Rev 3.00 Page 6 of 27 April 14, 2006

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X1288Power-up Timing Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec. (2) Typical values are for TA = 25°C and VCC = 5.0V Nonvolatile Write Cycle Timing Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS Watchdog/Low Voltage Reset Parameters (See Figures 3 and 4) Symbol Parameter Min. Typ.(2) Max. Units tPUR(1) Time from Power-up to Read 1 ms tPUW(1) Time from Power-up to Write 5 ms Symbol Parameter Min. Typ.(1) Max. Units tWC(1) Write Cycle Time 5 10 ms Symbols Parameters Min. Typ. Max. Unit VPTRIP Programmed Reset Trip Voltage X1288-4.5A X1288 X1288-2.7A X1288-2.7 4.50 4.25 2.75 2.55 4.63 4.38 2.85 2.65 4.75 4.50 2.95 2.75 V tRPD VCC Detect to RESET LOW 500 ns tPURST Power-up Reset Time-out Delay 100 250 400 ms tF VCC Fall Time 10 µs tR VCC Rise Time 10 µs tWDO Watchdog Timer Period (Crystal=32.768kHz): WD1=0, WD0=0, (default) WD1=0, WD0=1 WD1=1, WD0=0 1.7 725 225 1.75 750 250 1.8 775 275 s ms ms tRST Watchdog Reset Time-out Delay (Crystal=32.768kHz) 225 250 275 ms tRSP 2-Wire interface 1 µs VRVALID Reset Valid VCC 1.0 VFN8102 Rev 3.00 Page 7 of 27 April 14, 2006

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X1288VTRIP Programming Timing Diagram VTRIP Programming Parameters DESCRIPTION The X1288 device is a Real Time Clock with clock/calendar, two polled alarms with integrated 32kx8 EEPROM, oscillator compensation, CPU Supervisor (POR/LVS and WDT) and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are integrated on the chip. This eliminates several external discrete components and a trim capacitor, saving board area and component cost. The Real-Time Clock keeps track of time with separate registers for Hours, Minutes, Seconds and 1/100 of a second. The Calendar has separate registers for Date, Month, Year and Day-of-week. The calendar is correct through 2099, with automatic leap year correction. The powerful Dual Alarms can be set to any Clock/Calendar value for a match. For instance, every minute, every Tuesday, or 5:23 AM on March 21. The alarms can be polled in the Status Register or provide a hardware interrupt (IRQ Pin). There is a repeat mode for the alarms allowing a periodic interrupt. The PHZ/IRQ pin may be software selected to provide a frequency output of 1 Hz, 100 Hz, or 32,768 Hz. The X1288 device integrates CPU Supervisor func-tions and a Battery Switch. There is a Power-On Reset (RESET output) with typically 250 ms delay from power-on. It will also assert RESET when Vcc goes below the specified threshold. The Vtrip threshold is user repro-grammable. There is a WatchDog Timer (WDT) with 3 selectable time- out periods (0.25s, 0.75s, 1.75s) and a disabled setting. The watchdog activates the RESET pin when it expires. Parameter Description Min. Max. Units tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 14 16 V VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V Vtv VTRIP Program variation after programming (Programmed at 25°C) -25 +25 mV VTRIP programming parameters are not 100% Tested. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VCC (VTRIP) tVPHtVPS tVPO tRP SCL SDA AEh 03h/01h RESET VP = 15V 00h00h VCC VCC tTSU tTHD VTRIPFN8102 Rev 3.00 Page 8 of 27 April 14, 2006

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X1288The device offers a backup power input pin. This VBACK pin allows the device to be backed up by battery or SuperCap. The entire X1288 device is fully operational from 2.7 to 5.5 volts and the clock/calendar portion of the X1288 device remains fully operational down to 1.8 volts (Standby Mode). The X1288 device provides 256K bits of EEPROM with 8 modes of BlockLock™ control. The BlockLock allows a safe, secure memory for critical user and configuration data, while allowing a large user storage area. PIN DESCRIPTIONS Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. The input buffer on this pin is always active (not gated). Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. The input buffer is always active (not gated). An open drain output requires the use of a pull-up resistor. The output circuitry controls the fall time of the output signal with the use of a slope controlled pull-down. The circuit is designed for 400kHz 2-wire interface speed. VBACK This input provides a backup supply voltage to the device. VBACK supplies power to the device in the event the VCC supply fails. This pin can be connected to a battery, a Supercap or tied to ground if not used. RESET Output – RESET This is a reset signal output. This signal notifies a host pro- cessor that the watchdog time period has expired or that the voltage has dropped below a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the pullup resistor is 5k. If unused, tie to ground. Programmable Frequency/Interrupt Output – PHZ/IRQ This is either an output from the internal oscillator or an interrupt signal output. It is a CMOS output. When used as frequency output, this signal has a fre- quency of 32.768kHz, 100Hz, 1Hz or inactive. When used as interrupt output, this signal notifies a host processor that an alarm has occurred and an action is required. It is an active LOW output. The control bits for this function are FO1 and FO0 and are found in address 0011h of the Clock Control Memory map. See “Programmable Frequency Output Bits - FO1, FO0” on page 13. X1, X2 The X1 and X2 pins are the input and output, respectively, of an inverting amplifier. An external 32.768kHz quartz crystal is used with the X1288 to supply a timebase for the real time clock. The recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a complete oscillator circuit. Care should be taken in the placement of the crystal and the layout of the circuit. Plenty of ground plane around the device and short traces to X1 and X2 are highly recommended. See Application section for more information. POWER CONTROL OPERATION The power control circuit accepts a VCC and a VBACK input. The power control circuit powers the clock from VBACK when VCC < VBACK - 0.2V. It will switch back to power the device from VCC when VCC exceeds VBACK. REAL TIME CLOCK OPERATION The Real Time Clock (RTC) uses an external 32.768kHz quartz crystal to maintain an accurate internal representa- tion of the 1/100 of a second, second, minute, hour, day, date, month, and year. The RTC has leap-year correction. The clock also corrects for months having fewer than 31 days and has a bit that controls 24 hour or AM/PM format. When the X1288 powers up after the loss of both VCC and VBACK, the clock will not operate until at least one byte is written to the clock register. X1288 X1 X2 VBACK VCC NC PHZ/IRQ NC VSS 1 2 3 4 13 14 12 11 14 Ld TSSOP NC NC SCL NC RESET SDA 5 6 7 9 10 8 16 Ld SOIC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X1 X2 NC VSS NC NC RESET NC VBACK VCC PHZ/IRQ NC SCL NC SDA NC NC = No internal connection X1 X2 FIGURE 2. RECOMMENDED CRYSTAL CONNECTION VBACK In Voltage VCC On Off FIGURE 3. POWER CONTROLFN8102 Rev 3.00 Page 9 of 27 April 14, 2006

X1288V14-2.7 Reviews

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Roge*****rtis

January 4, 2020

As I said before, your crew rock's keep up the fantastic work as we need you out there.

Jova*****Hood

November 30, 2019

can supply almost all of my necessary parts in short lead time.

Gabri*****opkins

November 29, 2019

Work Great. Would recommend. Only used 2. So I have 248 extras. Best deal by far that's why I got these.

Shel*****ambert

October 13, 2019

I have never been experienced anything wrong with my order, the logistic has always get out the same day, and the items are always well packaged.

Cooper*****nabhan

October 3, 2019

Fast shipping. Got it in few dayss from Hong Kong

Sama*****alwar

September 6, 2019

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Est***** Tank

July 15, 2019

Used it on my system it works perfect as I need.

Ange*****ajaj

June 6, 2019

Very quick dispatch, arrived the next day. Item as described. Thanks!

Juda*****rrett

March 7, 2019

It's an incredible place to buy the hard-to-find parts. Fair price, good quality and nice service! I would definitely do business with them again, thank you!

Iren*****niel

March 1, 2019

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hotX1288V14-2.7 ISL78302ARBNZ Intersil, IC REG LIN 1.5/3.3V 10DFN, 10-VFDFN Exposed Pad, - View
hotX1288V14-2.7 X4285PI-2.7 Intersil, IC SUPERVISOR CPU 128K EE 8-DIP, 8-DIP (0.300", 7.62mm), - View
hotX1288V14-2.7 ISL28195FRUZ-T7 Intersil, IC OPAMP GP 10KHZ RRO 6UTDFN, 6-UFDFN Exposed Pad, - View
hotX1288V14-2.7 EL1511CS Intersil, IC LINE DRIVER ADSL/VDSL 16-SOIC, 16-SOIC (0.154", 3.90mm Width), - View
hotX1288V14-2.7 ISL54503IHZ-T Intersil, IC SWITCH SPDT SOT23-6, SOT-23-6, - View
hotX1288V14-2.7 ISL84053IAZ-T7A Intersil, IC MULTIPLEXER TRIPLE 2X1 16QSOP, 16-SSOP (0.154", 3.90mm Width), - View
hotX1288V14-2.7 X1288V14Z-2.7T1 Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View
hotX1288V14-2.7 X1288V14I-2.7T1 Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View
hotX1288V14-2.7 X1288V14I Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View
hotX1288V14-2.7 X1288V14-4.5AT1 Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View
hotX1288V14-2.7 X1288V14-4.5A Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View
hotX1288V14-2.7 X1288V14-2.7AT1 Intersil, IC RTC CLK/CALENDAR I2C 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), - View

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