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Part Number X4043S8I-2.7A
Manufacturer Intersil
Datasheet X4043S8I-2.7A Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 386 piece(s)
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X4043S8I-2.7A Specifications

CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet X4043S8I-2.7ADatasheet
Package8-SOIC (0.154", 3.90mm Width)
TypeSimple Reset/Power-On Reset
Number of Voltages Monitored1
OutputOpen Drain or Open Collector
ResetActive Low
Reset Timeout100 ms Minimum
Voltage - Threshold2.92V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

X4043S8I-2.7A Datasheet

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FN8118 Rev 3.00 December 9, 2015 X4043, X4045 4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM DATASHEETFEATURES • Selectable watchdog timer • Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current • 4kbits of EEPROM —16-byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes of EEPROM array with Block Lock™ protection • 400kHz 2-wire interface • 2.7V to 5.5V power supply operation • Available packages —8 Ld SOIC —8 Ld MSOP —8 Ld PDIP • Pb-free plus anneal available (RoHS compliant) DESCRIPTION The X4043/45 combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space require- ments, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry stan- dard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power-on and GenerationVTRIP + - RESET (X4043) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic B lo ck L oc k C on tr ol 2K bi ts 1K b 1K b RESET (X4045)FN8118 Rev 3.00 Page 1 of 24 December 9, 2015

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X4043, X4045 Ordering Information PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGE X4043S8Z-4.5A (Note) X4043 Z AL X4045S8Z-4.5A (Note) X4045 Z AL 4.5-5.5 4.5-4.75 0 to 70 8 Ld SOIC (Pb-free) X4043S8IZ-4.5A (Note) X4043 Z AM X4045S8IZ-4.5A (Note) X4045 Z AM -40 to 85 8 Ld SOIC (Pb-free) X4043M8Z-4.5A (Note) DAZ X4045M8Z-4.5A (Note) (No longer available, recommended replacement: X4045S8Z-4.5A) DBH 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-4.5A (Note) DAU X4045M8IZ-4.5A (Note) (No longer available, recommended replacement: X4045S8IZ-4.5A) DBE -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-4.5A (Note) (No longer available, recommended replacement: X4043M8Z-4.5A) X4043P Z AL X4045PZ-4.5A (Note) (No longer available, recommended replacement: X4045S8Z-4.5A) X4045P Z AL 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-4.5A (Note) (No longer available, recommended replacement: X4043M8IZ-4.5A) X4043P Z AM X4045PIZ-4.5A (Note) (No longer available, recommended replacement: X4045S8IZ-4.5A) X4045P Z AM -40 to 85 8 Ld PDIP (Pb-free) X4043S8Z* (Note) X4043 Z X4045S8Z* (Note) X4045 Z 4.5-5.5 4.25-4.5 0 to 70 8 Ld SOIC (Pb-free) X4043S8IZ* (Note) X4043 Z I X4045S8IZ (Note) X4045 Z I -40 to 85 8 Ld SOIC (Pb-free) X4043M8Z* (Note) DAW X4045M8Z (Note) (No longer available, recommended replacement: X4045S8Z) DBD 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ (Note) DAR X4045M8IZ (Note) (No longer available, recommended replacement: X4045S8IZ) DBA -40 to 85 8 Ld MSOP (Pb-free) X4043PZ (Note) (No longer available, recommended replacement: X4043M8Z) X4043P X4045PZ (Note) (No longer available, recommended replacement: X4045S8Z) X4045P Z 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ (Note) (No longer available, recommended replacement: X4043M8IZ) X4043P Z I X4045PIZ (Note) (No longer available, recommended replacement: X4045S8IZ) X4045P Z I -40 to 85 8 Ld PDIP (Pb-free)FN8118 Rev 3.00 Page 2 of 24 December 9, 2015

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X4043, X4045 X4043S8Z-2.7A* (Note) X4043 Z AN X4045S8Z-2.7A (Note) X4045 Z AN 2.7-5.5 2.85-3.0 0 to 70 8 Ld SOIC (Pb-free) X4043S8IZ-2.7A* (Note) X4043 Z AP X4045S8IZ-2.7A (Note) X4045 Z AP -40 to 85 8 Ld SOIC (Pb-free) X4043M8Z-2.7A (Note) DAY X4045M8Z-2.7A (Note) (No longer available, recommended replacement: X4045S8Z-2.7A) DBG 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-2.7A (Note) DAT X4045M8IZ-2.7A (Note) (No longer available, recommended replacement: X4045S8IZ-2.7A) DBC -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-2.7A (Note) (No longer available, recommended replacement: X4043M8Z-2.7A) X4043P Z AN X4045PZ-2.7A (Note) (No longer available, recommended replacement: X4045S8Z-2.7A) X4045P Z AN 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-2.7A (Note) (No longer available, recommended replacement: X4043M8IZ-2.7A) X4043P Z AP X4045PIZ-2.7A (Note) (No longer available, recommended replacement: X4045S8IZ-2.7A) X4045P Z AP -40 to 85 8 Ld PDIP (Pb-free) X4043S8Z-2.7* (Note) X4043 Z F X4045S8Z-2.7* (Note) X4045 Z F 2.7-5.5 2.55-2.7 0 to 70 8 Ld SOIC (Pb-free) X4043S8IZ-2.7 (Note) X4043 Z G X4045S8IZ-2.7 (Note) X4045 Z G -40 to 85 8 Ld SOIC (Pb-free) X4043M8Z-2.7 (Note) DAX X4045M8Z-2.7 (Note) (No longer available, recommended replacement: X4045S8Z-2.7) DBF 0 to 70 8 Ld MSOP (Pb-free) X4043M8IZ-2.7(Note) DAS X4045M8IZ-2.7 (Note) (No longer available, recommended replacement: X4045S8IZ-2.7) DBB -40 to 85 8 Ld MSOP (Pb-free) X4043PZ-2.7 (Note) (No longer available, recommended replacement: X4043M8Z-2.7) X4043P Z F X4045PZ-2.7 (Note) (No longer available, recommended replacement: X4045S8Z-2.7) X4045P Z F 0 to 70 8 Ld PDIP (Pb-free) X4043PIZ-2.7 (Note) (No longer available, recommended replacement: X4043M8IZ-2.7) X4043P Z G X4045PIZ-2.7 (Note) (No longer available, recommended replacement: X4045S8IZ-2.7) X4045P Z G -40 to 85 8 Ld PDIP (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE (V) VTRIP RANGE (V) TEMP RANGE (°C) PACKAGEFN8118 Rev 3.00 Page 3 of 24 December 9, 2015

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X4043, X4045 The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features an 2-wire interface and software protocol allowing oper- ation on an I2C bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. PIN CONFIGURATION NC VSS VCC SDA SCL3 2 4 1 6 7 5 8NC WP RESET 8-Pin JEDEC SOIC, MSOP (PDIP no longer available or supported) Pin (SOIC/MSOP/DIP) Name Function 1 NC No internal connections 2 NC No internal connections 3 RESET/RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC falls below VTRIP. It will remain active until VCC rises above the VTRIP for tPURST. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. RESET/RESET goes active on power-uppower-up and remains active for 250ms after the power supply stabilizes. RESET is an active high open drain output. An external pull up resistor is required on the RESET/RESET pin. 4 VSS Ground 5 SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). 6 SCL Serial Clock. The Serial Clock input controls the serial bus timing for data input and output. 7 WP Write Protect. WP HIGH prevents writes to any location in the device (including the control register). Connect WP pin to VSS when it is not used. 8 VCC Supply VoltageFN8118 Rev 3.00 Page 4 of 24 December 9, 2015

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X4043, X4045 PRINCIPLES OF OPERATION Power-on Reset Application of power to the X4043/45 activates a Power- on Reset Circuit that pulls the RESET/RESET pin active. This signal provides several benefits. – It prevents the system microprocessor from starting to operate with insufficient voltage. – It prevents the processor from operating prior to stabi- lization of the oscillator. – It allows time for an FPGA to download its configura- tion prior to initialization of the circuit. When VCC exceeds the device VTRIP threshold value for 200ms (nominal) the circuit releases RESET/RESET allowing the system to begin operation. Low Voltage Monitoring During operation, the X4043/45 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microproces- sor activity by monitoring the SDA and SCL pins. A stan- dard read or write sequence to any slave address byte restarts the watchdog timer and prevents the (RESET/RESET) signal going active. A minimum sequence to reset the watchdog timer requires four microprocessor intructions namely, a Start, Clock Low, Clock High and Stop. (See Page 18) The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be “locked” by tying the WP pin HIGH. Figure 1. Watchdog Restart EEPROM Inadvertent Write Protection When RESET/RESET goes active as a result of a low voltage condition (VCC < VTRIP), any in-progress commu- nications are terminated. While VCC < VTRIP, no new communications are allowed and no nonvolatile write operation can start. Nonvolatile writes in-progress when RESET/RESET goes active are allowed to finish. Additional protection mechanisms are provided with memory block lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. VTRIP Programming The X4043/45 is shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applica- tions where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X4043/45 threshold may be adjusted. The procedure is described below, and uses the application of a high volt- age control signal. Figure 2. Set VTRIP Level Sequence (VCC = desired VTRIP values WEL bit set) SCL SDA .6µs 1.3µs Start StopResetWDT 0 1 2 3 4 5 6 7 SCL SDA A0h 0 1 2 3 4 5 6 7 01h WP VP = 15-18V 0 1 2 3 4 5 6 7 00hFN8118 Rev 3.00 Page 5 of 24 December 9, 2015

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X4043, X4045 Setting a VTRIP Voltage There are two procedures used to set the threshold voltages (VTRIP), depending if the threshold voltage to be stored is higher or lower than the present value. For example, if the present VTRIP is 2.9 V and the new VTRIP is 3.2 V, the new voltage can be stored directly into the VTRIP cell. If however, the new setting is to be lower than the present setting, then it is necessary to “reset” the VTRIP voltage before setting the new value. Setting a Higher VTRIP Voltage To set a VTRIP threshold to a new voltage which is higher than the present threshold, the user must apply the desired VTRIP threshold voltage to the VCC. Then, a programming voltage (Vp) must be applied to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h, followed by the Byte Address 01h for VTRIP and a 00h Data Byte in order to program VTRIP . The STOP bit following a valid write operation initiates the program- ming sequence. WP pin must then be brought LOW to complete the operation. To check if the VTRIP has been set, first power-down the device. Slowly ramp up VCC and observe when the output, RESET (4043) or RESET (4045) switches. The voltage at which this occurs is the VTRIP (actual) (see Figure 2). CASE A Now if the desired VTRIP is greater than the VTRIP (actual), then add the difference between VTRIP (desired) - VTRIP (actual) to the original VTRIP desired. This is your new VTRIP that should be applied to VCC and the whole sequence should be repeated again (see Figure 5). CASE B Now if the VTRIP (actual), is higher than the VTRIP (desired), perform the reset sequence as described in the next section. The new VTRIP voltage to be applied to VCC will now be: VTRIP (desired) - (VTRIP (actual) - VTRIP (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIP Voltage In order to set VTRIP to a lower voltage than the pres- ent value, then VTRIP must first be “reset” according to the procedure described below. Once VTRIP has been “reset”, then VTRIP can be set to the desired voltage using the procedure described in “Setting a Higher VTRIP Voltage”. Resetting the VTRIP Voltage To reset a VTRIP voltage, apply the programming volt- age (Vp) to the WP pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h fol- lowed by 00h for the Data Byte in order to reset VTRIP. The STOP bit following a valid write operation initiates the programming sequence. Pin WP must then be brought LOW to complete the operation. After being reset, the value of VTRIP becomes a nomi- nal value of 1.7V or lesser. Note: This operation does not corrupt the memory array.FN8118 Rev 3.00 Page 6 of 24 December 9, 2015

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X4043, X4045 Figure 3. Reset VTRIP Level Sequence (VCC > 3V. WP = 15-18V, WEL bit set) Figure 4. Sample VTRIP Reset Circuit 0 1 2 3 4 5 6 7 SCL SDA 0 1 2 3 4 5 6 7 WP VP = 15-18V 0 1 2 3 4 5 6 7 A0h 03h 00h 1 2 3 4 8 7 6 5 X4043 VTRIP Adj. VP RESET 4.7K SDA SCL µC Adjust RunFN8118 Rev 3.00 Page 7 of 24 December 9, 2015

Page 9

X4043, X4045 Figure 5. VTRIP Programming Sequence Control Register The control register provides the user a mechanism for changing the block lock and watchdog timer settings. The block lock and watchdog timer bits are nonvolatile and do not change when power is removed. The control register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write opera- tion directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the control register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See "Writing to the Control Register". The user must issue a stop after sending this byte to the register to initiate the nonvolatile cycle that stores WD1, WD0, BP2, BP1, and BP0. The X4043/45 will not acknowledge any data bytes written after the first byte is entered. VTRIP Programming Power-down Actual VTRIP – Desired VTRIP DONE Set Higher VTRIP Sequence Error < MDE– | Error | < | MDE | YES NO Error > MDE+ the Device Desired Present Value ? VTRIP < Execute No YES Execute VTRIP Reset Sequence Set VCC = desired VTRIP New VCC applied = Old VCC applied + | Error | New VCC applied = Old VCC applied – | Error | Execute Reset VTRIP Sequence Output Switches? Let: MDE = Maximum Desired Error MDE+ Desired Value MDE– Acceptable Error Range Error = Actual – Desired (RESET) Ramp VCC = ErrorFN8118 Rev 3.00 Page 8 of 24 December 9, 2015

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X4043, X4045 The state of the control register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The X4043/45 resets itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the control register) or until the part pow- ers up again. Writes to the WEL bit do not cause a non- volatile write cycle, so the device is ready for the next operation immediately after the stop condition. BP2, BP1, BP0: Block Protect Bits (Nonvolatile) The block protect bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block protect bits will prevent write operations to one of eight seg- ments of the array. WD1, WD0: Watchdog Timer Bits The bits WD1 and WD0 control the period of the watch- dog timer. The options are shown below. Writing to the Control Register Changing any of the nonvolatile bits of the control regis- ter requires the following steps: – Write a 02H to the control register to set the write enable latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation preceeded by a start and ended with a stop). – Write a 06H to the control register to set both the reg- ister write enable latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). – Write a value to the control register that has all the control bits set to the desired state. This can be repre- sented as 0xys t01r in binary, where xy are the WD bits, and rst are the BP bits. (Operation preceeded by a start and ended with a stop). Since this is a nonvola- tile write cycle it will take up to 10ms to complete. The RWEL bit is reset by this cycle and the sequence must be repeated to change the nonvolatile bits again. If bit 2 is set to ‘1’ in this third step (0xys t11r) then the RWEL bit is set, but the WD1, WD0, BP2, BP1 and BP0 bits remain unchanged. Writing a second byte to the control register is not allowed. Doing so aborts the write operation and returns a NACK. – A read operation occurring between any of the previ- ous operations will not interrupt the register write oper- ation. – The RWEL bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write pro- tected block. To illustrate, a sequence of writes to the device consist- ing of [02H, 06H, 02H] will reset all of the nonvolatile bits in the control register to 0. A sequence of [02H, 06H, 06H] will leave the nonvolatile bits unchanged and the RWEL bit remains set. 7 6 5 4 3 2 1 0 0 WD1 WD0 BP1 BP0 RWEL WEL BP2 B P 2 B P 1 B P 0 Protected Addresses (Size) Array Lock 0 0 0 None (factory setting) None 0 0 1 180h - 1FFh (128 bytes) Upper 1/4 (Q4) 0 1 0 100h - 1FFh (256 bytes) Upper 1/2 (Q3,Q4) 0 1 1 000h - 1FFh (512 bytes) Full Array (All) 1 0 0 000h - 00Fh (16 bytes) First Page (P1) 1 0 1 000h - 01Fh (32 bytes) First 2 pgs (P2) 1 1 0 000h - 03Fh (64 bytes) First 4 pgs (P4) 1 1 1 000h - 07Fh (128 bytes) First 8 pgs (P8) WD1 WD0 Watchdog Time Out Period 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 Disabled (factory setting)FN8118 Rev 3.00 Page 9 of 24 December 9, 2015

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