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X5043PIZ-2.7A

hotX5043PIZ-2.7A

X5043PIZ-2.7A

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Part Number X5043PIZ-2.7A
Manufacturer Intersil
Description IC SUPERVISOR CPU 4K EE 8-DIP
Datasheet X5043PIZ-2.7A Datasheet
Package 8-DIP (0.300", 7.62mm)
In Stock 223 piece(s)
Unit Price $ 3.2536 *
Lead Time Can Ship Immediately
Estimated Delivery Time Sep 27 - Oct 2 (Choose Expedited Shipping)
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Part Number # X5043PIZ-2.7A (PMIC - Supervisors) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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X5043PIZ-2.7A Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - PMIC - Supervisors
Datasheet X5043PIZ-2.7ADatasheet
Package8-DIP (0.300", 7.62mm)
Series-
TypeSimple Reset/Power-On Reset
Number of Voltages Monitored1
OutputOpen Drain or Open Collector
ResetActive Low
Reset Timeout100 ms Minimum
Voltage - Threshold2.92V
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeThrough Hole
Package / Case8-DIP (0.300", 7.62mm)
Supplier Device Package8-PDIP

X5043PIZ-2.7A Datasheet

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FN8126 Rev 3.00 September 23, 2015 X5043, X5045 4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM DATASHEETThese devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor executes code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Four industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. Features • Low VCC Detection and Reset Assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence. - Reset signal valid to VCC = 1V • Selectable Time Out Watchdog Timer • Long Battery Life with Low Power Consumption - <50µA max standby current, watchdog on - <10µA max standby current, watchdog off • 4Kbits of EEPROM–1M Write Cycle Endurance • Save Critical Data with Block Lock™ Memory - Protect 1/4, 1/2, all or none of EEPROM array • Built-in Inadvertent Write Protection - Write enable latch - Write protect pin • SPI Interface - 3.3MHz Clock Rate • Minimize Programming Time - 16-byte page write mode - 5ms write cycle time (typical) • Available Packages - 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP - 14 Ld TSSOP • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Communications Equipment - Routers, Hubs, Switches - Set Top Boxes • Industrial Systems - Process Control - Intelligent Instrumentation • Computer Systems - Desktop Computers - Network Servers • Battery Powered EquipmentFN8126 Rev 3.00 Page 1 of 21 September 23, 2015

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X5043, X5045Typical Application Block Diagram uC RESET CS SCK SI SO WP VCC VSS RESET SPI VCC VSS X5043 2.7-5.0V 10K Watchdog Timer Command Decode & Control Logic SI SO SCK CS/WDI VCC POR and Low Generation VTRIP + - RESET (X5043) Voltage Reset Protect Logic 4Kbits EEPROM Watchdog Detector WP Array Status Register Transition Reset Reset & Watchdog Timebase RESET (X5045) X5043, X5045 STANDARD VTRIP LEVEL SUFFIX 4.63V (+/-2.5%) -4.5A 4.38V (+/-2.5%) -4.5 2.93V (+/-2.5%) -2.7A 2.63V (+/-2.5%) -2.7 See “Ordering Information” on page 3. for more details For Custom Settings, call Intersil.FN8126 Rev 3.00 Page 2 of 21 September 23, 2015

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X5043, X5045Ordering Information PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE VTRIP RANGE TEMP RANGE (°C) PACKAGE X5043PZ-4.5A (Note) X5043P Z AL X5045PZ-4.5A (Note) X5045P Z AL 4.5-5.5V 4.5-4.75 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5045P Z AM -40 to 85 8 Ld PDIP (Pb-free) X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A (Note) X5045 Z AL 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ-4.5A* (Note) X5043 Z AM X5045S8IZ-4.5A* (Note) X5045 Z AM -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-4.5A (Note) DBS X5045M8Z-4.5A (Note) (No longer available, recommended replacement: X5045S8Z-4.5A) DCB 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-4.5A (Note) DBM X5045M8IZ-4.5A (Note) (No longer available, recommended replacement: X5045S8IZ-4.5A) DBX -40 to 85 8 Ld MSOP (Pb-free) X5043PZ (Note) X5043P Z X5045PZ (Note) X5045P Z 4.25-4.5 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ (Note) X5043P Z I X5045PIZ (Note) X5045P Z I -40 to 85 8 Ld PDIP (Pb-free) X5043S8Z* (Note) X5043 Z X5045S8Z* (Note) X5045 Z 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ* (Note) X5043 Z I X5045S8IZ* (Note) X5045 Z I -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z (Note) DBN X5045M8Z (Note) (No longer available, recommended replacement: X5045S8Z) DBY 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ (Note) DBJ X5045M8IZ (Note) (No longer available, recommended replacement: X5045S8IZ-2.7) DBT -40 to 85 8 Ld MSOP (Pb-free) X5043V14IZ (Note) (No longer available, recommended replacement: X5043M8IZ) X5043V Z I X5045V14IZ (Note) (No longer available or supported) X5045V Z I -40 to 85 14 Ld TSSOP (Pb-free)FN8126 Rev 3.00 Page 3 of 21 September 23, 2015

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X5043, X5045X5043PZ-2.7A (Note) X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN 2.7-5.5V 2.85-3.0 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP -40 to 85 8 Ld PDIP (Pb-free) X5043S8Z-2.7A* (Note) X5043 Z AN X5045S8Z-2.7A (Note) X5045 Z AN 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ-2.7A* (Note) X5043 Z AP X5045S8IZ-2.7A (Note) X5045 Z AP -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-2.7A (Note) DBR X5045M8Z-2.7A (Note) (No longer available, recommended replacement: X5045S8Z-2.7A) DCA 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-2.7A* (Note) DBL X5045M8IZ-2.7A (Note) (No longer available, recommended replacement: X5045S8IZ-2.7A) DBW -40 to 85 8 Ld MSOP (Pb-free) X5043PZ-2.7 (Note) X5043P Z F X5045PZ-2.7 (Note) X5045P Z F 2.55-2.7 0 to 70 8 Ld PDIP (Pb-free) X5043PIZ-2.7 (Note) X5043P Z G X5045PIZ-2.7 (Note) X5045P Z G -40 to 85 8 Ld PDIP (Pb-free) X5043S8Z-2.7* (Note) X5043 Z F X5045S8Z-2.7* (Note) X5045 Z F 0 to 70 8 Ld SOIC (Pb-free) X5043S8IZ-2.7* (Note) X5043 Z G X5045S8IZ-2.7* (Note) X5045 Z G -40 to 85 8 Ld SOIC (Pb-free) X5043M8Z-2.7 (Note) DBP X5045M8Z-2.7 (Note) (No longer available, recommended replacement: X5045S8Z-2.7) DBZ 0 to 70 8 Ld MSOP (Pb-free) X5043M8IZ-2.7* (Note) DBK X5045M8IZ-2.7 (Note) (No longer available, recommended replacement: X5045S8IZ-2.7) DBU -40 to 85 8 Ld MSOP (Pb-free) *Add "-T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER RESET (ACTIVE LOW) PART MARKING PART NUMBER RESET (ACTIVE HIGH) PART MARKING VCC RANGE VTRIP RANGE TEMP RANGE (°C) PACKAGEFN8126 Rev 3.00 Page 4 of 21 September 23, 2015

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X5043, X5045Pin Configuration Pin Descriptions Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin is latched on the rising edge of the clock input, while data on the SO pin changes after the falling edge of the clock input. Chip Select (CS/WDI) When CS is high, the X5043, X5045 are deselected and the SO output pin is at high impedance and, unless an internal write operation is underway, the X5043, X5045 will be in the standby power mode. CS low enables the X5043, X5045, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low, nonvolatile writes to the X5043, X5045 are disabled, but the part otherwise functions normally. When WP is held high, all functions, including non volatile writes operate normally. WP going low while CS is still low will interrupt a write to the X5043, X5045. If the internal write cycle has already been initiated, WP going low will have no affect on a write. Reset (RESET, RESET) X5043, X5045, RESET/RESET is an active low/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET also goes active if the Watchdog timer is enabled and CS remains either high or low longer than the Watchdog time out period. A falling edge of CS will reset the watchdog timer. Principles of Operation Power-on Reset Application of power to the X5043, X5045 activate a Power-on Reset Circuit. This circuit pulls the RESET/RESET pin active. RESET/RESET prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5043, X5045 monitor the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The Watchdog Timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent an active RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits. With no microprocessor action, the watchdog timer control bits remain unchanged, even during total power failure. 8 Ld SOIC/PDIP/MSOP CS/WDI WP SO 1 2 3 4 RESET/RESET 8 7 6 5 VCC X5043, X5045 VSS SCK SI 14 Ld TSSOP CS NC SO 1 2 3 4 RESET/RESET 14 13 12 11 VCC X5043, X5045 NC NC NC WP NC 5 6 7VSS NC10 9 8 SCK SI Pin Names SYMBOL DESCRIPTION CS/WDI Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage RESET/RESET Reset OutputFN8126 Rev 3.00 Page 5 of 21 September 23, 2015

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X5043, X5045VCC Threshold Reset Procedure The X5043, X5045 are shipped with a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or if higher precision is needed in the VTRIP value, the X5043, X5045 threshold may be adjusted. The procedure is described below, and uses the application of a high voltage control signal. Setting the VTRIP Voltage This procedure is used to set the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure will directly make the change. If the new setting is to be lower than the current setting, then it is necessary to reset the trip point before setting the new value. To set the new VTRIP voltage, apply the desired VTRIP threshold voltage to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 01h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 01h. Resetting the VTRIP Voltage This procedure is used to set the VTRIP to a “native” voltage level. For example, if the current VTRIP is 4.4V and the new VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply at least 3V to the VCC pin and tie the WP pin to the programming voltage VP. Then send a WREN command, followed by a write of Data 00h to address 03h. CS going HIGH on the write operation initiates the VTRIP programming sequence. Bring WP LOW to complete the operation. Note: This operation also writes 00h to array address 03h. 0 1 2 3 4 5 6 7 SCK SI CS 06h 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 8 Bits 01h02h WP VP = 15-18V 00h WREN Write Address Data 11 FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.) 0 1 2 3 4 5 6 7 SCK SI CS 06h 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 8 Bits 03h02h WP VP = 15-18V 00h WREN Write Address Data 11 FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)FN8126 Rev 3.00 Page 6 of 21 September 23, 2015

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X5043, X50451 2 3 4 8 7 6 5 X5043 VTRIP Adj. VP RESET 4.7K SI SO CS SCK µC Adjust Run X5045 FIGURE 3. SAMPLE VTRIP RESET CIRCUIT VTRIP Programming Apply 5V to VCC Decrement VCC RESET pin goes active? Measured VTRIP -Desired VTRIP DONE Execute Sequence Reset VTRIP Set VCC = VCC Applied = Desired VTRIP Execute Sequence Set VTRIP New VCC Applied Old VCC Applied (VCC = VCC–10mV) Execute Sequence Reset VTRIP Error -Emax -Emax < Error < Emax YES NO Error  Emax Emax = Maximum Desired Error - Error = New VCC Applied Old VCC Applied - Error = FIGURE 4. VTRIP PROGRAMMING SEQUENCEFN8126 Rev 3.00 Page 7 of 21 September 23, 2015

Page 9

X5043, X5045SPI Serial Memory The memory portion of the device is a CMOS Serial EEPROM array with Intersil’s block lock protection. The array is internally organized as 512 x 8 bits. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 1,000,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device contains an 8-bit instruction register that controls the operation of the device. The instruction code is written to the device via the SI input. There are two write operations that requires only the instruction byte. There are two read operations that use the instruction byte to initiate the output of data. The remainder of the operations require an instruction byte, an 8-bit address, then data bytes. All instruction, address and data bits are clocked by the SCK input. All instructions (Table 1), addresses and data are transferred MSB first. Clock and Data Timing Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. CS must be LOW during the entire operation. Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first. TABLE 1. INSTRUCTION SET INSTRUCTION NAME INSTRUCTION FORMAT* OPERATION WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations) WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations) RSDR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register (Watchdog and Block Lock) READ 0000 A8011 Read Data from Memory Array Beginning at Selected Address WRITE 0000 A8010 Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)FN8126 Rev 3.00 Page 8 of 21 September 23, 2015

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X5043, X5045Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 5). This latch is automatically reset upon a power-up condition and after the completion of a valid byte, page, or status register write cycle. The latch is also reset if WP is brought LOW. When issuing a WREN, WRDI or RDSR commands, it is not necessary to send a byte address or data. Status Register The Status Register contains four nonvolatile control bits and two volatile status bits. The control bits set the operation of the watchdog timer and the memory block lock protection. The Status Register is formatted as shown in “Status Register”. The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress. The Write Enable Latch (WEL) bit indicates the status of the “write enable” latch. When WEL = 1, the latch is set and when WEL = 0 the latch is reset. The WEL bit is a volatile, read only bit. The WREN instruction sets the WEL bit and the WRDS instruction resets the WEL bit. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. Read Status Register To read the Status Register, pull CS low to select the device, then send the 8-bit RDSR instruction. Then the contents of the Status Register are shifted out on the SO line, clocked by CLK. Refer to the Read Status Register Sequence (Figure 6). The Status Register may be read at any time, even during a Write Cycle. Write Status Register Prior to any attempt to write data into the status register, the “Write Enable” Latch (WEL) must be set by issuing the WREN instruction (Figure 5). First pull CS LOW, then clock the WREN instruction into the device and pull CS HIGH. Then bring CS LOW again and enter the WRSR instruction followed by 8 bits of data. These 8 bits of data correspond to the contents of the status register. The operation ends with CS going HIGH. If CS does not go HIGH between WREN and WRSR, the WRSR instruction is ignored. Status Register: (Default = 30H) 7 6 5 4 3 2 1 0 0 0 WD1 WD0 BL1 BL0 WEL WIP 0 1 2 3 4 5 6 7 CS SI SCK High Impedance SO FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE (WREN/WRDI INSTRUCTION) STATUS REG BITS ARRAY ADDRESSES PROTECTED BL1 BL0 X5043, X5045 0 0 None 0 1 $180–$1FF 1 0 $100–$1FF 1 1 $000–$1FF STATUS REGISTER BITS WATCHDOG TIME OUT (TYPICAL)WD1 WD0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory default) TABLE 2. DEVICE PROTECT MATRIX WREN CMD (WEL) DEVICE PIN (WP) MEMORY BLOCK STATUS REGISTER PROTECTED AREA UNPROTECTED AREA (BL0, BL1, WD0, WD1) 0 x Protected Protected Protected x 0 Protected Protected ProtectedFN8126 Rev 3.00 Page 9 of 21 September 23, 2015

X5043PIZ-2.7A Reviews

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Asa*****hal

August 22, 2020

These are a great value at this price.

Ember*****shadri

August 21, 2020

Perfect! Nice components, professional service!

Jale*****dgers

August 20, 2020

The pricing is great. This is the first time I use Heisener Electronics but I will recommend it to my business partners.

Misa*****aini

August 17, 2020

Serves its purpose. All that's needed.

Doug*****Coffey

August 15, 2020

This was a useful assortment of product that filled in a parts gap that I had on my electronic workbench. Thank you.

Elli*****Leon

August 9, 2020

Outstanding supplier! Heisener is on a very short list of suppliers I can recommend. From stock, pricing, ease of ordering and great service, they get it all.

Any*****obb

August 2, 2020

Super easy to replace and labelled terminals made it a quick replacement.

Rube*****wers

July 26, 2020

Excellent Seller,great product and Super Fast Shipping! Highly recommended A+++

Benj***** Stone

July 18, 2020

Well packed in anti-static bags. Repaired my amp perfectly - thank you!

Atlas*****andez

July 6, 2020

Completely satisfied of X5043PIZ-2.7A , I always find what I need. The site is easy to get the components .

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