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X9118TV14I

X9118TV14I

X9118TV14I

For Reference Only

Part Number X9118TV14I
Manufacturer Intersil
Description IC DCP 100K 1024TP 14TSSOP
Datasheet X9118TV14I Datasheet
Package 14-TSSOP (0.173", 4.40mm Width)
In Stock 146 piece(s)
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X9118TV14I

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X9118TV14I Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9118TV14I Datasheet
Package14-TSSOP (0.173", 4.40mm Width)
SeriesXDCP?
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps1024
Resistance (Ohms)100k
InterfaceI2C
Memory TypeNon-Volatile
Voltage - Supply5V
FeaturesSelectable Address
Tolerance±20%
Temperature Coefficient (Typ)±300 ppm/°C
Resistance - Wiper (Ohms) (Typ)150
Operating Temperature-40°C ~ 85°C
Package / Case14-TSSOP (0.173", 4.40mm Width)
Supplier Device Package14-TSSOP

X9118TV14I Datasheet

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FN8161 Rev 5.00 April 9, 2014 X9118 Dual Supply/Low Power/1024-Tap/2-Wire Bus Single Digitally-Controlled (XDCP™) Potentiometer DATASHEETThe X9118 is a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. Features • 1024 resistor taps – 10-bit resolution • 2-wire serial interface for write, read and transfer operations of the potentiometer • Wiper resistance, 40 typical @ 5V • Four non-volatile data registers for each potentiometer • Non-volatile storage of multiple wiper positions • Power on recall: Loads saved wiper position on power-up • Standby current < 15µA Max • System VCC: 2.7V to 5.5V operation • Analog V+/V-: -5V to +5V • 100k end-to-end resistance • Endurance: 100,000 data changes per bit per register • 100 years data retention • 14 Ld TSSOP • Low power CMOS • Pb-free (RoHS compliant) Ordering Information PART NUMBER (Notes 1, 2) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # X9118TV14IZ X9118 TVZI 5 ±10% 100 -40 to +85 14 Ld TSSOP M14.173 X9118TV14IZ-2.7 X9118 TVZG 2.7 to 5.5 100 -40 to +85 14 Ld TSSOP M14.173 X9118TV14Z X9118 TVZ 5 ±10% 100 0 to +70 14 Ld TSSOP M14.173 X9118TV14Z-2.7 X9118 TVZF 2.7 to 5.5 100 0 to +70 14 Ld TSSOP M14.173 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. 2. For Moisture Sensitivity Level (MSL), please see product information page for X9118. For more information on MSL, please see tech brief TB363.FN8161 Rev 5.00 Page 1 of 17 April 9, 2014

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X9118 Functional Diagram Detailed Functional Diagram Circuit Level Applications • Vary the gain of a voltage amplifier • Provide programmable DC reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the DC biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits System Level Applications • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems RH RL BUS RW INTERFACE CONTROL POT VCC VSS 2-WIRE BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kPOWER ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE V+ V- AND SCL A0 SDA A1 WP INTERFACE AND CONTROL CIRCUITRY V- V+VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100K CONTROL POWER ON RECALLFN8161 Rev 5.00 Page 2 of 17 April 9, 2014

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X9118 Pinout X9118 (14 LD TSSOP) TOP VIEW Pin Descriptions Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bi-directional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. The user must account for the capacitance on the bus line and the desired rise and fall times when selecting a pull-up resistor. 2kΩ to 2.5kΩ are typical values when using the maximum clock frequency. SERIAL CLOCK (SCL) This input is used by 2-wire master to supply 2-wire serial clock to the X9118. DEVICE ADDRESS (A1–A0) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input, in order to initiate communication with the X9118. A maximum of 4 XDCP devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin is equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system or digital supply voltage. The VSS pin is the system ground. ANALOG SUPPLY VOLTAGES (V+ AND V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Principles of Operation The X9118 is an integrated microcircuit incorporating a resistor array and its registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides a detailed description of the following: • Resistor Array Description • Serial Interface Description • Instruction and Register Description Pin Assignments PIN # PIN NAME FUNCTION 1 V+ Analog Supply Voltage 2, 10 NC No Connect 3 A0 Device Address for 2-wire bus 4 SCL Serial Clock for 2-wire bus 5 WP Hardware Write Protect 6 SDA Serial Data Input/Output for 2-wire bus 7 VSS System Ground 8 V- Analog Supply Voltage 9 A1 Device Address for 2-wire bus 11 RW Wiper terminal of the Potentiometer 12 RH High terminal of the Potentiometer 13 RL Low terminal of the Potentiometer 14 VCC System Supply Voltage VCC RL VSS 1 2 3 4 5 6 7 8 14 13 12 11 10 9 A0 RWSCL A1 RH NC V+ SDA NCWP V-FN8161 Rev 5.00 Page 3 of 17 April 9, 2014

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X9118 Resistor Array Description The X9118 is comprised of a resistor array. The array contains 1023, in effect, discrete resistive segments that are connected in series (see Figure 1). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch (transmission gate) connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the wiper counter register (WCR). The 10 bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. The WCR may be written directly. The Data Registers and the WCR can be read and written by the host system. Serial Interface Description SERIAL INTERFACE – 2-WIRE The X9118 supports a bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9118 will be considered a slave device in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW periods. The SDA state changes during SCL HIGH are reserved for indicating start and stop conditions, see Figure 3. START CONDITION All commands to the X9118 are preceded by the start condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The X9118 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met, see Figure 3. STOP CONDITION All communications must be terminated by a stop condition, which is a LOW-to-HIGH transition of SDA while SCL is HIGH, see Figure 3. ACKNOWLEDGE Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting 8 bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9118 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte, the X9118 will respond with a final acknowledge, see Figure 2. SERIAL DATA PATH FROM INTERFACE REGISTER 0 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER RL 10 10 C O U N T E R D E C O D E If WCR = 000[HEX] then RW = RL If WCR = 3FF[HEX] then RW = RH WIPER (WCR) (DR0) CIRCUITRY REGISTER 1 (DR1) REGISTER 2 (DR2) REGISTER 3 (DR3) FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM RW RHFN8161 Rev 5.00 Page 4 of 17 April 9, 2014

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X9118 ACKNOWLEDGE POLLING The disabling of the inputs during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9118 initiates the internal write cycle. The ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9118 is still busy with the write operation no ACK will be returned. If the X9118 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence INSTRUCTION AND REGISTER DESCRIPTION Device Addressing: Identification Byte (ID and A) Following a start condition, the master must output the address of the slave it is accessing. The most significant 4 bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9118; this is fixed as 0101[B] (refer to Table 1 on page 6). The A[1:0] bits in the ID byte are the internal slave address. The physical device address is defined by the state of the A1- A0 input pins. The slave address is externally specified by the user. The X9118 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9118 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A1 to A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is the LSB and used to set the device for read or write operations. INSTRUCTION BYTE AND REGISTER SELECTION The next byte sent to the X9118 contains the instruction and register pointer information. The three most significant bits are used to provide the instruction opcode (I[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2. Table 3 provides a complete summary of the instruction set opcodes. 1 8 9 START ACKNOWLEDGE SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER FIGURE 2. ACKNOWLEDGE RESPONSE FROM RECEIVER NONVOLATILE WRITE COMMAND COMPLETED ENTERACK POLLING ISSUE START ISSUE SLAVE ADDRESS ACK RETURNED? FURTHER OPERATION? ISSUE INSTRUCTION ISSUE STOP NO YES YES PROCEED ISSUE STOP NO PROCEEDFN8161 Rev 5.00 Page 5 of 17 April 9, 2014

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X9118 TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT REGISTER SELECTED RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 ID3 ID2 ID1 ID0 0 A1 A0 R/W 0 1 0 1 0 A1 A0 R/W (MSB) (LSB) DEVICE TYPE IDENTIFIES SET TO 0 FOR PROPER INTERNAL SLAVE ADDRESS READ OR WRITE BITOPERATION I2 I1 I0 0 RB RA 0 0 (MSB) (LSB) INSTRUCTION OPCODE SET TO 0 FOR PROPER OPERATION REGISTER SELECTION SET TO 0 FOR PROPER OPERATION TABLE 3. INSTRUCTION SET INSTRUCTION R/W INSTRUCTION SET OPERATIONI2 I1 I0 0 RB RA 0 0 Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the Data Register pointed to RB-RA. Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to RB-RA. XFR Data Register to Wiper Counter Register 1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by RB-RA to the Wiper Counter Register XFR Wiper Counter Register to Data Register 0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by RB-RA. NOTE: 3. 1/ = data is one or zero.FN8161 Rev 5.00 Page 6 of 17 April 9, 2014

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X9118 Instruction and Register Description Device Addressing WIPER COUNTER REGISTER (WCR) The X9118 contains a Wiper Counter Register (see Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. It may be written directly by the host via the write Wiper Counter Register instruction (serial load). 2. It may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data register. 3. It is loaded with the contents of its Data Register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, contents are lost when the X9118 is powered down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power- down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR) The potentiometer has four 10-bit non-volatile Data Registers. These can be read or written directly by the host. Data can be transferred between any of the four data registers and the Wiper Counter Register. All operations changing data in one of the Data Registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0 ~1023). Four of the six instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – Read the current wiper position of the potentiometer. • Write Wiper Counter Register – Change current wiper position of the potentiometer. • Read Data Register – Read the contents of the selected Data Register. • Write Data Register – Write a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 3. These four-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between the potentiometer and one of its associated registers. Two instructions (see Figure 4) require a two-byte sequence to complete. These instructions transfer data between the host and the X9118; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: • XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the Wiper Counter Register. • XFR Wiper Counter Register to Data Register –This transfers the contents of the specified Wiper Counter Register to the specified Data Register. Refer to “Instruction Format” on page 8 for more details. Other POWER-UP AND POWER-DOWN REQUIREMENTS At all times, the V+ voltage must be greater than or equal to the voltage at RH or RL, and the voltage at RH or RL must be greater than or equal to the voltage at V-. During power-up and power-down, VCC, V+, and V- must reach their final values within 1ms of each other. TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9 TO WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V V V (MSB) (LSB) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9 TO BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV MSB LSBFN8161 Rev 5.00 Page 7 of 17 April 9, 2014

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X9118 Instruction Format Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) S T A R T 0 1 0 1 0 A1 A0 R/W A C K I2 I1 I0 0 RB RA 0 A C K SCL SDA S T O P 0 0 0 ID3 ID2 ID1 ID0 DEVICE ID INTERNAL INSTRUCTION OPCODEADDRESS REGISTER ADDRESS FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE S T A R T A C K A C K SCL SDA A C K S T O P A C K ID3 ID2 ID1 ID0 0 A1 A0 R/W I2 0 0 0 X X 0 0 X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 I1 I0 0 RB RA 0 1 0 1 0 X X X DEVICE ID INTERNAL ADDRESS INSTRUCTION OPCODE REGISTER ADDRESS WIPER OR DATA POSITION FIGURE 4. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K S T O P0 1 0 1 0 A 1 A 0 R /W = 1 1 0 0 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY MASTER ON SDA) S A C K WIPER POSITION (SENT BY MASTER ON SDA) S A C K S T O P0 1 0 1 0 A 1 A 0 R /W = 0 1 0 1 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K WIPER POSITION OR DATA (SENT BY SLAVE ON SDA) M A C K S T O P0 1 0 1 0 A 1 A 0 R /W = 1 1 0 1 0 RB RA 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 FN8161 Rev 5.00 Page 8 of 17 April 9, 2014

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X9118 Write Data Register (DR) Transfer Wiper Counter Register (WCR) to Data Register (DR) Transfer Data Register (DR) to Wiper Counter Register (WCR) NOTES: 1. “A1 ~ A0”: stands for the device addresses sent by the master. 2. WCRx refers to wiper position data in the Wiper Counter Register. S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K S T O P H IG H -V O LT A G E W R IT E C Y C L E 0 1 0 1 0 A 1 A 0 R /W = 0 1 1 0 0 RB RA 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 0 A 1 A 0 R /W = 0 1 1 1 0 RB RA 0 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P0 1 0 1 0 A 1 A 0 R /W = 1 1 1 0 0 RB RA 0 0FN8161 Rev 5.00 Page 9 of 17 April 9, 2014

X9118TV14I Reviews

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Dext*****akshi

December 25, 2019

quick delivery, received with well packaged, exactly as listed - Thanks

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December 17, 2019

Absolutely the best source for wire, connectors, terminal strips, panel lights, etc. for model railroaders. Web site is the best in the business.

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November 23, 2019

Work Great. Would recommend. Only used 2. So I have 248 extras. Best deal by far that's why I got these.

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November 12, 2019

I'm so sure that you're beating your competitor on delivery!

Ik***** Li

November 4, 2019

Perfect, functional, arrived a weeks earlier, excellent Seller. Recommended

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October 29, 2019

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October 19, 2019

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October 9, 2019

Fast delivery well packed and as described.

Kae***** Dean

September 3, 2019

I always have good experiences in dealing with Heisener Electronics. They have the components I need in stock, their search function is great, and shipping is fast and always as promised.

Mic*****Ayala

August 28, 2019

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X9118TV14I X9119TV14IZ-2.7T1 Intersil, IC POT DGTL 100K OHM 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP? View
X9118TV14I X9119TV14Z-2.7 Intersil, IC XDCP SGL 1024TAP 100K 14TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP? View
X9118TV14I X9110TV14Z-2.7 Intersil, IC XDCP SGL 1024TAP 100K 14TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP? View
X9118TV14I X9116WS8IZ-2.7 Intersil, IC XDCP 16-TAP 10K CMOS 8-SOIC, 8-SOIC (0.154", 3.90mm Width), XDCP? View

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