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X9119TV14IZ

hot X9119TV14IZ

X9119TV14IZ

For Reference Only

Part Number X9119TV14IZ
Manufacturer Intersil
Description IC XDCP SGL 1024TAP 100K 14TSSOP
Datasheet X9119TV14IZ Datasheet
Package 14-TSSOP (0.173", 4.40mm Width)
In Stock 433 piece(s)
Unit Price $ 7.48 *
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X9119TV14IZ

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X9119TV14IZ Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9119TV14IZ Datasheet
Package14-TSSOP (0.173", 4.40mm Width)
SeriesXDCP?
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps1024
Resistance (Ohms)100k
InterfaceI2C
Memory TypeNon-Volatile
Voltage - Supply5V
FeaturesSelectable Address
Tolerance±20%
Temperature Coefficient (Typ)±300 ppm/°C
Resistance - Wiper (Ohms) (Typ)150
Operating Temperature-40°C ~ 85°C
Package / Case14-TSSOP (0.173", 4.40mm Width)
Supplier Device Package14-TSSOP

X9119TV14IZ Datasheet

Page 1

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FN8162 Rev 5.00 July 5, 2016 X9119 1024 Tap, Low Power, 2-Wire Interface, Digitally Controlled (XDCP™) Potentiometer DATASHEETThe X9119 integrates a single digitally controlled potentiometer (XDCP™) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 1023 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile data registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP™ can be used as a 3-terminal potentiometer or as a 2-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing. Features • 1024 resistor taps – 10-bit resolution • 2-Wire serial interface for write, read, and transfer operations of the potentiometer • Wiper resistance, 40Ω typical at VCC = 5V • Four nonvolatile data registers • Nonvolatile storage of multiple wiper positions • Power-on recall, loads saved wiper position on power-up. • Standby current <3µA maximum • VCC: 2.7V to 5.5V operation • 100kΩ end-to-end resistance • 100 yr. data retention • Endurance: 100,000 data changes per bit per register • 14 Ld TSSOP • Low power CMOS • Single supply version of the X9118 • Pb-free available (RoHS compliant) FIGURE 1. FUNCTIONAL DIAGRAM RH RL BUS RW INTERFACE CONTROL POT VCC VSS 2-WIRE BUS ADDRESS DATA STATUS WRITE READ WIPER 1024-TAPSTRANSFER NC NC 100kΩPOWER-ON RECALL WIPER COUNTER REGISTER (WCR) DATA REGISTERS (DR0-DR3)CONTROL INTERFACE ANDFN8162 Rev 5.00 Page 1 of 18 July 5, 2016

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X9119Applications Circuit Level • Vary the gain of a voltage amplifier • Provide programmable DC reference voltages for comparators and detectors • Control the volume in audio circuits • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the DC biasing of a pin diode attenuator in RF circuits • Provide a control variable (I, V, or R) in feedback circuits System Level • Adjust the contrast in LCD displays • Control the power level of LED transmitters in communication systems • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems Ordering Information PART NUMBER (Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE RoHS COMPLIANT PKG. DWG.# X9119TV14IZ X9119 TVZI 5 ±10% 100 -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z X9119 TVZ 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14Z-2.7 X9119 TVZF 2.7 to 5.5 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9119TV14IZ-2.7 (Note 1) X9119 TVZG -40 to +85 14 Ld TSSOP (4.4mm) M14.173 NOTES: 1. Add “T1” suffix for 2.5k unit tape and reel option. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9119. For more information on MSL, please see tech brief TB363. FIGURE 2. DETAILED FUNCTIONAL DIAGRAM SCL A1 SDA A2 WP INTERFACE AND CONTROL CIRCUITRY VCC VSS DR0 DR1 DR2 DR3 WIPER COUNTER REGISTER (WCR) RH RL DATA RW 1024-TAPS 100kΩ CONTROL POWER ON RECALL A0FN8162 Rev 5.00 Page 2 of 18 July 5, 2016

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X9119Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open-drain output and may be wire-ORed with any number of open-drain or open collector outputs. An open-drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by a 2-wire master to supply a 2-wire serial clock to the X9119. DEVICE ADDRESS (A2–A0) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9119. A maximum of 8 devices may occupy the 2-wire serial bus. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW, prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Other Pins NO CONNECT No connect pins should be left open. These pins are used for Intersil manufacturing and testing purposes. Principals of Operation The X9119 is an integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometer. This section provides detail description of the following: • Resistor Array Description • Serial Interface Description • Instruction and Register Description Resistor Array Description The X9119 is comprised of a resistor array. The array contains, in effect, 1023 discrete resistive segments that are connected in series (Figure 3 on page 4). The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select, and enable, one of 1024 switches. Pin Configuration X9119 (14 LD TSSOP) TOP VIEW Pin Assignments PIN NUMBER PIN NAME FUNCTION 1, 3, 10 NC No connect 2 A0 Device address for 2-wire bus 4 A2 Device address for 2-wire bus 5 SCL Serial clock for 2-wire bus 6 SDA Serial data input/output for 2-wire bus 7 VSS System ground 8 WP Hardware write protect 9 A1 Device address for 2-wire bus 11 RW Wiper terminal of the potentiometer 12 RH High terminal of the potentiometer 13 RL Low terminal of the potentiometer 14 VCC System supply voltage VCC RL VSS 1 2 3 4 5 6 7 8 14 13 12 11 10 9 NC RWA2 A1 RH A0 NC SDA NCSCL WPFN8162 Rev 5.00 Page 3 of 18 July 5, 2016

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X9119The WCR may be written directly. The data registers and the WCR can be read and written by the host system. Serial Interface Description SERIAL INTERFACE The X9119 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9119 will be considered a slave device in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 6 on page 8). START CONDITION All commands to the X9119 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9119 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met (Figure 6). STOP CONDITION All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 6). ACKNOWLEDGE Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9119 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9119 will respond with a final acknowledge (see Figure 4). ACKNOWLEDGE POLLING The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9119 initiates the internal write cycle. ACK polling, Flow 1 (see Figure 5 on page 5), can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9119 is still busy with the write operation, no ACK will be returned. If the X9119 has completed the write operation, an ACK will be returned and the master can then proceed with the next operation. FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION SERIAL DATA PATH FROM INTERFACE REGISTER 0 SERIAL BUS INPUT PARALLEL BUS INPUT COUNTER REGISTER RH RL R W 10 10 C O U N T E R D E C O D E WIPER (WCR) (DR0) CIRCUITRY REGISTER 1 (DR1) REGISTER 2 (DR2) REGISTER 3 (DR3) R IF WCR = 000[HEX] THEN RW = RL IF WCR = 3FF[HEX] THEN RW = RHFN8162 Rev 5.00 Page 4 of 18 July 5, 2016

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X9119FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER FIGURE 5. FLOW 1. ACK POLLING SEQUENCE SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9 ST AR T ACKNOWLEDGE DATA OUTPUT FROM RECEIVER NONVOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS ACK RETURNED? FURTHER OPERATION? ISSUE INSTRUCTION ISSUE STOP NO YES YES PROCEED ISSUE STOP NO PROCEEDFN8162 Rev 5.00 Page 5 of 18 July 5, 2016

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X9119Instruction and Register Description Device Addressing: Identification Byte (ID and A) Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier. The ID[3:0] bits is the device ID for the X9119; this is fixed as 0101[B] (refer to Table 1). The A2–A0 bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A2–A0 input pins. The slave address is externally specified by the user. The X9119 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9119 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A2–A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit is the LSB and is be used to program the device for read or write operations. INSTRUCTION BYTE AND REGISTER SELECTION The next byte sent to the X9119 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode (IOP[2:0]). The RB and RA bits point to one of the four registers. The format is shown in Table 2. Table 3 provides a complete summary of the instruction set opcodes. TABLE 1. IDENTIFICATION BYTE FORMAT TABLE 2. INSTRUCTION BYTE FORMAT ID3 ID2 ID1 ID0 A2 A1 A0 R/W 0 1 0 1 (MSB) (LSB) DEVICE TYPE IDENTIFIES INTERNAL SLAVE ADDRESS READ OR WRITE BIT I2 I1 I0 0 RB RA 0 0 (MSB) (LSB) INSTRUCTION OPCODE REGISTER SELECTION REGISTER SELECTED RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 TABLE 3. INSTRUCTION SET INSTRUCTION INSTRUCTION SET OPERATIONR/W I2 I1 I0 0 RB RA 0 0 Read Wiper Counter Register 1 1 0 0 0 0 0 0 0 Read the contents of the wiper counter register. Write Wiper Counter Register 0 1 0 1 0 0 0 0 0 Write new value to the wiper counter register. Read Data Register 1 1 0 1 0 1/0 1/0 0 0 Read the contents of the data register pointed to RB-RA. Write Data Register 0 1 1 0 0 1/0 1/0 0 0 Write new value to the data register pointed to RB-RA. XFR Data Register to Wiper Counter Register 1 1 1 0 0 1/0 1/0 0 0 Transfer the contents of the data register pointed to by RB-RA to the wiper counter register. XFR Wiper Counter Register to Data Register 0 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the wiper counter register to the data register pointed to by RB-RA. NOTE: 1/0 = data is one or zero.FN8162 Rev 5.00 Page 6 of 18 July 5, 2016

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X9119Instruction and Register Description Device Addressing WIPER COUNTER REGISTER (WCR) The X9119 contains a wiper counter register (refer to Table 4) for the XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of 1024 switches along its resistor array. The contents of the WCR can be altered in one of three ways: 1. It may be written directly by the host via the write wiper counter register instruction (serial load). 2. It may be written indirectly by transferring the contents of one of four associated data registers via the XFR data register. 3. It is loaded with the contents of its data register zero (R0) upon power-up. The wiper counter register is a volatile register; that is, its contents are lost when the X9119 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Power-up guidelines are recommended to ensure proper loadings of the DR0 value into the WCR. DATA REGISTERS (DR0 TO DR3) The potentiometer has four 10-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the wiper counter register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit 9 to Bit 0 are used to store one of the 1024 wiper position (0 ~1023). Four of the six instructions are four bytes in length. These instructions are: • Read Wiper Counter Register – Reads the current wiper position of the selected potentiometer. • Write Wiper Counter Register – Changes current wiper position of the selected potentiometer. • Read Data Register – Reads the contents of the selected Data Register. • Write Data Register – Writes a new value to the selected Data Register. The basic sequence of the four byte instructions is illustrated in Figure 6 on page 8. These 4-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write-to-nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers. Two instructions (Figure 7 on page 8) require a 2-byte sequence to complete. These instructions transfer data between the host and the X9119; either between the host and one of the data registers or directly between the host and the wiper counter register. These instructions are: • XFR Data Register to Wiper Counter Register – This transfers the contents of one specified data register to the wiper counter register. • XFR Wiper Counter Register to Data Register – This transfers the contents of the wiper counter register to the specified data register. See “Instruction Format” on page 8 for more details. POWER-UP AND POWER-DOWN REQUIREMENTS There are no restrictions on the power-up condition of VCC and the voltages applied to the potentiometer pins provided that the VCC is always more positive than or equal to the voltages at RH, RL, and RW, i.e., VCC ≥ RH, RL, RW. There are no restrictions on the power-down condition. However, the datasheet parameters for the DCP do not apply until 1ms after VCC reaches its final value. TABLE 4. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V) WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V V V (MSB) (LSB) TABLE 5. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV) BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NV NV NV NV NV NV NV NV NV NV MSB LSBFN8162 Rev 5.00 Page 7 of 18 July 5, 2016

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X9119Instruction Format READ WIPER COUNTER REGISTER (WCR) WRITE WIPER COUNTER REGISTER (WCR) READ DATA REGISTER (DR) WRITE DATA REGISTER (DR) S T A R T 0 1 0 1 A2 A1 A0 R/W A C K I2 I1I0 0 RB RA 0 A C K SCL SDA S T O P 0 0 0 ID3 ID2 ID1 ID0 DEVICE ID INTERNAL INSTRUCTION OPCODEADDRESS REGISTER ADDRESS FIGURE 6. TWO-BYTE INSTRUCTION SEQUENCE S T A R T A C K A C K SCL SDA A C K S T O P A C K ID3 ID2 ID1 ID0 A2 A1 A0 R/W I2 0 0 0 X X 0 0 X X X W C R 9 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 I1 I0 0 RB RA 0 1 0 1 X X X DEVICE ID INTERNAL ADDRESS INSTRUCTION OPCODE REGISTER ADDRESS WIPER OR DATA POSITION FIGURE 7. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS) W C R 8 W C R 7 W C R 6 W C R 5 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K S T O P 0 1 0 1 A2 A1 A0 R / W = 1 1 0 0 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY MASTER ON SDA) S A C K WIPER POSITION (SENT BY MASTER ON SDA) S A C K S T O P 0 1 0 1 A2 A1 A0 R / W = 0 1 0 1 0 0 0 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION (SENT BY SLAVE ON SDA) M A C K WIPER POSITION OR DATA (SENT BY SLAVE ON SDA) M A C K S T O P 0 1 0 1 A2 A1 A0 R / W = 1 1 0 1 0 RB RA 0 0 X X X X X X W CR 9 W CR 8 W CR 7 W CR 6 W CR 5 W CR 4 W CR 3 W CR 2 W CR 1 W CR 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K WIPER POSITION OR DATA (SENT BY MASTER ON SDA) S A C K S T O P H IG H -V O LT A G E W R IT E C YC LE 0 1 0 1 A2 A1 A0 R / W = 0 1 1 0 0 RB RA 0 0 X X X X X X W C R 9 W C R 8 W C R 7 W C R 6 W C R 5 W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 FN8162 Rev 5.00 Page 8 of 18 July 5, 2016

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X9119TRANSFER WIPER COUNTER REGISTER (WCR) TO DATA REGISTER (DR) TRANSFER DATA REGISTER (DR) TO WIPER COUNTER REGISTER (WCR) S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 A2 1 A0 R / W = 0 1 1 1 0 RB RA 0 0 S T A R T DEVICE TYPE IDENTIFIER DEVICE ADDRESSES S A C K INSTRUCTION OPCODE REGISTER ADDRESSES S A C K S T O P 0 1 0 1 A2 A1 A0 R / W = 1 1 1 0 0 RB RA 0 0 NOTES: 4. A2 ~ A0”: stand for the device addresses sent by the master. 5. WCRx refers to wiper position data in the wiper counter register.FN8162 Rev 5.00 Page 9 of 18 July 5, 2016

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hotX9119TV14IZ X9119TV14I-2.7 Intersil, IC DCP 100K 1024TP 14TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP? View
hotX9119TV14IZ X9119TV14-2.7 Intersil, IC DCP 100K 1024TP 14TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP? View
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hotX9119TV14IZ X9408WS24IZ-2.7 Intersil, IC XDCP QUAD 64TAP 10K 24-SOIC, 24-SOIC (0.295", 7.50mm Width), XDCP? View

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