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X9317ZV8I-2.7

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X9317ZV8I-2.7

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Part Number X9317ZV8I-2.7
Manufacturer Intersil
Description IC XDCP SGL 100TAP 1K 8-TSSOP
Datasheet X9317ZV8I-2.7 Datasheet
Package 8-TSSOP (0.173", 4.40mm Width)
In Stock 5,000 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Aug 7 - Aug 12 (Choose Expedited Shipping)
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Part Number # X9317ZV8I-2.7 (Data Acquisition - Digital Potentiometers) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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X9317ZV8I-2.7 Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9317ZV8I-2.7Datasheet
Package8-TSSOP (0.173", 4.40mm Width)
SeriesXDCP?
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps100
Resistance (Ohms)1k
InterfaceUp/Down (U/D, INC, CS)
Memory TypeNon-Volatile
Voltage - Supply2.7 V ~ 5.5 V
Features-
Tolerance±20%
Temperature Coefficient (Typ)±300 ppm/°C
Resistance - Wiper (Ohms) (Typ)400
Operating Temperature-40°C ~ 85°C
Package / Case8-TSSOP (0.173", 4.40mm Width)
Supplier Device Package8-TSSOP

X9317ZV8I-2.7 Datasheet

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Page 2

FN8183 Rev 9.00 November 4, 2014 X9317 Low Noise, Low Power, 100 Taps, Digitally Controlled Potentiometer (XDCP™) DATASHEETThe Intersil X9317 is a digitally controlled potentiometer (XDCP™). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. Applications • LCD bias control • DC bias adjustment • Gain and offset trim • Laser diode bias control • Voltage regulator output control Features • Solid-state potentiometer • 3-wire serial up/down interface • 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 99 resistive elements - Temperature compensated - End-to-end resistance range ±20% • Low power CMOS - VCC = 2.7V to 5.5V, and 5V ±10% - Standby current <5µA • High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years • RTOTAL values = 10kΩ, 50kΩ, 100kΩ • Packages - 8 Ld SOIC, TSSOP, and MSOP • Pb-free (RoHS compliant) UP/DOWN COUNTER 7-BIT NONVOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF ONE DECODER RESISTOR ARRAY RH U/D INC CS WIPER SWITCHESHUNDRED VCC VSS RL RW CONTROL AND MEMORY UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) VCC (SUPPLY VOLTAGE) VSS (GROUND) RH RW RL GENERAL DETAILED 0 1 2 96 97 98 99 FIGURE 1. BLOCK DIAGRAMFN8183 Rev 9.00 Page 1 of 13 November 4, 2014

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X9317Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VCC LIMITS (V) RTOTAL (kΩ) TEMPERATURE RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # X9317WM8Z DCW 5 ±10% 10 0 to +70 8 Ld MSOP M8.118 X9317WM8IZ DCT -40 to +85 8 Ld MSOP M8.118 X9317WS8Z X9317W Z 0 to +70 8 Ld SOIC M8.15E X9317WS8IZ X9317W ZI -40 to +85 8 Ld SOIC M8.15E X9317WV8Z 9317W Z 0 to +70 8 Ld TSSOP M8.173 X9317WV8IZ 9317W IZ -40 to +85 8 Ld TSSOP M8.173 X9317UM8Z DCS 50 0 to +70 8 Ld MSOP M8.118 X9317UM8IZ DCR -40 to +85 8 Ld MSOP M8.118 X9317US8Z X9317U Z 0 to +70 8 Ld SOIC M8.15E X9317US8IZ X9317U ZI -40 to +85 8 Ld SOIC M8.15E X9317UV8Z 9317U Z 0 to +70 8 Ld TSSOP M8.173 X9317UV8IZ 9317U IZ -40 to +85 8 Ld TSSOP M8.173 X9317TM8Z DCN 100 0 to +70 8 Ld MSOP M8.118 X9317TM8IZ DCL -40 to +85 8 Ld MSOP M8.118 X9317TS8Z X9317T Z 0 to +70 8 Ld SOIC M8.15E X9317TS8IZ X9317T ZI -40 to +85 8 Ld SOIC M8.15E X9317TV8Z 9317T Z 0 to +70 8 Ld TSSOP M8.173 X9317TV8IZ 9317T IZ -40 to +85 8 Ld TSSOP M8.173 X9317WM8Z-2.7 DCX 2.7 to 5.5 10 0 to +70 8 Ld MSOP M8.118 X9317WM8IZ-2.7 DCU -40 to +85 8 Ld MSOP M8.118 X9317WS8Z-2.7 X9317W ZF 0 to +70 8 Ld SOIC M8.15E X9317WS8IZ-2.7 X9317W ZG -40 to +85 8 Ld SOIC M8.15E X9317WV8Z-2.7 9317W FZ 0 to +70 8 Ld TSSOP M8.173 X9317WV8IZ-2.7 AKZ -40 to +85 8 Ld TSSOP M8.173 X9317UM8Z-2.7 AOB 50 0 to +70 8 Ld MSOP M8.118 X9317UM8IZ-2.7 AOH -40 to +85 8 Ld MSOP M8.118 X9317US8Z-2.7 X9317U ZF 0 to +70 8 Ld SOIC M8.15E X9317US8IZ-2.7 X9317U ZG -40 to +85 8 Ld SOIC M8.15E X9317UV8Z-2.7 9317U FZ 0 to +70 8 Ld TSSOP M8.173 X9317UV8IZ-2.7 9317U GZ -40 to +85 8 Ld TSSOP M8.173 X9317TM8Z-2.7 DCP 100 0 to +70 8 Ld MSOP M8.118 X9317TM8IZ-2.7 DCM -40 to +85 8 Ld MSOP M8.118 X9317TS8Z-2.7 X9317T ZF 0 to +70 8 Ld SOIC M8.15E X9317TS8IZ-2.7 X9317T ZG -40 to +85 8 Ld SOIC M8.15E X9317TV8Z-2.7 9317T FZ 0 to +70 8 Ld TSSOP M8.173 X9317TV8IZ-2.7 9317T GZ -40 to +85 8 Ld TSSOP M8.173 NOTES: 1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb- free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for X9317. For more information on MSL please see tech brief TB363.FN8183 Rev 9.00 Page 2 of 13 November 4, 2014

Page 4

X9317Pin Configurations X9317 (8 LD TSSOP) TOP VIEW X9317 (8 LD SOIC, 8 LD MSOP) TOP VIEW INC RLCS VCC 1 2 3 4 8 7 6 5U/D RW VSS RH RH VCCINC U/D 1 2 3 4 8 7 6 5VSS CS RL RW Pin Descriptions SOIC/MSOP TSSOP SYMBOL BRIEF DESCRIPTION 1 3 INC Increment Toggling INC while CS is low moves the wiper either up or down. 2 4 U/D Up/Down The U/D input controls the direction of the wiper movement. 3 5 RH The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 4 6 VSS Ground 5 7 RW The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer. 6 8 RL The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 7 1 CS Chip Select The device is selected when the CS input is LOW, and de-selected when CS is high. 8 2 VCC Supply VoltageFN8183 Rev 9.00 Page 3 of 13 November 4, 2014

Page 5

X9317Absolute Maximum Ratings Thermal Information IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA RH, RW, RL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V Voltage on CS, INC, U/D and VCC with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) SOIC Package (Notes 4, 5) . . . . . . . . . . . . . 115 60 MSOP Package (Notes 4, 5) . . . . . . . . . . . . 145 55 TSSOP Package (Notes 4, 5) . . . . . . . . . . . . 155 49 Junction Temperature Under Bias . . . . . . . . . . . . . . . . . . . -65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. Potentiometer Specifications VCC = full range. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL PARAMETER TEST CONDITIONS/NOTES MIN (Note 13) TYP (Note 9) MAX (Note 13) UNIT RTOTAL End-to-end Resistance Tolerance See “Ordering Information” on page 2 for values -20 +20 % VRH/RL RH/RL Terminal Voltage VSS = 0V VSS VCC V Power Rating RTOTAL ≥ 10kΩ 10 mW RW Wiper Resistance IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 5V 200 400 Ω IW = [V(RH) - V(RL)]/ RTOTAL, VCC = 2.7V 400 1000 Ω IW Wiper Current (Note 10) See “Test Circuit” on page 5 -4.4 +4.4 mA Noise (Note 12) Ref: 1kHz -120 dBV Resolution 1 % Absolute Linearity (Note 6) V(RH) = VCC, V(RL) = 0V -1 +1 MI (Note 8) Relative Linearity (Note 7) V(RH) = VCC, V(RL) = 0V -0.2 +0.2 MI (Note 8) RTOTAL Temperature Coefficient (Note 10) V(RH) = VCC, V(RL) = 0V ±300 ppm/°C Ratiometric Temperature Coefficient (Notes 10, 11) ±20 ppm/°C CH/CL/CW (Note 10) Potentiometer Capacitances See “Equivalent Circuit” on page 5 10/10/25 pF VCC Supply Voltage X9317 4.5 5.5 V X9317-2.7 2.7 5.5 VFN8183 Rev 9.00 Page 4 of 13 November 4, 2014

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X9317DC Electrical Specifications VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 13) TYP (Note 9) MAX (Note 13) UNIT ICC1 VCC Active Current (Increment) CS = VIL, U/D = VIL or VIH and INC = VIL/VIH at min. tCYC RL, RH, RW not connected 80 µA ICC2 VCC Active Current (Store) (non-volatile write) CS = VIH, U/D = VIL or VIH and INC = VIL or VIH. RL, RH, RW not connected 400 µA ISB Standby Supply Current CS  VIH, U/D and INC = VIL RL, RH, RW not connected 5 µA ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC -10 +10 µA VIH CS, INC, U/D Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VIL CS, INC, U/D Input LOW Voltage -0.5 VCC x 0.1 V CIN (Note 10) CS, INC, U/D Input Capacitance VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz 10 pF Endurance and Data Retention VCC = 5V ±10%, TA = Full Operating Temperature Range. PARAMETER MIN UNIT Minimum Endurance 100,000 Data changes per bit Data Retention 100 Years Test Circuit Equivalent Circuit FORCE CURRENT TEST POINT RW CH CL RW 10pF 10pF RTOTAL CW 25pF RH RL AC Conditions of Test Input pulse levels 0V to 3V Input rise and fall times 10ns Input reference levels 1.5V AC Electrical Specifications VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL PARAMETER MIN (Note 13) TYP (Note 9) MAX (Note 13) UNIT tCl CS to INC Setup 50 ns tlD (Note 10) INC HIGH to U/D Change 100 ns tDI (Note 10) U/D to INC Setup 1 µs tlL INC LOW Period 960 ns tlH INC HIGH Period 960 ns tlC INC Inactive to CS Inactive 1 µs tCPHS CS Deselect Time (STORE) 10 ms tCPHNS (Note 10) CS Deselect Time (NO STORE) 100 ns tIW INC to RW Change 1 5 µs tCYC INC Cycle Time 2 µsFN8183 Rev 9.00 Page 5 of 13 November 4, 2014

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X9317Power-up and Down Requirements The recommended power-up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until 1ms after VCC reaches its final value. The VCC ramp spec is always in effect. In order to prevent unwanted tap position changes, or an inadvertent store, bring the CS and INC high before or concurrently with the VCC pin on power-up. tR, tF (Note 10) INC Input Rise and Fall Time 500 µs tPU (Note 10) Power-up to Wiper Stable 5 µs tR VCC (Note 10) VCC Power-up Rate 0.2 50 V/ms tWR Store Cycle 5 10 ms NOTES: 6. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/99 + V(RL), with n from 0 to 99. 7. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) - MI)]/MI. 8. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/99. 9. Typical values are for TA = +25°C and nominal supply voltage. 10. This parameter is not 100% tested. 11. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2) x 10 6], with T1 and T2 being 2 temperatures, and n from 0 to 99. 12. Measured with wiper at tap position 99, RL grounded, using test circuit. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. AC Electrical Specifications VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). (Continued) SYMBOL PARAMETER MIN (Note 13) TYP (Note 9) MAX (Note 13) UNITFN8183 Rev 9.00 Page 6 of 13 November 4, 2014

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X9317AC Timing Typical Performance Characteristic CS INC U/D RW tCI tIL tIH tCYC tID tDI tIW MI (3) tIC tCPHS tF tR 10% 90% 90% tCPHNS -55 -350 -300 -250 -200 -150 -100 -50 0 -45 -35 -25 -15 -5 5 15 25 35 TEMPERATURE (°C) P P M 45 55 65 75 85 95 105115 125 FIGURE 2. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENTFN8183 Rev 9.00 Page 7 of 13 November 4, 2014

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X9317Pin Descriptions RH and RL The high (RH) and low (RL) terminals of the X9317 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 200Ω. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete, the X9317 will be placed in the low power standby mode until the device is selected once again. Principles of Operation There are three sections of the X9317: the control section, the nonvolatile memory, and the resistor array. The control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. Electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, RW. The wiper acts like its mechanical equivalent and does not move beyond the first or last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW, the device is selected and enabled to respond to the U/D and INC inputs. HIGH-to-LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a 7-bit counter. The output of this counter is decoded to select one of one hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9317, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as previously described and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalls the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Applications Information Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer, 2. The flexibility of computer-based digital controls, and 3. The retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Mode Selection CS INC U/D MODE L H Wiper up L L Wiper down H X Store wiper position to nonvolatile memory H X X Standby L X No store, return to standby L H Wiper up (not recommended) L L Wiper down (not recommended)FN8183 Rev 9.00 Page 8 of 13 November 4, 2014

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X9317Basic Configurations of Electronic Potentiometers FIGURE 3. THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER FIGURE 4. TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT VREF RW RH RL VREF I Basic Circuits FIGURE 5. BUFFERED REFERENCE VOLTAGE FIGURE 6. CASCADING TECHNIQUES FIGURE 7. SINGLE SUPPLY INVERTING AMPLIFIER FIGURE 8. VOLTAGE REGULATOR FIGURE 9. OFFSET VOLTAGE ADJUSTMENT FIGURE 10. COMPARATOR WITH HYSTERESIS - + +5V R1 +V VREF VOUT LMC7101 VOUT = VW/RW RW RW RW +V +V +V X (a) (b) + - R1 VO LMC7101 R2 +5V 100k 100k +5V VS VO = (R2/R1)VS R1 R2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 + - VS VO R2R1 100kΩ 10kΩ10kΩ 10kΩ +5V LMC7101 +5V VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) + -VS VO R2R1 } LT311A } FN8183 Rev 9.00 Page 9 of 13 November 4, 2014

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