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X9418YV24-2.7

hotX9418YV24-2.7

X9418YV24-2.7

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Part Number X9418YV24-2.7
Manufacturer Intersil
Description IC XDCP DUAL 64-TAP 2.5K 24TSSOP
Datasheet X9418YV24-2.7 Datasheet
Package 24-TSSOP (0.173", 4.40mm Width)
In Stock 433 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 2 - Jun 7 (Choose Expedited Shipping)
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Part Number # X9418YV24-2.7 (Data Acquisition - Digital Potentiometers) is manufactured by Intersil and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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X9418YV24-2.7 Specifications

ManufacturerIntersil
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9418YV24-2.7Datasheet
Package24-TSSOP (0.173", 4.40mm Width)
SeriesXDCP?
TaperLinear
ConfigurationPotentiometer
Number of Circuits2
Number of Taps64
Resistance (Ohms)2.5k
InterfaceI2C
Memory TypeNon-Volatile
Voltage - Supply��2.7 V ~ 5.5 V
FeaturesSelectable Address
Tolerance±20%
Temperature Coefficient (Typ)±300 ppm/°C
Resistance - Wiper (Ohms) (Typ)150
Operating Temperature0°C ~ 70°C
Package / Case24-TSSOP (0.173", 4.40mm Width)
Supplier Device Package24-TSSOP

X9418YV24-2.7 Datasheet

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FN8194 Rev 2.00 October 12, 2006 X9418 Low Noise/Low Power/2-Wire Bus Dual Digitally Controlled Potentiometers (XDCP™) DATASHEETNOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tscFEATURES • Two potentiometers in one package • 2-wire serial interface • Register oriented format —Direct Read/Write/Transfer Wiper Position —Store as many as Four Positions per Potentiometer • Power supplies —VCC = 2.7V to 5.5V —V+ = 2.7V to 5.5V —V– = -2.7V to -5.5V • Low power CMOS —Standby current < 1µA —Ideal for Battery Operated Applications • High reliability —Endurance–100,000 Data Changes per Bit per Register —Register Data Retention–100 years • 8-bytes of nonvolatile memory • 2.5k, 10k resistor array • Resolution: 64 taps each potentiometer • 24-pin plastic DIP, 24-lead TSSOP and 24-lead SOIC packages • Pb-Free plus anneal available (RoHS compliant) DESCRIPTION The X9418 integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM R0 R1 R2 R3 Resistor Array XDCP1 VH1/RH1 VL1/RL1 R0 R1 R2 R3 Wiper Counter Register (WCR) Interface and Control Circuitry SCL SDA A0 A1 A2 A3 VH0/RH0 VL0/RL0 Data 8 VW0/RW0 VW1/RW1 Wiper Counter Register (WCR) WP VCC VSS V+ V-FN8194 Rev 2.00 Page 1 of 20 October 12, 2006

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X9418PIN DESCRIPTIONS Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9418. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Device Address (A0 - A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9418. A maximum of 16 devices may occupy the 2- wire serial bus. Potentiometer Pins VH/RH (VH0/RH0 - VH1/RH1), VL/RL (VL0/RL0 - VL1/RL1) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0 - VW1/RW1) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, V- The Analog Supplies V+, V- are the supply voltages for the XDCP analog section. Ordering Information PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMET ER ORGANIZATION (k) TEMPERATU RE RANGE (°C) PACKAGE PKG. DWG. # X9418WV24* X9418WV 5 ±10% 10 0 to +70 24 Ld TSSOP (4.4MM) MDP0044 X9418WV24Z* (Note) X9418WV Z 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044 X9418WP24I-2.7 X9418WP G 2.7 to 5.5 10 -40 to +85 24 Ld PDIP E24.6 X9418WS24I-2.7 X9418WS G -40 to +85 24 Ld SOIC (300MIL) M24.3 X9418WS24IZ-2.7 (Note) X9418WS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3 X9418WV24-2.7* X9418WV F 0 to +70 24 Ld TSSOP (4.4MM) MDP0044 X9418WV24Z-2.7* (Note) X9418WV ZF 0 to +70 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044 X9418WV24I-2.7 X9418WV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044 X9418WV24IZ-2.7 (Note) X9418WV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044 X9418YS24-2.7 X9418YS F 2.5 0 to +70 24 Ld SOIC (300MIL) M24.3 X9418YS24Z-2.7 (Note) X9418YS ZF 0 to +70 24 Ld SOIC (300MIL) (Pb-free) M24.3 X9418YS24I-2.7 X9418YS G -40 to +85 24 Ld SOIC (300MIL) M24.3 X9418YS24IZ-2.7 (Note) X9418YS ZG -40 to +85 24 Ld SOIC (300MIL) (Pb-free) M24.3 X9418YV24I-2.7* X9418YV G -40 to +85 24 Ld TSSOP (4.4MM) MDP0044 X9418YV24IZ-2.7* (Note) X9418YV ZG -40 to +85 24 Ld TSSOP (4.4MM) (Pb-free) MDP0044 *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.FN8194 Rev 2.00 Page 2 of 20 October 12, 2006

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X9418PIN CONFIGURATION PIN NAMES PRINCIPLES OF OPERATION The X9418 is a highly integrated microcircuit incorporating two resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9418 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9418 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9418 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9418 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. Symbol Description SCL Serial Clock SDA Serial Data A0 - A3 Device Address VH0/RH0 - VH1/RH1, VL0/RL0 - VL1/RL1 Potentiometer Pins (terminal equivalent) VW0/RW0 - VW1/RW1 Potentiometer Pins (wiper equivalent) WP Hardware Write Protection V+,V- Analog Supplies VCC System Supply Voltage VSS System Ground NC No Connection VCC RL0/VL0 RH0/VH0 WP SDA A1 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 5 V+ NC NC NC A0 NC A3 SCL NC NC DIP/SOIC X9418 VSS RW0/VW0 14 13 11 12 A2 RL1/VL1 RH1/VH1 RW1/VW1 NC V- SDA A1 RL1/VL1 VSS NC NC 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 WP A2 VW0/RW0 VH0/RH0 VL0/RL0 VCC NC NC NC V+ X9418 A3 RH1/VH1 14 13 11 12 RW1/VW1 NC V- SCL A0 NC TSSOPFN8194 Rev 2.00 Page 3 of 20 October 12, 2006

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X9418The X9418 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9418 will respond with a final acknowledge. Array Description The X9418 is comprised of two resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9418 this is fixed as 0101[B]. Figure 1. Slave Address The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9418 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9418 to respond with an acknowledge. The A0 - A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9418 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9418 is still busy with the write operation no ACK will be returned. If the X9418 has completed the write operation an ACK will be returned, and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence Instruction Structure The next byte sent to the X9418 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two pots and when applicable they point to one of four associated registers. The format is shown Figure 2. 10 0 A3 A2 A1 A0 Device Type Identifier Device Address 1 Nonvolatile Write Command Completed Enter ACK Polling Issue START Issue Slave Address ACK Returned? Further Operation? Issue Instruction Issue STOP NO YES YES Proceed Issue STOP NO ProceedFN8194 Rev 2.00 Page 4 of 20 October 12, 2006

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X9418Figure 2. Instruction Byte Format The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P0) select which one of the two potentiometers is to be affected by the instruction. Bit 1 is defined to be 0. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the wiper counter register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the wiper counter register (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between both of the potentiometers and one of their associated registers. Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9418; either between the host and one of the Data Registers or directly between the host and the wiper counter register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9418 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Figure 3. Two-Byte Instruction Sequence I1I2I3 I0 R1 R0 0 P0 Wiper Counter Register Select Register Select Instructions S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 0 P0 A C K SCL SDA S T O P FN8194 Rev 2.00 Page 5 of 20 October 12, 2006

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X9418Table 1. Instruction Set Note: (7) 1/0 = data is one or zero Figure 4. Three-Byte Instruction Sequence Figure 5. Increment/Decrement Instruction Sequence Instruction Instruction Set OperationI3 I2 I1 I0 R1 R0 P1 P0 Read Wiper Counter Register 1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter Register pointed to by P0 Write Wiper Counter Register 1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter Register pointed to by P0 Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed to by P0 and R1 - R0 Write Data Register 1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed to by P0 and R1 - R0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register pointed to by P0 and R1 - R0 to its associated Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by R1 - R0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by R1 - R0 of both pots to their respective Wiper Counter Registers Global XFR Wiper Count- er Registers to Data Reg- ister 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by R1 - R0 of both pots Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter Register pointed to by P0 S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 0 P0 A C K SCL SDA S T O P A C K 0 0 D5 D4 D3 D2 D1 D0 S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R0 0 P0 A C K SCL SDA S T O P XX I N C 1 I N C 2 I N C n D E C 1 D E C n R1FN8194 Rev 2.00 Page 6 of 20 October 12, 2006

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X9418Figure 6. Increment/Decrement Timing Limits Figure 7. Acknowledge Response from Receiver SCL SDA VW/RW INC/DEC CMD Issued Voltage Out tWRID SCL from Data Output from Transmitter 1 8 9 START Acknowledge Master Data Output from ReceiverFN8194 Rev 2.00 Page 7 of 20 October 12, 2006

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X9418Figure 8. Detailed Potentiometer Block Diagram DETAILED OPERATION Both XDCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9418 contains two wiper counter registers, one for each XDCP potentiometer. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty- four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9418 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions Data Registers, (6-Bit), Nonvolatile Four 6-bit Data Registers for each XDCP. (eight 6-bit registers in total). – {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the Wiper Counter Register on power-up. Serial Data Path From Interface Circuitry Register 0 Register 1 Register 2 Register 3 Serial Bus Input Parallel Bus Input Wiper Counter Register INC/DEC Logic UP/DN CLK Modified SCL UP/DN VH/RH VL/RL VW/RW If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH 8 6 C o u n t e r D e c o d e (WCR) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MSB) (LSB)FN8194 Rev 2.00 Page 8 of 20 October 12, 2006

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X9418Wiper Counter Register, (6-Bit), Volatile One 6-bit wiper counter register for each XDCP. (Four 6- bit registers in total.) – {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. Instruction Format Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A3 ~ A0”: stands for the device addresses sent by the master. (3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. (4) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) Write Wiper Counter Register (WCR) Read Data Register (DR) Write Data Register (DR) XFR Data Register (DR) to Wiper Counter Register (WCR) WP5 WP4 WP3 WP2 WP1 WP0 V V V V V V (MSB) (LSB) S T A R T device type identifier device addresses S A C K instruction opcode WCR addresses S A C K wiper position (sent by slave on SDA) M A C K S T O P0 1 0 1 A 3 A 2 A 1 A 0 1 0 0 1 0 0 0 P 0 0 0 W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 S T A R T device type identifier device addresses S A C K instruction opcode WCR addresses S A C K wiper position (sent by master on SDA) S A C K S T O P0 1 0 1 A 3 A 2 A 1 A 0 1 0 1 0 0 0 0 P 0 0 0 W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K wiper position/data (sent by slave on SDA) M A C K S T O P0 1 0 1 A 3 A 2 A 1 A 0 1 0 1 1 R 1 R 0 0 P 0 0 0 W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K wiper position/data (sent by master on SDA) S A C K S T O P HIGH-VOLTAGE WRITE CYCLE 0 1 0 1 A3 A 2 A 1 A 0 1 1 0 0 R 1 R 0 0 P0 0 0 W P 5 W P 4 W P 3 W P 2 W P 1 W P 0 S T A R T device type identifier device addresses S A C K instruction opcode DR and WCR addresses S A C K S T O P0 1 0 1 A 3 A 2 A 1 A 0 1 1 0 1 R 1 R 0 0 P 0 FN8194 Rev 2.00 Page 9 of 20 October 12, 2006

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May 16, 2020

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May 12, 2020

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April 25, 2020

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April 21, 2020

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