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X9C102SZ

hot X9C102SZ

X9C102SZ

For Reference Only

Part Number X9C102SZ
Manufacturer Renesas Electronics America
Description IC XDCP 100-TAP 1K EE 8-SOIC
Datasheet X9C102SZ Datasheet
Package 8-SOIC (0.154", 3.90mm Width)
In Stock 2492 piece(s)
Unit Price $ 5.22 *
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X9C102SZ

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X9C102SZ Specifications

ManufacturerRenesas Electronics America
CategoryIntegrated Circuits (ICs) - Data Acquisition - Digital Potentiometers
Datasheet X9C102SZ Datasheet
Package8-SOIC (0.154", 3.90mm Width)
SeriesXDCP™
TaperLinear
ConfigurationPotentiometer
Number of Circuits1
Number of Taps100
Resistance (Ohms)1k
InterfaceUp/Down (U/D, INC, CS)
Memory TypeNon-Volatile
Voltage - Supply5V
Tolerance±20%
Temperature Coefficient (Typ)±600 ppm/°C
Resistance - Wiper (Ohms) (Typ)40
Operating Temperature0°C ~ 70°C
Package / Case8-SOIC (0.154", 3.90mm Width)
Supplier Device Package8-SOIC

X9C102SZ Datasheet

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FN8222 Rev 3.00 July 20, 2009 X9C102, X9C103, X9C104, X9C503 Digitally Controlled Potentiometer (XDCP™) DATASHEETThe X9C102, X9C103, X9C104, X9C503 are Intersils’ digitally controlled (XDCP) potentiometers. The device consists of a resistor array, wiper switches, a control section, and non-volatile memory. The wiper position is controlled by a three-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in non-volatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications ranging from control to signal processing to parameter adjustment. Pinout X9C102, X9C103, X9C104, X9C503 (8 LD SOIC, 8 LD PDIP) TOP VIEW Features • Solid-State Potentiometer • Three-Wire Serial Interface • 100 Wiper Tap Points - Wiper Position Stored in Non-volatile Memory and Recalled on Power-up • 99 Resistive Elements - Temperature Compensated - End-to-End Resistance, ±20% - Terminal Voltages, ±5V • Low Power CMOS - VCC = 5V - Active Current, 3mA max. - Standby Current, 750µA max. • High Reliability - Endurance, 100,000 Data Changes per Bit - Register Data Retention, 100 years • X9C102 = 1k • X9C103 = 10k • X9C503 = 50k • X9C104 = 100k • Packages - 8 Ld SOIC - 8 Ld PDIP • Pb-Free Available (RoHS Compliant) Block Diagram VCC CS VL/RL VW/RW INC U/D VH/RH VSS 1 2 3 4 8 7 6 5 7-BIT UP/DOWN COUNTER 7-BIT NON-VOLATILE MEMORY STORE AND RECALL CONTROL CIRCUITRY ONE OF HUNDRED DECODER RESISTOR ARRAY RL/VL RW/VW RH/VH U/D INC CS TRANSFER VCC ONE- GATES 99 98 97 96 2 1 0GND UP/DOWN (INC)INCREMENT DEVICE (U/D) (CS) VCC (SUPPLY VOLTAGE) VSS (GROUND) CONTROL AND MEMORY GENERAL VH/RH RW/VW VL/RLSELECT DETAILEDFN8222 Rev 3.00 Page 1 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Ordering Information PART NUMBER PART MARKING RTOTAL (k) TEMP RANGE (°C) PACKAGE PACKAGE DWG. # X9C102P X9C102P 1 0 to +70 8 Ld PDIP MDP0031 X9C102PZ (Notes 1, 2) X9C102P Z 0 to +70 8 Ld PDIP (Pb-free) MDP0031 X9C102PI X9C102P I -40 to +85 8 Ld PDIP MDP0031 X9C102PIZ (Notes 1, 2) X9C102P ZI -40 to +85 8 Ld PDIP (Pb-free) MDP0031 X9C102S*, ** X9C102S 0 to +70 8 Ld SOIC MDP0027 X9C102SZ* (Note 1) X9C102S Z 0 to +70 8 Ld SOIC (Pb-free) MDP0027 X9C102SI*, ** X9C102S I -40 to +85 8 Ld SOIC MDP0027 X9C102SIZ*, ** (Note 1) X9C102S ZI -40 to +85 8 Ld SOIC (Pb-free) MDP0027 X9C103P X9C103P 10 0 to +70 8 Ld PDIP MDP0031 X9C103PZ (Notes 1, 2) X9C103P Z 0 to +70 8 Ld PDIP (Pb-free) MDP0031 X9C103PI X9C103P I -40 to +85 8 Ld PDIP MDP0031 X9C103PIZ (Note 1) X9C103P ZI -40 to +85 8 Ld PDIP (Pb-free) MDP0031 X9C103S*, ** X9C103S 0 to +70 8 Ld SOIC MDP0027 X9C103SZ*, ** (Note 1) X9C103S Z 0 to +70 8 Ld SOIC (Pb-free) MDP0027 X9C103SI*, ** X9C103S I -40 to +85 8 Ld SOIC MDP0027 X9C103SIZ*, ** (Note 1) X9C103S ZI -40 to +85 8 Ld SOIC (Pb-free) MDP0027 X9C503P X9C503P 50 0 to +70 8 Ld PDIP MDP0031 X9C503PZ (Notes 1, 2) X9C503P Z 0 to +70 8 Ld PDIP (Pb-free) MDP0031 X9C503PI X9C503P I -40 to +85 8 Ld PDIP MDP0031 X9C503PIZ (Notes 1, 2) X9C503P ZI -40 to +85 8 Ld PDIP (Pb-free) MDP0031 X9C503S* X9C503S 0 to +70 8 Ld SOIC MDP0027 X9C503SZ* (Note 1) X9C503S Z 0 to +70 8 Ld SOIC (Pb-free) MDP0027 X9C503SI*, ** X9C503S I -40 to +85 8 Ld SOIC MDP0027 X9C503SIZ*, ** (Note 1) X9C503S ZI -40 to +85 8 Ld SOIC (Pb-free) MDP0027 X9C104P X9C104P 100 0 to +70 8 Ld PDIP MDP0031 X9C104PI X9C104P I -40 to +85 8 Ld PDIP MDP0031 X9C104PIZ (Notes 1, 2) X9C104P ZI -40 to +85 8 Ld PDIP (Pb-free) MDP0031 X9C104S*, ** X9C104S 0 to +70 8 Ld SOIC MDP0027 X9C104SZ*, ** (Note 1) X9C104S Z 0 to +70 8 Ld SOIC (Pb-free) MDP0027 X9C104SI*, ** X9C104S I -40 to +85 8 Ld SOIC MDP0027 X9C104SIZ*, ** (Note 1) X9C104S ZI -40 to +85 8 Ld SOIC (Pb-free) MDP0027 *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. **Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.FN8222 Rev 3.00 Page 2 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 INC INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 2 U/D UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. 3 VH/RH VH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. 4 VSS VSS 5 VW/RW VW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. 6 RL/VL RL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. 7 CS CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103, X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again. 8 VCC VCCFN8222 Rev 3.00 Page 3 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V Voltage on VH/RH and VL/RL Referenced to VSS. . . . . . . -8V to +8V V = |VH/RH - VL/RL| X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V X9C103, X9C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . . . .10V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA Power Rating X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . -65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C Industrial Temperature Range . . . . . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage Range (VCC) . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications Over recommended operating conditions unless otherwise stated. SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP (Note 6) MAX POTENTIOMETER CHARACTERISTICS RTOTAL End-to-End Resistance Variation -20 +20 % VVH/RH VH Terminal Voltage -5 +5 V VVL/RL VL Terminal Voltage -5 +5 V IW Wiper Current -4.4 4.4 mA RW Wiper Resistance Wiper Current = ±1mA 40 100  Resistor Noise (Note 7) Ref 1kHz -120 dBV Charge Pump Noise (Note 7) @ 850kHz 20 mVRMS Resolution 1 % Absolute Linearity (Note 3) VW(n)(actual) - VW(n)(EXPECTED) -1 +1 MI (Note 5) Relative Linearity (Note 4) VW(n + 1)(ACTUAL) - [VW(n) + MI] -0.2 +0.2 MI (Note 5) RTOTAL Temperature Coefficient X9C103, X9C503, X9C104 ±300 (Note 7) ppm/°C RTOTAL Temperature Coefficient X9C102 ±600 (Note 7) ppm/°C Ratiometric Temperature Coefficient ±20 ppm/°C CH/CL/CW (Note 7) Potentiometer Capacitances See “Circuit #3 SPICE Macro Model” on page 5. 10/10/25 pF DC OPERATING CHARACTERISTICS ICC VCC Active Current CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V at Max tCYC 1 3 mA ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V 200 750 µA ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC ±10 µA VIH CS, INC, U/D input HIGH Voltage 2 V VIL CS, INC, U/D input LOW Voltage 0.8 V CIN CS, INC, U/D Input Capacitance (Note 7) VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz 10 pFFN8222 Rev 3.00 Page 4 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Power-up and Down Requirements At all times, voltages on the potentiometer pins must be less than ±VCC. The recall of the wiper position from non-volatile memory is not in effect until the VCC supply reaches its final value. The VCC ramp rate specification is always in effect. AC OPERATION CHARACTERISTICS tCl CS to INC Setup 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Setup 2.9 µs tlL INC LOW Period 1 µs tlH INC HIGH Period 1 µs tlC INC Inactive to CS Inactive 1 µs tCPH CS Deselect Time (STORE) 20 ms tCPH CS Deselect Time (NO STORE) 100 ns tIW (5) INC to VW/RW Change 100 µs tCYC INC Cycle Time 2 µs tCYC INC Input Rise and Fall Time 500 µs tR, tF Power-up to Wiper Stable (Note 7) 500 µs tPU VCC Power-up Rate (Note 7) 0.2 50 V/ms NOTES: 3. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum. 4. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI. 5. 1 MI = Minimum Increment = RTOT/99. 6. Typical values are for TA = +25°C and nominal supply voltage. 7. This parameter is not 100% tested. Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITMIN TYP (Note 6) MAX Test Circuit #1 TEST POINT Vw/RW VR/RH VL/RL VS Test Circuit #2 FORCE VL/RL VW/Rw VH/RH TEST POINT CURRENT Circuit #3 SPICE Macro Model CW RTOTAL RL RH CL RW 10pF CL 10pF 25pF Endurance and Data Retention PARAMETER MIN UNIT Medium Endurance 100,000 Data changes per bit per register Data Retention 100 years AC Conditions of Test Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input Reference Levels 1.5VFN8222 Rev 3.00 July 20, 2009Page 5 of 10

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X9C102, X9C103, X9C104, X9C503AC Timing Diagram Pin Descriptions RH/VH and RL/VL The high (VH/RH) and low (VL/RL) terminals of the ISLX9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and V L /R L references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the ISLX9C102, X9C103, X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again. Principles of Operation There are three sections of the X9C102, X9C103, ISL9C104 and ISL9C503: the input control, counter and decode section; the non-volatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions, the contents of the counter can be stored in non-volatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW/RW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the non-volatile memory. When power is restored, the contents of the memory are recalled and the wiper is reset to the value last stored. The internal charge pump allows a wide range of voltages (from -5V to 5V) applied to XDCP terminals yet given a convenience of single power supply. The typical charge pump noise of 20mV at 850kHz should be taken in consideration when designing an application circuit. CS INC U/D VW tCI tIL tIH tCYC tID tDI tIW MI tIC tCPH tF tR 10% 90% 90% (NOTE) NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION.FN8222 Rev 3.00 Page 6 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW, the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a 7-bit counter. The output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. The value of the counter is stored in non-volatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9Cxxx, move the wiper and deselect the device without having to store the latest wiper position in non-volatile memory. After the wiper movement is performed as previously described and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a pre- set value stored in non-volatile memory; then during system operation, minor adjustments could be made. The adjustments might be based on user preference, i.e.: system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Symbol Table Performance Characteristics Contact the factory for more information. Applications Information Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer. 2. The flexibility of computer-based digital controls. 3. The retentivity of non-volatile memory used for the storage of multiple potentiometer settings or data. Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position H X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High ImpedanceFN8222 Rev 3.00 Page 7 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503Basic Configurations of Electronic Potentiometers Basic Circuits VR VR I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT VH/RH VL/RL VW/RW CASCADING TECHNIQUESBUFFERED REFERENCE VOLTAGE – + +5V R1 +V -5V VW VREF VOUT OP-07 VW/RW VW/RW +V +V +V X (a) (b) VOUT = VW/RW NONINVERTING AMPLIFIER VO = (1+R2/R1)VS VOLTAGE REGULATOR R1 R2 Iadj VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VO (REG)VIN 317 OFFSET VOLTAGE ADJUSTMENT + – VS VO R2R1 100k 10k10k 10k -12V+12V TL072 COMPARATOR WITH HYSTERESIS VUL = {R1/(R1 + R2)} VO(MAX) VLL = {R1/(R1 + R2)} VO(MIN) + – VS VO R2 R1 LM308A +5V -5V + –VS VO R2R1 }} LT311A (FOR ADDITIONAL CIRCUITS SEE AN1145)FN8222 Rev 3.00 Page 8 of 10 July 20, 2009

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X9C102, X9C103, X9C104, X9C503 FN8222 Rev 3.00 Page 9 of 10 July 20, 2009 Small Outline Package Family (SO) GAUGE PLANE A2 A1 L L1 DETAIL X 4° ±4° SEATING PLANE e H b C 0.010 BM C A0.004 C 0.010 BM C A B D (N/2)1 E1E N (N/2)+1 A PIN #1 I.D. MARK h X 45° A SEE DETAIL “X” c 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL INCHES TOLERANCE NOTESSO-8 SO-14 SO16 (0.150”) SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - N 8 14 16 16 20 24 28 Reference - Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994

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hotX9C102SZ X9271TV14Z Intersil, IC XDCP SGL 256TAP 100K 14-TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP™ View
hotX9C102SZ X9400WS24 Intersil, IC DCP QUAD 10K 64TP 24SOIC, 24-SOIC (0.295", 7.50mm Width), XDCP™ View
hotX9C102SZ X9315WSI-2.7 Intersil, IC DIGITAL POT 10K 32TP 8SOIC, 8-SOIC (0.154", 3.90mm Width), XDCP™ View
hotX9C102SZ X9118TV14I Intersil, IC DCP 100K 1024TP 14TSSOP, 14-TSSOP (0.173", 4.40mm Width), XDCP™ View
hotX9C102SZ HIP4083AB Renesas Electronics America, IC DRIVER HISIDE N-CH 3PH 16SOIC, 16-SOIC (0.154", 3.90mm Width), XDCP™ View
hotX9C102SZ X9408WV24-2.7T1 Renesas Electronics America, IC XDCP QUAD 64-TAP 10K 24-TSSOP, 24-TSSOP (0.173", 4.40mm Width), XDCP™ View
hotX9C102SZ X9315TMT1 Renesas Electronics America, IC XDCP 32-TAP 100K 3WIRE 8-MSOP, 8-TSSOP, 8-MSOP (0.118", 3.00mm Width), XDCP™ View

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