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XC17256ELPD8C

hot XC17256ELPD8C

XC17256ELPD8C

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Part Number XC17256ELPD8C
Manufacturer Xilinx Inc.
Description IC 3V SER CFG PROM 256K 8-DIP
Datasheet XC17256ELPD8C Datasheet
Package 8-DIP (0.300", 7.62mm)
In Stock 1360 piece(s)
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XC17256ELPD8C Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Memory - Configuration Proms for FPGAs
Datasheet XC17256ELPD8C Datasheet
Package8-DIP (0.300", 7.62mm)
Series-
Programmable TypeOTP
Memory Size256Kb
Voltage - Supply3 V ~ 3.6 V
Operating Temperature0°C ~ 70°C
Package / Case8-DIP (0.300", 7.62mm)
Supplier Device Package8-PDIP

XC17256ELPD8C Datasheet

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DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 1 © Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx® FPGAs • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple bitstreams • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • XC17128E/EL, XC17256E/EL, XC1701, and XC1700L series support fast configuration • Low-power CMOS floating-gate process • XC1700E series are available in 5V and 3.3V versions • XC1700L series are available in 3.3V only • Available in compact plastic packages: 8-pin SOIC, 8- pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44- pin PLCC or 44-pin VQFP • Programming support by leading programmer manufacturers • Design support using the Xilinx Alliance and Foundation™ software packages • Guaranteed 20 year life data retention • Lead-free (Pb-free) packaging available Description The XC1700 family of configuration PROMs provides an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. See Figure 1 for a simplified block diagram. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. After configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation software compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers. < B L XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 8 Product Specification R X-Ref Target - Figure 1 Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit) EPROM Cell Matrix Address Counter CE DATA OEOutput CLK VCC VPP GND DS027_01_021500 TC OE RESET/ OE/ RESET or CEO Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 2 R Pin Description DATA Data output is in a high-impedance state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin. CE When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. CEO Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO follows CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! VCC and GND Positive supply and ground pins. PROM Pinouts Pins not listed are "no connects." " Capacity Pin Name 8-pin PDIP (PD8/ PDG8) SOIC (SO8/ SOG8) VOIC (VO8/ VOG8) 20-pin SOIC (SO20) 20-pin PLCC (PC20/ PCG20) 44-pin VQFP (VQ44) 44-pin PLCC (PC44) DATA 1 1 2 40 2 CLK 2 3 4 43 5 RESET/OE (OE/RESET) 3 8 6 13 19 CE 4 10 8 15 21 GND 5 11 10 18, 41 24, 3 CEO 6 13 14 21 27 VPP 7 18 17 35 41 VCC 8 20 20 38 44 Devices Configuration Bits XC1704L 4,194,304 XC1702L 2,097,152 XC1701/L 1,048,576 XC17512L 524,288 XC1736E 36,288 XC1765E/EL 65,536 XC17128E/EL 131,072 XC17256E/EL 262,144 Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 3 R Pinout Diagrams 6 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 39 38 37 36 35 34 33 32 31 30 29 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 7 8 9 10 11 12 13 14 15 16 17 PC44 Top View NC NC NC NC NC NC NC NC NC NC NC N C R E S E T /O E N C C E N C N C G N D N C N C C E O N C N C C L K N C G N D D A T A (D 0 ) N C V C C N C N C V P P N C DS027_05_090602 NC NC NC NC NC NC NC NC NC NC NC PD8/PDG8 VO8/VOG8 SO8/SOG8 Top View DS027_06_060705 VCC VPP CEO GND DATA(D0) CLK OE/RESET CE 8 7 6 5 1 2 3 4 VQ44 Top View NC NC NC NC NC NC NC NC NC NC NC N C R E S E T /O E N C C E N C N C G N D N C N C C E O N C N C C L K N C G N D D A T A (D 0 ) N C V C C N C N C V P P N C DS027_07_090602 NC NC NC NC NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 33 32 31 30 29 28 27 26 25 24 23 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 DS027_08_110102 SO20 Top View VCC NC VPP NC NC NC NC CEO NC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DATA(D0) NC CLK NC NC NC NC OE/RESET NC CE PC20/PCG20 Top View DS027_09_060705 3 2 1 2 0 1 9 18 17 16 15 14 9 1 0 1 1 1 2 1 3 4 5 6 7 8 N C D A T A (D 0 ) N C V C C N C NC VPP NC NC CEO N C G N D N C N C N C CLK NC OE/RESET NC CE 6 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 N C R E S E T /O E N C C E N C N C G N D N C N C C E O N C N C C L K N C G N D D A T A (D 0 ) N C V C C N C N C V P P N C N C R E S E T /O E N C C E N C N C G N D N C N C C E O N C N C C L K N C G N D D A T A (D 0 ) N C V C C N C N C V P P N C 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 3 2 1 2 0 1 9 9 1 0 1 1 1 2 1 3 N C D A T A (D 0 ) N C V C C N C N C G N D N C N C N C Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 4 R Xilinx FPGAs and Compatible PROMs Controlling PROMs Connecting the FPGA device with the PROM: • The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). • The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal power- on-reset is always in step with the FPGA’s internal power-on-reset. This may not be a safe assumption. • The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. • The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Device Configuration Bits PROM XC4003E 53,984 XC17128E(1) XC4005E 95,008 XC17128E XC4006E 119,840 XC17128E XC4008E 147,552 XC17256E XC4010E 178,144 XC17256E XC4013E 247,968 XC17256E XC4020E 329,312 XC1701 XC4025E 422,176 XC1701 XC4002XL 61,100 XC17128EL(1) XC4005XL 151,960 XC17256EL XC4010XL 283,424 XC17512L XC4013XL/XLA 393,632 XC17512L XC4020XL/XLA 521,880 XC17512L XC4028XL/XLA 668,184 XC1701L XC4028EX 668,184 XC1701 XC4036EX/XL/XLA 832,528 XC1701L XC4036EX 832,528 XC1701 XC4044XL/XLA 1,014,928 XC1701L XC4052XL/XLA 1,215,368 XC1702L XC4062XL/XLA 1,433,864 XC1702L XC4085XL/XLA 1,924,992 XC1702L XC40110XV 2,686,136 XC1704L XC40150XV 3,373,448 XC1704L XC40200XV 4,551,056 XC1704L + XC17512L XC40250XV 5,433,888 XC1704L+ XC1702L XC5202 42,416 XC1765E XC5204 70,704 XC17128E XC5206 106,288 XC17128E XC5210 165,488 XC17256E XC5215 237,744 XC17256E XCV50 559,200 XC1701L XCV100 781,216 XC1701L XCV150 1,040,096 XC1701L XCV200 1,335,840 XC1702L XCV300 1,751,808 XC1702L XCV400 2,546,048 XC1704L XCV600 3,607,968 XC1704L XCV800 4,715,616 XC1704L + XC1701L XCV1000 6,127,744 XC1704L + XC1702L XCV50E 630,048 XC1701L XCV100E 863,840 XC1701L XCV200E 1,442,016 XC1702L XCV300E 1,875,648 XC1702L XCV400E 2,693,440 XC1704L XCV405E 3,340,400 XC1704L XCV600E 3,961,632 XC1704L XCV812E 6,519,648 2 of XC1704L XCV1000E 6,587,520 2 of XC1704L XCV1600E 8,308,992 2 of XC1704L XCV2000E 10,159,648 3 of XC1704L XCV2600E 12,922,336 4 of XC1704L XCV3200E 16,283,712 4 of XC1704L Notes: 1. The suggested PROM is determined by compatibility with the higher configuration frequency of the Xilinx FPGA CCLK. Designers using the default slow configuration frequency (CCLK) can use the XC1765E or XC1765EL for the noted FPGA devices. Device Configuration Bits PROM Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 5 R FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode- select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor. Programming the FPGA With Counters Unchanged upon Completion When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration is then completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. Cascading Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 2, page 6. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low, assuming the PROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. Programming The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC1700 Control Inputs Control Inputs Internal Address Outputs RESET CE DATA CEO ICC Inactive Low If address < TC(1): increment If address > TC(2): don’t change Active High-Z High Low Active Reduced Active Low Held reset High-Z High Active Inactive High Not changing High-Z(3) High Standby Active High Held reset High-Z(3) High Standby Notes: 1. The XC1700 RESET input has programmable polarity. 2. TC = Terminal Count = highest address value. TC + 1 = address 0. 3. Pull DATA pin to GND or VCC to meet ICCS standby current. Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 6 R X-Ref Target - Figure 2 Figure 2: Master Serial Mode DIN DOUT CCLK INIT DONE PROM DATA CLK CE CE FPGA (Low Resets the Address Pointer) VCC VCC VCC OPTIONAL Daisy-chained FPGAs with Different configurations OPTIONAL Slave FPGAs with Identical Configurations RESET RESET DS027_02_111606 CCLK (Output) DIN DOUT (Output) OE/RESET MODES(1) VPP Cascaded Serial Memory DATA CLK CEO OE/RESET 3.3V 4 .7 K Ω Notes: 1. For mode pin connections, refer to the appropriate FPGA data sheet. 2. The one-time-programmable PROM supports automatic loading of configuration programs. 3. Multiple devices can be cascaded to support additional FPGAs. 4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active. Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 7 R XC1701, XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings Operating Conditions (5V Supply) DC Characteristics Over Operating Condition Symbol Description Conditions Units VCC Supply voltage relative to GND –0.5 to +7.0 V VPP Supply voltage relative to GND –0.5 to +12.5 V VIN Input voltage relative to GND –0.5 to VCC +0.5 V VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C TJ Junction temperature +125 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Symbol Description Min Max Units VCC (1) Supply voltage relative to GND (TA = 0°C to +70°C) Commercial 4.750 5.25 V Supply voltage relative to GND (TA = –40°C to +85°C) Industrial 4.50 5.50 V Notes: 1. During normal read operation VPP must be connect to VCC. Symbol Description Min Max Units VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = –4 mA) Commercial 3.86 – V VOL Low-level output voltage (IOL = +4 mA) – 0.32 V VOH High-level output voltage (IOH = –4 mA) Industrial 3.76 – V VOL Low-level output voltage (IOL = +4 mA) – 0.37 V ICCA Supply current, active mode at maximum frequency (XC1736E, XC1765E, XC17128E, and XC17256E) – 10 mA ICCA Supply current, active mode at maximum frequency (XC1701) – 20 mA ICCS Supply current, standby mode (XC1736E, XC1765E, XC17128E, and XC17256E) – 50(1) μA ICCS Supply current, standby mode (XC1701) – 100(1) μA IL Input or output leakage current –10 10 μA CIN Input capacitance (VIN = GND, f = 1.0 MHz) – 10 pF COUT Output capacitance (VIN = GND, f = 1.0 MHz) – 10 pF Notes: 1. ICCS standby current is specified for DATA pin that is pulled to VCC or GND. Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 8 R XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings Operating Conditions (3V Supply) DC Characteristics Over Operating Condition Symbol Description Conditions Units VCC Supply voltage relative to GND –0.5 to +7.0 V VPP Supply voltage relative to GND –0.5 to +12.5 V VIN Input voltage relative to GND –0.5 to VCC +0.5 V VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Symbol Description Min Max Units VCC (1) Supply voltage relative to GND (TA = 0°C to +70°C) Commercial 3.0 3.6 V Supply voltage relative to GND (TA = –40°C to +85°C) Industrial 3.0 3.6 V Notes: 1. During normal read operation VPP must be connect to VCC. Symbol Description Min Max Units VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = –3 mA) 2.4 – V VOL Low-level output voltage (IOL = +3 mA) – 0.4 V ICCA Supply current, active mode (at maximum frequency) (XC1700L) – 10 mA ICCA Supply current, active mode (at maximum frequency) (XC1765EL, XC17128EL, XC17256EL) – 5 mA ICCS Supply current, standby mode (XC1701L, XC17512L, XC17256L, X1765EL, XC17128EL) – 50(1) μA ICCS Supply current, standby mode (XC1702L, XC1704L) – 350 (1) μA IL Input or output leakage current –10 10 μA CIN Input capacitance (VIN = GND, f = 1.0 MHz) – 10 pF COUT Output capacitance (VIN = GND, f = 1.0 MHz) – 10 pF Notes: 1. ICCS standby current is specified for DATA pin that is pulled to VCC or GND. Product Obsolete or Under Obsolescence

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XC1700E, XC1700EL, and XC1700L Series Configuration PROMs DS027 (v3.5) June 25, 2008 www.xilinx.com Product Specification 9 R AC Characteristics Over Operating Condition Symbol Description XC1701, XC17128E, XC17256E XC17128EL, XC17256EL, XC1704L, XC1702L, XC1701L, XC17512L XC1736E, XC1765E XC1765EL Units Min Max Min Max Min Max Min Max TOE OE to data delay – 25 – 30 – 45 – 40 ns TCE CE to data delay – 45 – 45 – 60 – 60 ns TCAC CLK to data delay – 45 – 45 – 80 – 200 ns TDF CE or OE to data float delay (2,3) – 50 – 50 – 50 – 50 ns TOH Data hold from CE, OE, or CLK (3) 0 – 0 – 0 – 0 – ns TCYC Clock periods 67 – 67 – 100 – 400 – ns TLC CLK Low time (3) 20 – 25 – 50 – 100 – ns THC CLK High time (3) 20 – 25 – 50 – 100 – ns TSCE CE setup time to CLK (to guarantee proper counting) 20 – 25 – 25 – 40 – ns THCE CE hold time to CLK (to guarantee proper counting) 0 – 0 – 0 – 0 – ns THOE OE hold time (guarantees counters are reset) 20 – 25 – 100 – 100 – ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. RESET/OE CE CLK DATA TCE TOE TLC TSCE TSCE THCE THOE TCAC TOH TDF TOH THC DS027_03_021500 TCYC Product Obsolete or Under Obsolescence

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hotXC17256ELPD8C XC17S50ASO20I Xilinx Inc., IC PROM SER 50000 I-TEMP 20-SOIC, 20-SOIC (0.295", 7.50mm Width), - View
hotXC17256ELPD8C XC17S30PD8I Xilinx Inc., IC PROM PROG I-TEMP 5V 8-DIP, 8-DIP (0.300", 7.62mm), - View
hotXC17256ELPD8C XC17S20VO8I Xilinx Inc., IC PROM SER 200K 8-SOIC, 8-SOIC (0.154", 3.90mm Width), - View
hotXC17256ELPD8C XC17S20PD8C Xilinx Inc., IC PROM PROG C-TEMP 5V 8-DIP, 8-DIP (0.300", 7.62mm), - View
hotXC17256ELPD8C XC17512LSO20C Xilinx Inc., IC PROM SER C-TEMP 512K 20-SOIC, 20-SOIC (0.295", 7.50mm Width), - View
hotXC17256ELPD8C XC17256EPC20I Xilinx Inc., IC PROM SER I-TEMP 256K 20-PLCC, 20-LCC (J-Lead), - View
hotXC17256ELPD8C XC1701PC20C Xilinx Inc., IC PROM SER C-TEMP 1K 20-PLCC, 20-LCC (J-Lead), - View
hotXC17256ELPD8C XC17256EPD8C Xilinx Inc., IC SERIAL CFG PROM 256K 8-DIP, 8-DIP (0.300", 7.62mm), - View
hotXC17256ELPD8C XC17128EPC20C Xilinx Inc., IC SERIAL CFG PROM 128K 20-PLCC, 20-LCC (J-Lead), - View

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