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XC3S2000-5FGG676C

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XC3S2000-5FGG676C

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Part Number XC3S2000-5FGG676C
Manufacturer Xilinx Inc.
Description IC FPGA 489 I/O 676FBGA
Datasheet XC3S2000-5FGG676C Datasheet
Package 676-BGA
In Stock 355 piece(s)
Unit Price $ 94.2000 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jul 18 - Jul 23 (Choose Expedited Shipping)
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Part Number # XC3S2000-5FGG676C (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XC3S2000-5FGG676C Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XC3S2000-5FGG676CDatasheet
Package676-BGA
SeriesSpartan?-3
Number of LABs/CLBs5120
Number of Logic Elements/Cells46080
Total RAM Bits737280
Number of I/O489
Number of Gates2000000
Voltage - Supply1.14 V ~ 1.26 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case676-BGA
Supplier Device Package676-FBGA (27x27)

XC3S2000-5FGG676C Datasheet

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DS099 June 27, 2013 www.xilinx.com Product Specification 1 © Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Module 1: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 • Introduction • Features • Architectural Overview • Array Sizes and Resources • User I/O Chart • Ordering Information Module 2: Functional Description DS099 (v3.1) June 27, 2013 • Input/Output Blocks (IOBs) • IOB Overview • SelectIO™ Interface I/O Standards • Configurable Logic Blocks (CLBs) • Block RAM • Dedicated Multipliers • Digital Clock Manager (DCM) • Clock Network • Configuration Module 3: DC and Switching Characteristics DS099 (v3.1) June 27, 2013 • DC Electrical Characteristics • Absolute Maximum Ratings • Supply Voltage Specifications • Recommended Operating Conditions • DC Characteristics • Switching Characteristics • I/O Timing • Internal Logic Timing • DCM Timing • Configuration and JTAG Timing Module 4: Pinout Descriptions DS099 (v3.1) June 27, 2013 • Pin Descriptions • Pin Behavior During Configuration • Package Overview • Pinout Tables • Footprints 1 Spartan-3 FPGA Family Data Sheet DS099 June 27, 2013 Product Specification

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DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 2 © Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Introduction The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table 1. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. Features • Low-cost, high-performance logic solution for high-volume, consumer-oriented applications • Densities up to 74,880 logic cells • SelectIO™ interface signaling • Up to 633 I/O pins • 622+ Mb/s data transfer rate per I/O • 18 single-ended signal standards • 8 differential I/O standards including LVDS, RSDS • Termination by Digitally Controlled Impedance • Signal swing ranging from 1.14V to 3.465V • Double Data Rate (DDR) support • DDR, DDR2 SDRAM support up to 333 Mb/s • Logic resources • Abundant logic cells with shift register capability • Wide, fast multiplexers • Fast look-ahead carry logic • Dedicated 18 x 18 multipliers • JTAG logic compatible with IEEE 1149.1/1532 • SelectRAM™ hierarchical memory • Up to 1,872 Kbits of total block RAM • Up to 520 Kbits of total distributed RAM • Digital Clock Manager (up to four DCMs) • Clock skew elimination • Frequency synthesis • High resolution phase shifting • Eight global clock lines and abundant routing • Fully supported by Xilinx ISE® and WebPACK™ software development systems • MicroBlaze™ and PicoBlaze™ processor, PCI®, PCI Express® PIPE Endpoint, and other IP cores • Pb-free packaging options • Automotive Spartan-3 XA Family variant 8 Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 Product Specification Table 1: Summary of Spartan-3 FPGA Attributes Device System Gates Equivalent Logic Cells(1) CLB Array (One CLB = Four Slices) Distributed RAM Bits (K=1024) Block RAM Bits (K=1024) Dedicated Multipliers DCMs Max. User I/O Maximum Differential I/O PairsRows Columns Total CLBs XC3S50(2) 50K 1,728 16 12 192 12K 72K 4 2 124 56 XC3S200(2) 200K 4,320 24 20 480 30K 216K 12 4 173 76 XC3S400(2) 400K 8,064 32 28 896 56K 288K 16 4 264 116 XC3S1000(2) 1M 17,280 48 40 1,920 120K 432K 24 4 391 175 XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221 XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270 XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300 XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 633 300 Notes: 1. Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness. 2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 3 Architectural Overview The Spartan-3 family architecture consists of five fundamental programmable functional elements: • Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. • Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. • Block RAM provides data storage in the form of 18-Kbit dual-port blocks. • Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. • Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several 18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer block RAM columns. The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust reprogrammable static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying X-Ref Target - Figure 1 Figure 1: Spartan-3 Family Architecture DS099-1_01_032703 Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 has only the block RAM column on the far left.

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 4 power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit-wide SelectMAP port. The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial configuration. I/O Capabilities The SelectIO feature of Spartan-3 devices supports eighteen single-ended standards and eight differential standards as listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal reflections. Table 2: Signal Standards Supported by the Spartan-3 Family Standard Category Description VCCO (V) Class Symbol (IOSTANDARD) DCI Option Single-Ended GTL Gunning Transceiver Logic N/A Terminated GTL Yes Plus GTLP Yes HSTL High-Speed Transceiver Logic 1.5 I HSTL_I Yes III HSTL_III Yes 1.8 I HSTL_I_18 Yes II HSTL_II_18 Yes III HSTL_III_18 Yes LVCMOS Low-Voltage CMOS 1.2 N/A LVCMOS12 No 1.5 N/A LVCMOS15 Yes 1.8 N/A LVCMOS18 Yes 2.5 N/A LVCMOS25 Yes 3.3 N/A LVCMOS33 Yes LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A LVTTL No PCI Peripheral Component Interconnect 3.0 33 MHz(1) PCI33_3 No SSTL Stub Series Terminated Logic 1.8 N/A (±6.7 mA) SSTL18_I Yes N/A (±13.4 mA) SSTL18_II No 2.5 I SSTL2_I Yes II SSTL2_II Yes Differential LDT (ULVDS) Lightning Data Transport (HyperTransport™) Logic 2.5 N/A LDT_25 No LVDS Low-Voltage Differential Signaling Standard LVDS_25 Yes Bus BLVDS_25 No Extended Mode LVDSEXT_25 Yes LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A LVPECL_25 No RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No HSTL Differential High-Speed Transceiver Logic 1.8 II DIFF_HSTL_II_18 Yes SSTL Differential Stub Series Terminated Logic 2.5 II DIFF_SSTL2_II Yes Notes: 1. 66 MHz PCI is not supported by the Xilinx IP core although PCI66_3 is an available I/O standard.

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 5 Table 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Package Marking Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for Spartan-3 FPGAs in the CP132 and CPG132 packages. The “5C” and “4I” part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Some specifications vary according to mask revision. Mask revision E devices are errata-free. All shipments since 2006 have been mask revision E. Table 3: Spartan-3 Device I/O Chart Available User I/Os and Differential (Diff) I/O Pairs by Package Type Package VQ100 VQG100 CP132(1) CPG132 TQ144 TQG144 PQ208 PQG208 FT256 FTG256 FG320 FGG320 FG456 FGG456 FG676 FGG676 FG900 FGG900 FG1156(1) FGG1156 Footprint (mm) 16 x 16 8 x 8 22 x 22 30.6 x 30.6 17 x 17 19 x 19 23 x 23 27 x 27 31 x 31 35 x 35 Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff XC3S50 63 29 89(1) 44(1) 97 46 124 56 – – – – – – – – – – – – XC3S200 63 29 – – 97 46 141 62 173 76 – – – – – – – – – – XC3S400 – – – – 97 46 141 62 173 76 221 100 264 116 – – – – – – XC3S1000 – – – – – – – – 173 76 221 100 333 149 391 175 – – – – XC3S1500 – – – – – – – – – – 221 100 333 149 487 221 – – – – XC3S2000 – – – – – – – – – – – – 333 149 489 221 565 270 – – XC3S4000 – – – – – – – – – – – – – – 489 221 633 300 712(1) 312(1) XC3S5000 – – – – – – – – – – – – – – 489 221 633 300 784(1) 344(1) Notes: 1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm. 2. All device options listed in a given package column are pin-compatible. 3. User = Single-ended user I/O pins. Diff = Differential I/O pairs. X-Ref Target - Figure 2 Figure 2: Spartan-3 FPGA QFP Package Marking Example for Part Number XC3S400-4PQ208C DS099-1_03_050305 Lot Code Date Code Mask Revision Code Process Technology XC3S400 TM PQ208EGQ0525 D1234567A 4C SPARTAN Device Type Package Speed Grade Temperature Range Fabrication Code Pin P1 R R

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 6 Ordering Information Spartan-3 FPGAs are available in both standard (Figure 5) and Pb-free (Figure 6) packaging options for all device/package combinations. The Pb-free packages include a special ‘G’ character in the ordering code. For additional information on Pb-free packaging, see XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. X-Ref Target - Figure 3 Figure 3: Spartan-3 FPGA BGA Package Marking Example for Part Number XC3S1000-4FT256C X-Ref Target - Figure 4 Figure 4: Spartan-3 FPGA CP132 and CPG132 Package Marking Example for XC3S50-4CP132C X-Ref Target - Figure 5 Figure 5: Standard Packaging X-Ref Target - Figure 6 Figure 6: Pb-Free Packaging DS099-1_04_050305 Lot Code Date Code XC3S1000TM 4C SPARTAN Device Type BGA Ball A1 Package Speed Grade Temperature Range R R FT256EGQ0525 D1234567A Mask Revision Code Process Code Fabrication Code DS099-1_05_092712 Date Code Temperature Range Speed Grade 3S50 C5-EGQ 4C Device TypeBall A1 Lot Code Package C5 = CP132 C6 = CPG132 Mask Revision Code Fabrication Code F12345 -0525 PHILIPPINES Process Code XC3S50 -4 PQ 208 C Device Type Speed Grade Temperature Range: C = Commercial (Tj = 0°C to 85°C) I = Industrial (Tj = –40°C to +100°C) Package Type Number of Pins Example: DS099_1_05_020711 XC3S50 -4 PQ G 208 C Device Type Speed Grade Temperature Range: Package Type Number of Pins Pb-free Example: C = Commercial (Tj = 0°C to 85°C) I = Industrial (Tj = –40°C to +100°C) DS099_1_06_020711

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 7 Revision History Table 4: Example Ordering Information Device Speed Grade Package Type/Number of Pins Temperature Range (Tj) XC3S50 -4 Standard Performance VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C) XC3S200 -5 High Performance(1) CP(G)132(2) 132-pin Chip-Scale Package (CSP) I Industrial (–40°C to 100°C) XC3S400 TQ(G)144 144-pin Thin Quad Flat Pack (TQFP) XC3S1000 PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP) XC3S1500 FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) XC3S2000 FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA) XC3S4000 FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA) XC3S5000 FG(G)676 676-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)900 900-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)1156(2) 1156-ball Fine-Pitch Ball Grid Array (FBGA) Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. 2. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See http://www.xilinx.com/support/documentation/spartan-3_customer_notices.htm. Date Version Description 04/11/2003 1.0 Initial Xilinx release. 04/24/2003 1.1 Updated block RAM, DCM, and multiplier counts for the XC3S50. 12/24/2003 1.2 Added the FG320 package. 07/13/2004 1.3 Added information on Pb-free packaging options. 01/17/2005 1.4 Referenced Spartan-3 XA Automotive FPGA families in Table 1. Added XC3S50CP132, XC3S2000FG456, XC3S4000FG676 options to Table 3. Updated Package Marking to show mask revision code, fabrication facility code, and process technology code. 08/19/2005 1.5 Added package markings for BGA packages (Figure 3) and CP132/CPG132 packages (Figure 4). Added differential (complementary single-ended) HSTL and SSTL I/O standards. 04/03/2006 2.0 Increased number of supported single-ended and differential I/O standards. 04/26/2006 2.1 Updated document links. 05/25/2007 2.2 Updated Package Marking to allow for dual-marking. 11/30/2007 2.3 Added XC3S5000 FG(G)676 to Table 3. Noted that FG(G)1156 package is being discontinued and updated max I/O count. 06/25/2008 2.4 Updated max I/O counts based on FG1156 discontinuation. Clarified dual mark in Package Marking. Updated formatting and links. 12/04/2009 2.5 CP132 and CPG132 packages are being discontinued. Added link to Spartan-3 FPGA customer notices. Updated Table 3 with package footprint dimensions. 10/29/2012 3.0 Added Notice of Disclaimer section. Per XCN07022, updated the discontinued FG1156 and FGG1156 package discussion throughout document. Per XCN08011, updated the discontinued CP132 and CPG132 package discussion throughout document. Although the package is discontinued, updated the marking on Figure 4. This product is not recommended for new designs. 06/27/2013 3.1 Removed banner. This product IS recommended for new designs.

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Spartan-3 FPGA Family: Introduction and Ordering Information DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 8 Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. CRITICAL APPLICATIONS DISCLAIMER XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR. CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. AUTOMOTIVE APPLICATIONS DISCLAIMER XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

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DS099 (v3.1) June 27, 2013 www.xilinx.com Product Specification 9 © Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. Spartan-3 FPGA Design Documentation The functionality of the Spartan®-3 FPGA family is described in the following documents. The topics covered in each guide are listed. • UG331: Spartan-3 Generation FPGA User Guide • Clocking Resources • Digital Clock Managers (DCMs) • Block RAM • Configurable Logic Blocks (CLBs) - Distributed RAM - SRL16 Shift Registers - Carry and Arithmetic Logic • I/O Resources • Embedded Multiplier Blocks • Programmable Interconnect • ISE® Software Design Tools • IP Cores • Embedded Processing and Control Solutions • Pin Types and Package Overview • Package Drawings • Powering FPGAs • UG332: Spartan-3 Generation Configuration User Guide • Configuration Overview - Configuration Pins and Behavior - Bitstream Sizes • Detailed Descriptions by Mode - Master Serial Mode using Xilinx Platform Flash PROM - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor - JTAG Mode • ISE iMPACT Programming Examples Create a Xilinx user account and sign up to receive automatic e-mail notification whenever this data sheet or the associated user guides are updated. • Sign Up for Alerts on Xilinx.com https://secure.xilinx.com/webreg/register.do ?group=myprofile&languageID=1 For specific hardware examples, see the Spartan-3 FPGA Starter Kit board web page, which has links to various design examples and the user guide. • Spartan-3 FPGA Starter Kit Board page http://www.xilinx.com/s3starter • UG130: Spartan-3 FPGA Starter Kit User Guide 57 Spartan-3 FPGA Family: Functional Description DS099 (v3.1) June 27, 2013 Product Specification

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XC3S2000-5FGG676C

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Heisener's commitment to quality has shaped our processes for sourcing, testing, shipping, and every step in between. This foundation underlies each component we sell.

ISO9001:2015, ICAS, IAF, UKAS

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