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XC7VX690T-1FFG1927I

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XC7VX690T-1FFG1927I

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Part Number XC7VX690T-1FFG1927I
Manufacturer Xilinx Inc.
Description IC FPGA 600 I/O 1927FCBGA
Datasheet XC7VX690T-1FFG1927I Datasheet
Package 1924-BBGA, FCBGA
In Stock 409 piece(s)
Unit Price $ 9,763.0000 *
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 2 - Dec 7 (Choose Expedited Shipping)
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Part Number # XC7VX690T-1FFG1927I (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XC7VX690T-1FFG1927I Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XC7VX690T-1FFG1927IDatasheet
Package1924-BBGA, FCBGA
SeriesVirtex?-7 XT
Number of LABs/CLBs54150
Number of Logic Elements/Cells693120
Total RAM Bits54190080
Number of I/O600
Number of Gates-
Voltage - Supply0.97 V ~ 1.03 V
Mounting TypeSurface Mount
Operating Temperature-40°C ~ 100°C (TJ)
Package / Case1924-BBGA, FCBGA
Supplier Device Package1927-FCBGA (45x45)

XC7VX690T-1FFG1927I Datasheet

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DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 1 © 2011–2017 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Zynq, Spartan, ISE, Vivado and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Introduction Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and -2L speed grades, with -3 having the highest performance. The -2L devices operate at VCCINT = 1.0V and are screened for lower maximum static power. The speed specification of a -2L device is the same as the -2 speed grade. The -2G speed grade is available in devices utilizing Stacked Silicon Interconnect (SSI) technology. The -2G speed grade supports 12.5 Gb/s GTX or 13.1 Gb/s GTH transceivers as well as the standard -2 speed grade specifications. Virtex-7 T and XT FPGA DC and AC characteristics are specified in commercial, extended, industrial, and military temperature ranges. Except for the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1M speed grade military device are the same as for a -1C speed grade commercial device). However, only selected speed grades and/or devices are available in each temperature range. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. Available device and package combinations can be found in: • 7 Series FPGAs Overview (DS180) • Defense-Grade 7 Series FPGAs Overview (DS185) This Virtex-7 T and XT FPGA data sheet, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website at www.xilinx.com/7. DC Characteristics Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 Product Specification Table 1: Absolute Maximum Ratings(1) Symbol Description Min Max Units FPGA Logic VCCINT Internal supply voltage –0.5 1.1 V VCCAUX Auxiliary supply voltage –0.5 2.0 V VCCBRAM Supply voltage for the block RAM memories –0.5 1.1 V VCCO Output drivers supply voltage for 3.3V HR I/O banks –0.5 3.6 V Output drivers supply voltage for 1.8V HP I/O banks –0.5 2.0 V VCCAUX_IO Auxiliary supply voltage –0.5 2.06 V VREF Input reference voltage –0.5 2.0 V VIN (2)(3)(4) I/O input voltage for 3.3V HR I/O banks –0.40 VCCO + 0.55 V I/O input voltage for 1.8V HP I/O banks –0.55 VCCO + 0.55 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(5) –0.40 2.625 V VCCBATT Key memory battery backup supply –0.5 2.0 V GTX and GTH Transceivers VMGTAVCC Analog supply voltage for the GTX/GTH transmitter and receiver circuits –0.5 1.1 V VMGTAVTT Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits –0.5 1.32 V VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers –0.5 1.935 V VMGTREFCLK GTX/GTH transceiver reference clock absolute input voltage –0.5 1.32 V Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 2 VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTX/GTH transceiver column –0.5 1.32 V VIN Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage –0.5 1.26 V IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating – 14 mA IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT – 12 mA IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND – 6.5 mA IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating – 14 mA IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT – 12 mA XADC VCCADC XADC supply relative to GNDADC –0.5 2.0 V VREFP XADC reference input relative to GNDADC –0.5 2.0 V Temperature TSTG Storage temperature (ambient) –65 150 °C TSOL Maximum soldering temperature for Pb/Sn component bodies(6) – +220 °C Maximum soldering temperature for Pb-free component bodies(6) – +260 °C Tj Maximum junction temperature (6) – +125 °C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. The lower absolute voltage specification always applies. 3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide (UG471). 4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4 and Table 5. 5. See Table 10 for TMDS_33 specifications. 6. For soldering guidelines and thermal considerations, see the 7 Series FPGA Packaging and Pinout Specification (UG475). Table 2: Recommended Operating Conditions(1)(2) Symbol Description Min Typ Max Units FPGA Logic VCCINT (3) Internal supply voltage 0.97 1.00 1.03 V Internal supply voltage for -1C devices with voltage identification (VID) bit programmed to run at 0.9V typical(4). 0.87 0.90 0.93 V VCCBRAM (3) Block RAM supply voltage 0.97 1.00 1.03 V Block RAM supply voltage for -1C devices with voltage identification (VID) bit programmed to run at 0.9V typical(4). 0.87 0.90 1.03 V VCCAUX Auxiliary supply voltage 1.71 1.80 1.89 V VCCO (5)(6) Supply voltage for 3.3V HR I/O banks 1.14 – 3.465 V Supply voltage for 1.8V HP I/O banks 1.14 – 1.89 V VCCAUX_IO (7) Auxiliary supply voltage when set to 1.8V 1.71 1.80 1.89 V Auxiliary supply voltage when set to 2.0V 1.94 2.00 2.06 V VIN (8) I/O input voltage –0.20 – VCCO + 0.2 V I/O input voltage (when VCCO = 3.3V) for VREF and differential I/O standards except TMDS_33(9) –0.20 – 2.625 V IIN (10) Maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. – – 10 mA Table 1: Absolute Maximum Ratings(1) (Cont’d) Symbol Description Min Max Units Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 3 VCCBATT (11) Battery voltage 1.0 – 1.89 V GTX and GTH Transceivers VMGTAVCC (12) Analog supply voltage for the GTX/GTH transceiver QPLL frequency range ≤ 10.3125 GHz(13)(14) 0.97 1.0 1.08 V Analog supply voltage for the GTX/GTH transceiver QPLL frequency range > 10.3125 GHz 1.02 1.05 1.08 V VMGTAVTT (12) Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits 1.17 1.2 1.23 V VMGTVCCAUX (12) Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers 1.75 1.80 1.85 V VMGTAVTTRCAL (12) Analog supply voltage for the resistor calibration circuit of the GTX/GTH transceiver column 1.17 1.2 1.23 V XADC VCCADC XADC supply relative to GNDADC 1.71 1.80 1.89 V VREFP Externally supplied reference voltage 1.20 1.25 1.30 V Temperature Tj Junction temperature operating range for commercial (C) temperature devices 0 – 85 °C Junction temperature operating range for extended (E) temperature devices 0 – 100 °C Junction temperature operating range for industrial (I) temperature devices –40 – 100 °C Junction temperature operating range for military (M) temperature devices –55 – 125 °C Notes: 1. All voltages are relative to ground. 2. For the design of the power distribution system, consult the 7 Series FPGAs PCB Design and Pin Planning Guide (UG483). 3. VCCINT and VCCBRAM should be connected to the same supply. 4. For more information on the VID bit see the Lowering Power using the Voltage Identification Bit application note (XAPP555). 5. Configuration data is retained even if VCCO drops to 0V. 6. Includes VCCO of 1.2V, 1.35V, 1.5V, 1.8V, 2.5V (HR I/O only), 3.3V (HR I/O only) at ±5%. 7. For more information, refer to the VCCAUX_IO section of 7 Series FPGAs SelectIO Resources User Guide (UG471). 8. The lower absolute voltage specification always applies. 9. See Table 10 for TMDS_33 specifications. 10. A total of 200 mA per bank should not be exceeded. 11. VCCBATT is required only when using bitstream encryption. If battery is not used, connect VCCBATT to either ground or VCCAUX. 12. Each voltage listed requires the filter circuit described in the 7 Series FPGAs GTX/GTH Transceiver User Guide (UG476). 13. For data rates ≤ 10.3125 Gb/s, VMGTAVCC should be 1.0V ±3% for lower power consumption. 14. For lower power consumption, VMGTAVCC should be 1.0V ±3% over the entire CPLL frequency range. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ(1) Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.75 – – V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 1.5 – – V IREF VREF leakage current per pin – – 15 µA IL Input or output leakage current per pin (sample-tested) – – 15 µA CIN (2) Die input capacitance at the pad – – 8 pF Table 2: Recommended Operating Conditions(1)(2) (Cont’d) Symbol Description Min Typ Max Units Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 4 IRPU Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 90 – 330 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 68 – 250 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 34 – 220 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 23 – 150 µA Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V 12 – 120 µA IRPD Pad pull-down (when selected) @ VIN = 3.3V 68 – 330 µA Pad pull-down (when selected) @ VIN = 1.8V 45 – 180 µA ICCADC Analog supply current, analog circuits in powered up state – – 25 mA IBATT (3) Battery supply current – – 150 nA RIN_TERM (4) Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_40) 28 40 55 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_50) 35 50 65 Ω Thevenin equivalent resistance of programmable input termination to VCCO/2 (UNTUNED_SPLIT_60) 44 60 83 Ω n Temperature diode ideality factor – 1.010 – – r Temperature diode series resistance – 2 – Ω Notes: 1. Typical values are specified at nominal voltage, 25°C. 2. This measurement represents the die capacitance at the pad, not including the package. 3. Maximum value specified for worst case process at 25°C. 4. Termination resistance to a VCCO/2 level. Table 4: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks (1)(2) AC Voltage Overshoot % of UI @–55°C to 125°C AC Voltage Undershoot % of UI @–55°C to 125°C VCCO + 0.55 100 –0.40 100 –0.45 61.7 –0.50 25.8 –0.55 11.0 VCCO + 0.60 46.6 –0.60 4.77 VCCO + 0.65 21.2 –0.65 2.10 VCCO + 0.70 9.75 –0.70 0.94 VCCO + 0.75 4.55 –0.75 0.43 VCCO + 0.80 2.15 –0.80 0.20 VCCO + 0.85 1.02 –0.85 0.09 VCCO + 0.90 0.49 –0.90 0.04 VCCO + 0.95 0.24 –0.95 0.02 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. Table 3: DC Characteristics Over Recommended Operating Conditions (Cont’d) Symbol Description Min Typ(1) Max Units Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 5 Table 5: VIN Maximum Allowed AC Voltage Overshoot and Undershoot for 1.8V HP I/O Banks (1)(2) AC Voltage Overshoot % of UI @–55°C to 125°C AC Voltage Undershoot % of UI @–55°C to 125°C VCCO + 0.55 100 –0.55 100 VCCO + 0.60 50.0 (3) –0.60 50.0(3) VCCO + 0.65 50.0 (3) –0.65 50.0(3) VCCO + 0.70 47.0 –0.70 50.0 (3) VCCO + 0.75 21.2 –0.75 50.0 (3) VCCO + 0.80 9.71 –0.80 50.0 (3) VCCO + 0.85 4.51 –0.85 28.4 VCCO + 0.90 2.12 –0.90 12.7 VCCO + 0.95 1.01 –0.95 5.79 Notes: 1. A total of 200 mA per bank should not be exceeded. 2. The peak voltage of the overshoot or undershoot, and the duration above VCCO + 0.20V or below GND – 0.20V, must not exceed the values in this table. 3. For UI lasting less than 20 µs. Table 6: Typical Quiescent Supply Current Symbol Description Device Speed Grade Units -3 -2G -2 -2L -1 -1M ICCINTQ Quiescent VCCINT supply current XC7V585T 1483 1483 1483 1483 1483 N/A mA XC7V2000T N/A 3756 3756 3756 3756 N/A mA XC7VX330T 1012 1012 1012 1012 1012 N/A mA XC7VX415T 1324 1324 1324 1324 1324 N/A mA XC7VX485T 1578 1578 1578 1578 1578 N/A mA XC7VX550T 2214 2214 2214 2214 2214 N/A mA XC7VX690T 2214 2214 2214 2214 2214 N/A mA XC7VX980T N/A 2580 2580 2580 2580 N/A mA XC7VX1140T N/A 3448 3448 3448 3448 N/A mA XQ7V585T N/A N/A 1483 1483 1483 1483 mA XQ7VX330T N/A N/A 1012 1012 1012 1012 mA XQ7VX485T N/A N/A 1578 1578 1578 1578 mA XQ7VX690T N/A N/A 2214 N/A 2214 N/A mA XQ7VX980T N/A N/A N/A 2580 2580 N/A mA Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 6 ICCOQ Quiescent VCCO supply current XC7V585T 1 1 1 1 1 N/A mA XC7V2000T N/A 1 1 1 1 N/A mA XC7VX330T 1 1 1 1 1 N/A mA XC7VX415T 1 1 1 1 1 N/A mA XC7VX485T 1 1 1 1 1 N/A mA XC7VX550T 1 1 1 1 1 N/A mA XC7VX690T 1 1 1 1 1 N/A mA XC7VX980T N/A 1 1 1 1 N/A mA XC7VX1140T N/A 1 1 1 1 N/A mA XQ7V585T N/A N/A 1 1 1 1 mA XQ7VX330T N/A N/A 1 1 1 1 mA XQ7VX485T N/A N/A 1 1 1 1 mA XQ7VX690T N/A N/A 1 N/A 1 N/A mA XQ7VX980T N/A N/A N/A 1 1 N/A mA ICCAUXQ Quiescent VCCAUX supply current XC7V585T 114 114 114 114 114 N/A mA XC7V2000T N/A 315 315 315 315 N/A mA XC7VX330T 73 73 73 73 73 N/A mA XC7VX415T 88 88 88 88 88 N/A mA XC7VX485T 104 104 104 104 104 N/A mA XC7VX550T 147 147 147 147 147 N/A mA XC7VX690T 147 147 147 147 147 N/A mA XC7VX980T N/A 183 183 183 183 N/A mA XC7VX1140T N/A 250 250 250 250 N/A mA XQ7V585T N/A N/A 114 114 114 114 mA XQ7VX330T N/A N/A 73 73 73 73 mA XQ7VX485T N/A N/A 104 104 104 104 mA XQ7VX690T N/A N/A 147 N/A 147 N/A mA XQ7VX980T N/A N/A N/A 183 183 N/A mA Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units -3 -2G -2 -2L -1 -1M Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 7 ICCAUX_IOQ Quiescent VCCAUX_IO supply current XC7V585T 2 2 2 2 2 N/A mA XC7V2000T N/A 2 2 2 2 N/A mA XC7VX330T 2 2 2 2 2 N/A mA XC7VX415T 2 2 2 2 2 N/A mA XC7VX485T 2 2 2 2 2 N/A mA XC7VX550T 2 2 2 2 2 N/A mA XC7VX690T 2 2 2 2 2 N/A mA XC7VX980T N/A 2 2 2 2 N/A mA XC7VX1140T N/A 2 2 2 2 N/A mA XQ7V585T N/A N/A 2 2 2 2 mA XQ7VX330T N/A N/A 2 2 2 2 mA XQ7VX485T N/A N/A 2 2 2 2 mA XQ7VX690T N/A N/A 2 N/A 2 N/A mA XQ7VX980T N/A N/A N/A 2 2 N/A mA ICCBRAMQ Quiescent VCCBRAM supply current XC7V585T 34 34 34 34 34 N/A mA XC7V2000T N/A 56 56 56 56 N/A mA XC7VX330T 32 32 32 32 32 N/A mA XC7VX415T 38 38 38 38 38 N/A mA XC7VX485T 44 44 44 44 44 N/A mA XC7VX550T 63 63 63 63 63 N/A mA XC7VX690T 63 63 63 63 63 N/A mA XC7VX980T N/A 65 65 65 65 N/A mA XC7VX1140T N/A 81 81 81 81 N/A mA XQ7V585T N/A N/A 34 34 34 34 mA XQ7VX330T N/A N/A 32 32 32 32 mA XQ7VX485T N/A N/A 44 44 44 44 mA XQ7VX690T N/A N/A 63 N/A 63 N/A mA XQ7VX980T N/A N/A N/A 65 65 N/A mA Notes: 1. Typical values are specified at nominal voltage, 85°C junction temperatures (Tj) with single-ended SelectIO resources. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to estimate static power consumption for conditions other than those specified. Table 6: Typical Quiescent Supply Current (Cont’d) Symbol Description Device Speed Grade Units -3 -2G -2 -2L -1 -1M Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 8 Power-On/Off Power Supply Sequencing The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on sequence. If VCCINT and VCCBRAM have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. If VCCAUX, VCCAUX_IO, and VCCO have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. For VCCO voltages of 3.3V in HR I/O banks and configuration bank 0: • The voltage difference between VCCO and VCCAUX must not exceed 2.625V for longer than TVCCO2VCCAUX for each power-on/off cycle to maintain device reliability levels. • The TVCCO2VCCAUX time can be allocated in any percentage between the power-on and power-off ramps. The recommended power-on sequence to achieve minimum current draw for the GTX/GTH transceivers is VCCINT, VMGTAVCC, VMGTAVTT OR VMGTAVCC, VCCINT, VMGTAVTT. There is no recommended sequencing for VMGTVCCAUX. Both VMGTAVCC and VCCINT can be ramped simultaneously. The recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. If these recommended sequences are not met, current drawn from VMGTAVTT can be higher than specifications during power- up and power-down. • When VMGTAVTT is powered before VMGTAVCC and VMGTAVTT – VMGTAVCC > 150 mV and VMGTAVCC < 0.7V, the VMGTAVTT current draw can increase by 460 mA per transceiver during VMGTAVCC ramp up. The duration of the current draw can be up to 0.3 x TMGTAVCC (ramp time from GND to 90% of VMGTAVCC). The reverse is true for power-down. • When VMGTAVTT is powered before VCCINT and VMGTAVTT – VCCINT > 150 mV and VCCINT < 0.7V, the VMGTAVTT current draw can increase by 50 mA per transceiver during VCCINT ramp up. The duration of the current draw can be up to 0.3 x TVCCINT (ramp time from GND to 90% of VCCINT). The reverse is true for power-down. There is no recommended sequence for supplies not shown. Send Feedback

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Virtex-7 T and XT FPGAs Data Sheet: DC and AC Switching Characteristics DS183 (v1.27) April 6, 2017 www.xilinx.com Product Specification 9 Table 7 shows the minimum current, in addition to ICCQ, that is required by Virtex-7 T and XT devices for proper power-on and configuration. If the current minimums shown in Table 6 and Table 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. The FPGA must not be configured until after VCCINT is applied. Once initialized and configured, use the Xilinx Power tools to estimate current drain on these supplies. Table 7: Power-On Current for Virtex-7 T and XT Devices Device ICCINTMIN ICCAUXMIN ICCOMIN ICCAUX_IO ICCBRAM Units XC7V585T ICCINTQ + 2700 ICCAUXQ + 40 ICCOQ + 60 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA XC7V2000T ICCINTQ + 4000 ICCAUXQ + 80 ICCOQ + 60 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 176 mA XC7VX330T ICCINTQ + 1000 ICCAUXQ + 65 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 95 mA XC7VX415T ICCINTQ + 1200 ICCAUXQ + 75 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 115 mA XC7VX485T ICCINTQ + 1200 ICCAUXQ + 80 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 140 mA XC7VX550T ICCINTQ + 3300 ICCAUXQ + 143 ICCOQ + 40 mA per bank ICCOAUXIOQ + 57 mA per bank ICCBRAMQ + 200 mA XC7VX690T ICCINTQ + 3300 ICCAUXQ + 143 ICCOQ + 40 mA per bank ICCOAUXIOQ + 57 mA per bank ICCBRAMQ + 200 mA XC7VX980T ICCINTQ + 6500 ICCAUXQ + 202 ICCOQ + 40 mA per bank ICCOAUXIOQ + 60 mA per bank ICCBRAMQ + 204 mA XC7VX1140T ICCINTQ + 8000 ICCAUXQ + 235 ICCOQ + 40 mA per bank ICCOAUXIOQ + 63 mA per bank ICCBRAMQ + 256 mA XQ7V585T ICCINTQ + 2700 ICCAUXQ + 40 ICCOQ + 60 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 108 mA XQ7VX330T ICCINTQ + 1000 ICCAUXQ + 65 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 95 mA XQ7VX485T ICCINTQ + 1200 ICCAUXQ + 80 ICCOQ + 40 mA per bank ICCOAUXIOQ + 40 mA per bank ICCBRAMQ + 140 mA XQ7VX690T ICCINTQ + 3300 ICCAUXQ + 143 ICCOQ + 40 mA per bank ICCOAUXIOQ + 57 mA per bank ICCBRAMQ + 200 mA XQ7VX980T ICCINTQ + 6500 ICCAUXQ + 202 ICCOQ + 40 mA per bank ICCOAUXIOQ + 60 mA per bank ICCBRAMQ + 204 mA Table 8: Power Supply Ramp Time Symbol Description Conditions Min Max Units TVCCINT Ramp time from GND to 90% of VCCINT 0.2 50 ms TVCCO Ramp time from GND to 90% of VCCO 0.2 50 ms TVCCAUX Ramp time from GND to 90% of VCCAUX 0.2 50 ms TVCCAUX_IO Ramp time from GND to 90% of VCCAUX_IO 0.2 50 ms TVCCBRAM Ramp time from GND to 90% of VCCBRAM 0.2 50 ms TVCCO2VCCAUX Allowed time per power cycle for VCCO – VCCAUX > 2.625V TJ = 125°C (1) – 300 msTJ = 100°C (1) – 500 TJ = 85°C (1) – 800 TMGTAVCC Ramp time from GND to 90% of VMGTAVCC 0.2 50 ms TMGTAVTT Ramp time from GND to 90% of VMGTAVTT 0.2 50 ms TMGTVCCAUX Ramp time from GND to 90% of VMGTVCCAUX 0.2 50 ms Notes: 1. Based on 240,000 power cycles with nominal VCCO of 3.3V or 36,500 power cycles with a worst case VCCO of 3.465V. Send Feedback

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