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XCR3512XL-10FT256I

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XCR3512XL-10FT256I

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Part Number XCR3512XL-10FT256I
Manufacturer Xilinx Inc.
Description IC CPLD 512MC 9NS 256BGA
Datasheet XCR3512XL-10FT256I Datasheet
Package 256-LBGA
In Stock 367 piece(s)
Unit Price $ 109.0003 *
Lead Time Can Ship Immediately
Estimated Delivery Time Jun 8 - Jun 13 (Choose Expedited Shipping)
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Part Number # XCR3512XL-10FT256I (Embedded - CPLDs (Complex Programmable Logic Devices)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XCR3512XL-10FT256I Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - CPLDs (Complex Programmable Logic Devices)
Datasheet XCR3512XL-10FT256IDatasheet
Package256-LBGA
SeriesCoolRunner XPLA3
Programmable TypeIn System Programmable (min 1K program/erase cycles)
Delay Time tpd(1) Max9.0ns
Voltage Supply - Internal2.7 V ~ 3.6 V
Number of Logic Elements/Blocks32
Number of Macrocells512
Number of Gates12000
Number of I/O212
Operating Temperature-40°C ~ 85°C (TA)
Mounting TypeSurface Mount
Package / Case256-LBGA
Supplier Device Package256-FTBGA (17x17)

XCR3512XL-10FT256I Datasheet

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Features • Low power 3.3V 512 macrocell CPLD • 7.0 ns pin-to-pin logic delays • System frequencies up to 135 MHz • 512 macrocells with 12,000 usable gates • Available in small footprint packages - 208-pin PQFP (180 user I/O) - 256-ball FBGA (212 user I/O) - 324-ball FBGA (260 user I/O) • Optimized for 3.3V systems - Ultra low power operation - Typical Standby Current of 18 μA at 25° C - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero Power™ (FZP) CMOS design technology - 3.3V PCI electrical specification compatible outputs (no internal clamp diode on any input or I/O) • Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block • Fast ISP programming times • Port Enable pin for additional I/O • 2.7V to 3.6V supply voltage at industrial grade voltage range • Programmable slew rate control per output • Security bit prevents unauthorized access • Refer to the CoolRunner™ XPLA3 family data sheet (DS012) for architecture description Description The CoolRunner™ XPLA3 XCR3512XL device is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 32 function blocks provide 12,000 usable gates. Pin-to-pin propagation delays are as fast as 7.0 ns with a maximum system frequency of 135 MHz. TotalCMOS Design Technique for Fast Zero Power CoolRunner XPLA3 CPLDs offer a TotalCMOS™ solution, both in process technology and design technique. This fam- ily employs a cascade of CMOS gates to implement its sum of products, instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 show- ing the ICC vs. Frequency of our XCR3512XL TotalCMOS CPLD (data taken with 32 resetable up/down, 16-bit counters at 3.3V, 25°C). 0 XCR3512XL: 512 Macrocell CPLD DS081 (v2.0) March 31, 2006 0 14 Product Specification R Figure 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C 30 270 300 240 210 180 150 120 90 60 0 20 40 60 80 100 120 Frequency (MHz) T y p ic a l IC C ( m A ) Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25°C Frequency (MHz) 0 1 10 20 40 60 80 100 120 Typical ICC (mA) 0.018 2.57 25.5 50.8 100.3 147.9 193.5 237.8 281.6DS081 (v2.0) March 31, 2006 www.xilinx.com 1 Product Specification © 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Page 3

XCR3512XL: 512 Macrocell CPLD R DC Electrical Characteristics Over Recommended Operating Conditions(1) Symbol Parameter Test Conditions Typical Min. Max. Unit VOH(2) Output High voltage VCC = 3.0V to 3.6V, IOH = –8 mA - 2.4 - V VCC = 2.7V to 3.0V, IOH = –8 mA - 2.0 - V IOH = –500 μA - 90% VCC(3) - V VOL Output Low voltage IOL = 8 mA - - 0.4 V IIL Input leakage current VIN = GND or VCC to 5.5V - –10 10 μA IIH I/O High-Z leakage current VIN = GND or VCC to 5.5V - –10 10 μA ICCSB(7) Standby current VCC = 3.6V 32.5 - 100 μA ICC Dynamic current(4,5) f = 1 MHz - - 7 mA f = 50 MHz - - 175 mA CIN Input pin capacitance(6) f = 1 MHz - - 8 pF CCLK Clock input capacitance(6) f = 1 MHz - - 12 pF CI/O I/O pin capacitance(6) f = 1 MHz - - 10 pF Notes: 1. See CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions 2. See Figure 2 for output drive characteristics of the CoolRunner XPLA3 family. 3. This parameter guaranteed by design and characterization, not by testing. 4. See Table 1, Figure 1 for typical values. 5. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing. 6. Typical values, not tested. 7. Typical value at 70° C. Figure 2: Typical I/V Curve for the CoolRunner XPLA3 Family, 25°C 0 0 10 20 30 40 50 60 70 80 90 100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Volts IOL (3.3V) IOH (3.3V) IOH (2.7V) m A DS012_10_0419012 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification

Page 4

XCR3512XL: 512 Macrocell CPLD R AC Electrical Characteristics Over Recommended Operating Conditions(1,2) Symbol Parameter -7 -10 -12 Unit Min. Max. Min. Max. Min. Max. TPD1 Propagation delay time (single p-term) - 7.0 - 9.0 - 10.8 ns TPD2 Propagation delay time (OR array)(3) - 7.5 - 10.0 - 12.0 ns TCO Clock to output (global synchronous pin clock) - 5.0 - 5.8 - 6.9 ns TSUF Setup time (fast input register) 4.0 - 5.0 - 5.0 - ns TSU1(4) Setup time (single p-term) 3.8 - 5.5 - 6.7 - ns TSU2 Setup time (OR array) 4.3 - 6.5 - 7.9 - ns TH(4) Hold time 0 - 0 - 0 - ns TWLH(4) Global Clock pulse width (High or Low) 3.0 - 4.0 - 5.0 - ns TPLH(4) P-term clock pulse width 4.5 - 6.0 - 7.5 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) 4.5 - 6.0 - 7.5 - ns TR(4) Input rise time - 20 - 20 - 20 ns TL(4) Input fall time - 20 - 20 - 20 ns fSYSTEM(4) Maximum system frequency - 135 - 97 - 77 MHz TCONFIG(4 ) Configuration time(5) - 200 - 200 - 200 μs TINIT(4) ISP initialization time - 200 - 200 - 200 μs TPOE(4) P-term OE to output enabled - 9.0 - 11.0 - 13.0 ns TPOD(4) P-term OE to output disabled(6) - 9.0 - 11.0 - 13.0 ns TPCO(4) P-term clock to output - 8.5 - 10.3 - 12.4 ns TPAO(4) P-term set/reset to output valid - 9.0 - 11.0 - 13.0 ns Notes: 1. Specifications measured with one output switching. 2. See the CoolRunner XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 17 mA at 3.6V. 6. Output CL = 5 pF.DS081 (v2.0) March 31, 2006 www.xilinx.com 3 Product Specification

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XCR3512XL: 512 Macrocell CPLD R Internal Timing Parameters(1,2) Symbol Parameter -7 -10 -12 UnitMin. Max. Min. Max. Min. Max. Buffer Delays TIN Input buffer delay - 2.5 - 3.3 - 4.0 ns TFIN Fast input buffer delay - 4.7 - 4.3 - 4.3 ns TGCK Global clock buffer delay - 1.5 - 1.3 - 1.5 ns TOUT Output buffer delay - 2.5 - 3.2 - 3.8 ns TEN Output buffer enable/disable delay - 4.5 - 5.2 - 6.0 ns Internal Register and Combinatorial Delays TLDI Latch transparent delay - 1.3 - 1.6 - 2.0 ns TSUI Register setup time 0.8 - 1.0 - 1.2 - ns THI Register hold time 0.3 - 0.5 - 0.7 - ns TECSU Register clock enable setup time 2.0 - 2.5 - 3.0 - ns TECHO Register clock enable hold time 3.0 - 4.5 - 5.5 - ns TCOI Register clock to output delay - 1.0 - 1.3 - 1.6 ns TAOI Register async. S/R to output delay - 2.0 - 2.0 - 2.2 ns TRAI Register async. recovery - 5.0 - 7.0 - 8.0 ns TPTCK Product term clock delay - 2.5 - 2.5 - 3.0 ns TLOGI1 Internal logic delay (single p-term) - 2.0 - 2.5 - 3.0 ns TLOGI2 Internal logic delay (PLA OR term) - 2.5 - 3.5 - 4.2 ns Feedback Delays TF ZIA delay - 3.1 - 4.5 - 6.0 ns Time Adders TLOGI3 Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns TUDA Universal delay - 3.5 - 4.0 - 4.0 ns TSLEW Slew rate limited delay - 5.0 - 5.0 - 6.0 ns Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See the CoolRunner XPLA3 family data sheet (DS012) for timing model.4 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification

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XCR3512XL: 512 Macrocell CPLD R Switching Characteristics Figure 3: AC Load Circuit DS023_03_102401 Component Values R1 390Ω R2 390Ω C1 35 pF Measurement S1 S2 TPOE (High) TPOE (Low) TP Open Closed Closed Open Closed Closed VCC VOUT VIN C1 R1 R2 S1 S2 Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH – 300 mV. Figure 4: Derating Curve for TPD2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 7.1 7.2 7.3 7.4 7.5 1 2 4 8 16 DS081_04_120902 Number of Adjacent Outputs Switching (n s ) Figure 5: Voltage Waveform 90% 10% 1.5 ns 1.5 ns DS017_05_042800 +3.0V 0V Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. TR TLDS081 (v2.0) March 31, 2006 www.xilinx.com 5 Product Specification

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XCR3512XL: 512 Macrocell CPLD R Pin Descriptions Table 2: XCR3512XL User I/O Pins PQ208 FT256 FG324 Total User I/O Pins 180 212 260 Table 3: XCR3512XL I/O Pins Function Block Macrocell PQ208 FT256 FG324 1 1 208 C14 C21 1 2 - D13 C20 1 3 207 - B22 1 4 206 A15 B21 1 5 - - - 1 6 - - - 1 7 - - - 1 8 - - - 1 9 - - - 1 10 - - - 1 11 - - - 1 12 - - - 1 13 - - A22 1 14 205 B15 A21 1 15 - B14 B20 1 16 204 C13 C19 2 1 1 E12 D20 2 2 - - C22 2 3 2 A16 D21 2 4 - C15 D22 2 5 - - - 2 6 - - - 2 7 - - - 2 8 - - - 2 9 - - - 2 10 - - - 2 11 - - - 2 12 - - - 2 13 3 B16 E20 2 14 4 D14 F19 2 15 - - E21 2 16 6 D15 E22 3 1 203 A14 B19 3 2 - E11 A20 3 3 202 - C18 3 4 201 A13 B18 3 5 - - - 3 6 - - - 3 7 - - - 3 8 - - - 3 9 - - - 3 10 - - - 3 11 - - - 3 12 - - - 3 13 - D12 A19 3 14 - - D17 3 15 199 B13 A18 3 16 198 C12 C17 4 1 7 E13 F20 4 2 - - F21 4 3 8 C16 F22 4 4 9 F12 G19 4 5 - - - 4 6 - - - 4 7 - - - 4 8 - - - 4 9 - - - 4 10 - - - 4 11 - - - 4 12 - - - 4 13 - - G20 4 14 10 D16 G21 4 15 - E14 G22 4 16 11 E15 H20 Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG3246 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification

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XCR3512XL: 512 Macrocell CPLD R 5 1 197 A12 B17 5 2 - - A17 5 3 196 D11 D16 5 4 - - C16 5 5 - - - 5 6 - - - 5 7 - - - 5 8 - - - 5 9 - - - 5 10 - - - 5 11 - - - 5 12 - - - 5 13 195 A11 B16 5 14 - E10 A16 5 15 194 B12 C15 5 16 193 C11 B15 6 1 12 F13 H21 6 2 - - H22 6 3 13 E16 J19 6 4 - - J20 6 5 - - - 6 6 - - - 6 7 - - - 6 8 - - - 6 9 - - - 6 10 - - - 6 11 - - - 6 12 - - - 6 13 15 F15 J21 6 14 16 G12 J22 6 15 - F14 K19 6 16 17 G15 K20 7 1 192 B11 A15 7 2 - D10 D14 7 3 190 A10 C14 Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 7 4 189(1) C10(1) B14(1) 7 5 - - - 7 6 - - - 7 7 - - - 7 8 - - - 7 9 - - - 7 10 - - - 7 11 - - - 7 12 - - - 7 13 188 - A14 7 14 - - D13 7 15 - A9 C13 7 16 187 D9 B13 8 1 18 G13 K21 8 2 - - K22 8 3 19 F16 L19 8 4 - - L20 8 5 - - - 8 6 - - - 8 7 - - - 8 8 - - - 8 9 - - - 8 10 - - - 8 11 - - - 8 12 - - - 8 13 20 G14 L21 8 14 21 G16 L22 8 15 22 H13 M21 8 16 24 H12 M20 9 1 51 P16 AA21 9 2 - N14 AB22 9 3 49 R16 AA22 9 4 - - Y20 9 5 - - - 9 6 - - - Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324DS081 (v2.0) March 31, 2006 www.xilinx.com 7 Product Specification

Page 9

XCR3512XL: 512 Macrocell CPLD R 9 7 - - - 9 8 - - - 9 9 - - - 9 10 - - - 9 11 - - - 9 12 - - - 9 13 48 M13 Y21 9 14 47 P15 W20 9 15 46 L12 W21 9 16 45 N16 Y22 10 1 52 N13 AB21 10 2 53 R15 Y19 10 3 54 M12 AA20 10 4 - - AB20 10 5 - - - 10 6 - - - 10 7 - - - 10 8 - - - 10 9 - - - 10 10 - - - 10 11 - - - 10 12 - - - 10 13 55 T16 Y18 10 14 56 P14 AA19 10 15 - T15 AB19 10 16 57 P13 W17 11 1 44 M14 W22 11 2 43 M16 V20 11 3 42 L13 V21 11 4 - N15 U19 11 5 - - - 11 6 - - - 11 7 - - - 11 8 - - - 11 9 - - - Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 11 10 - - - 11 11 - - - 11 12 - - - 11 13 - - V22 11 14 40 M15 U20 11 15 39 L16 U21 11 16 38 K12 U22 12 1 58 R14 Y17 12 2 - N12 AA18 12 3 59 T14 AB18 12 4 - - AA17 12 5 - - - 12 6 - - - 12 7 - - - 12 8 - - - 12 9 - - - 12 10 - - - 12 11 - - - 12 12 - - - 12 13 60 M11 AB17 12 14 - R13 W16 12 15 61 P12 Y16 12 16 62 T13 AA16 13 1 37 L15 T19 13 2 - - T20 13 3 36 K13 T21 13 4 35 K16 T22 13 5 - - - 13 6 - - - 13 7 - - - 13 8 - - - 13 9 - - - 13 10 - - - 13 11 - - - 13 12 - - - Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG3248 www.xilinx.com DS081 (v2.0) March 31, 2006 Product Specification

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XCR3512XL: 512 Macrocell CPLD R 13 13 - K14 R20 13 14 34 K15 R21 13 15 33 L14 R22 13 16 31 J16 P19 14 1 64 N11 AB16 14 2 - R12 Y15 14 3 65 T12 AA15 14 4 66 R11 AB15 14 5 - - - 14 6 - - - 14 7 - - - 14 8 - - - 14 9 - - - 14 10 - - - 14 11 - - - 14 12 - - - 14 13 67 M10 W14 14 14 68 P11 Y14 14 15 - - AA14 14 16 69 N10 AB14 15 1 30(1) J13(1) P20(1) 15 2 29 J15 P21 15 3 28 J14 P22 15 4 - - N19 15 5 - - - 15 6 - - - 15 7 - - - 15 8 - - - 15 9 - - - 15 10 - - - 15 11 - - - 15 12 - - - 15 13 27 H16 N21 15 14 - - N22 15 15 26 H14 M22 Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324 15 16 25 H15 M19 16 1 70 T11 W13 16 2 71 R10 Y13 16 3 73 P10 AA13 16 4 - T10 AB13 16 5 - - - 16 6 - - - 16 7 - - - 16 8 - - - 16 9 - - - 16 10 - - - 16 11 - - - 16 12 - - - 16 13 - - W12 16 14 76 N9 AA12 16 15 77 R9 AB12 16 16 78 P9 Y11 17 1 157 B1 C3 17 2 - B2 A2 17 3 158 C3 B3 17 4 - - C4 17 5 - - - 17 6 - - - 17 7 - - - 17 8 - - - 17 9 - - - 17 10 - - - 17 11 - - - 17 12 - - - 17 13 159 D4 B4 17 14 - A2 C5 17 15 160 A1 B5 17 16 161 B3 A3 18 1 156 C1 D3 18 2 155 D3 B2 Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 FT256 FG324DS081 (v2.0) March 31, 2006 www.xilinx.com 9 Product Specification

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Jayd*****layton

May 27, 2020

These are high quality connectors. They work as you would expect them to. There is not much else you can say about them.

Kaliy*****rnandez

May 21, 2020

It's so nice to have all these babies. I was using so many for projects, I decided to buy these. They'll definitely last me a while!

Aleja*****Jackson

May 20, 2020

They work great exactly what I needed.

Jayl*****Bass

May 15, 2020

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May 11, 2020

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Adal*****Greer

May 9, 2020

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Apol*****ccall

May 9, 2020

Quality electronic components plus fast response.Thank you.

Mala***** Kent

May 8, 2020

Awesome buying experience, smooth transmission with the seller, and fast delivery.

Maxim***** Wong

May 2, 2020

They worked great. Not much to say - as far as I can tell they adhere to the specs, and did the job I needed them to. Good transistors for higher current situations.

Glor*****iles

April 18, 2020

Perfectly satisfied with item. Top supplier on my list.

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