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XCS10XL-4VQ100C

hot XCS10XL-4VQ100C

XCS10XL-4VQ100C

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Part Number XCS10XL-4VQ100C
Manufacturer Xilinx Inc.
Description IC FPGA 77 I/O 100VQFP
Datasheet XCS10XL-4VQ100C Datasheet
Package 100-TQFP
In Stock 6978 piece(s)
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XCS10XL-4VQ100C Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XCS10XL-4VQ100C Datasheet
Package100-TQFP
SeriesSpartan?-XL
Number of LABs/CLBs196
Number of Logic Elements/Cells466
Total RAM Bits6272
Number of I/O77
Number of Gates10000
Voltage - Supply3 V ~ 3.6 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case100-TQFP
Supplier Device Package100-VQFP (14x14)

XCS10XL-4VQ100C Datasheet

Page 1

Page 2

Product Obsolete/Under ObsolescenceIntroduction The Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask pro- grammed ASIC devices. By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inher- ent risk of conventional ASICs. The Spartan and Spar- tan-XL families in the Spartan series have ten members, as shown in Table 1. Spartan/Spartan-XL FPGA Features Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheets for more advanced members for the Spartan Series. • First ASIC replacement FPGA for high-volume production with on-chip RAM • Density up to 1862 logic cells or 40,000 system gates • Streamlined feature set based on XC4000 architecture • System performance beyond 80 MHz • Broad set of AllianceCORE and LogiCORE™ predefined solutions available • Unlimited reprogrammability • Low cost • System level features - Available in both 5V and 3.3V versions - On-chip SelectRAM™ memory - Fully PCI compliant - Full readback capability for program verification and internal node observability - Dedicated high-speed carry logic - Internal 3-state bus capability - Eight global low-skew clock or signal networks - IEEE 1149.1-compatible Boundary Scan logic - Low cost plastic packages available in all densities - Footprint compatibility in common packages • Fully supported by powerful Xilinx ISE® Classics development system - Fully automatic mapping, placement and routing Additional Spartan-XL Family Features • 3.3V supply for low power with 5V tolerant I/Os • Power down input • Higher performance • Faster carry logic • More flexible high-speed clock network • Latch capability in Configurable Logic Blocks • Input fast capture latch • Optional MUX or 2-input function generator on outputs • 12 mA or 24 mA output drive • 5V and 3.3V PCI compliant • Enhanced Boundary Scan • Express Mode configuration • 0 Spartan and Spartan-XL FPGA Families Data Sheet DS060 (v2.0) March 1, 2013 0 0 Product Specification R Table 1: Spartan and Spartan-XL Field Programmable Gate Arrays Device Logic Cells Max System Gates Typical Gate Range (Logic and RAM)(1) CLB Matrix Total CLBs No. of Flip-flops Max. Avail. User I/O Total Distributed RAM Bits XCS05 and XCS05XL 238 5,000 2,000-5,000 10 x 10 100 360 77 3,200 XCS10 and XCS10XL 466 10,000 3,000-10,000 14 x 14 196 616 112 6,272 XCS20 and XCS20XL 950 20,000 7,000-20,000 20 x 20 400 1,120 160 12,800 XCS30 and XCS30XL 1368 30,000 10,000-30,000 24 x 24 576 1,536 192 18,432 XCS40 and XCS40XL 1862 40,000 13,000-40,000 28 x 28 784 2,016 205(2) 25,088 Notes: 1. Max values of Typical Gate Range include 20-30% of CLBs used as RAM. 2. XCS40XL provided 224 max I/O in CS280 package discontinued by PDN2004-01.DS060 (v2.0) March 1, 2013 www.xilinx.com 1 Product Specification © 1998-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Page 3

Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceGeneral Overview Spartan series FPGAs are implemented with a regular, flex- ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur- rounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter- connect patterns. The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi- ble an unlimited number of times. The values stored in these memory cells determine the logic functions and intercon- nections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode). Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month. Figure 1: Basic FPGA Block Diagram CLB B- SCAN CLB CLB CLB CLB CLB Routing Channels VersaRing Routing Channels CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB IOB IOB IOB IOB IO B IO B IO B IO B IO B IO B IO B IO B IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IO B IO B IO B IO B IO B IO B IO B IO B RDBK START -UP OSC DS060_01_0811002 www.xilinx.com DS060 (v2.0) March 1, 2013 Product Specification

Page 4

Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceSpartan and Spartan-XL devices provide system clock rates exceeding 80 MHz and internal performance in excess of 150 MHz. In addition to the conventional benefit of high volume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features. The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family’s features and benefits. Technology advancements have been derived from the XC4000XLA process developments. Logic Functional Description The Spartan series uses a standard FPGA structure as shown in Figure 1, page 2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels. • CLBs provide the functional elements for implementing the user’s logic. • IOBs provide the interface between the package pins and internal signal lines. • Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs. The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA. Configurable Logic Blocks (CLBs) The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli- fied block diagram in Figure 2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page 13. Function Generators Two 16 x 1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer- ing unrestricted logic implementation of any Boolean func- tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented. A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure 2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement cer- tain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbi- trarily defined Boolean function of five inputs.DS060 (v2.0) March 1, 2013 www.xilinx.com 3 Product Specification

Page 5

Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceA CLB can implement any of the following functions: • Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables Note: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB. • Any single function of five variables • Any function of four variables together with some functions of six variables • Some functions of up to nine variables. Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently. This flexibility improves cell usage. Flip-Flops Each CLB contains two flip-flops that can be used to regis- ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay. The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS, page 20. Latches (Spartan-XL Family Only) The Spartan-XL family CLB storage elements can also be configured as latches. The two latches have common clock (K) and clock enable (EC) inputs. Functionality of the stor- age element is described in Table 2. Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown) G4 G H1 F G4 G3G3 G2G2 G1 D YQ Y X SR CK EC Q G1 SR H1 DIN G H Logic Function of G1-G4 Logic Function of F-G-H1 Multiplexer Controlled by Configuration Program G-LUT F4F4 F3F3 F2F2 F1F1 K EC G Logic Function of F1-F4 F-LUT H-LUT A B D XQ SR CK EC Q DS060_02_0506 014 www.xilinx.com DS060 (v2.0) March 1, 2013 Product Specification

Page 6

Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under Obsolescence. Clock Input Each flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops. However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock Enable The clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left discon- nected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device. Set/Reset The set/reset line (SR) is an asynchronous active High con- trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB. CLB Signal Flow Control In addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y). Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source. Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT. Control Signals There are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig- nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals. Table 2: CLB Storage Element Functionality Mode CK EC SR D Q Power-Up or GSR X X X X SR Flip-Flop Operation X X 1 X SR 1* 0* D D 0 X 0* X Q Latch Operation (Spartan-XL) 1 1* 0* X Q 0 1* 0* D D Both X 0 0* X Q Legend: X Don’t care Rising edge (clock not inverted). SR Set or Reset value. Reset is default. 0* Input is Low or unconnected (default value) 1* Input is High or unconnected (default value) Figure 3: CLB Flip-Flop Functional Block Diagram Multiplexer Controlled by Configuration Program D QQD GND GSR Vcc CK EC SR SD RD DS060_03_041901DS060 (v2.0) March 1, 2013 www.xilinx.com 5 Product Specification

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Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceThe four internal control signals are: • EC: Enable Clock • SR: Asynchronous Set/Reset or H function generator Input 0 • DIN: Direct In or H function generator Input 2 • H1: H function generator Input 1. Input/Output Blocks (IOBs) User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con- figured for input, output, or bidirectional signals. Figure 6 shows a simplified functional block diagram of the Spar- tan/XL FPGA IOB. IOB Input Signal Path The input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3, and a simplified block diagram of the register can be seen in Figure 5. Figure 4: CLB Control Signal Interface Multiplexer Controlled by Configuration Program C1 DIN H1 SR EC C2 C3 C4 DS060_04_081100 Figure 5: IOB Flip-Flop/Latch Functional Block Diagram Table 3: Input Register Functionality Mode CK EC D Q Power-Up or GSR X X X SR Flip-Flop 1* D D 0 X X Q Latch 1 1* X Q 0 1* D D Both X 0 X Q Legend: X Don’t care. Rising edge (clock not inverted). SR Set or Reset value. Reset is default. 0* Input is Low or unconnected (default value) 1* Input is High or unconnected (default value) Multiplexer Controlled by Configuration Program D QQD GSR Vcc CK EC SD RD DS060_05_0419016 www.xilinx.com DS060 (v2.0) March 1, 2013 Product Specification

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Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceThe register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure 5 on the CK line. The Spartan family IOB data input path has a one-tap delay element: either the delay is inserted (default), or it is not. The Spartan-XL family IOB data input path has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Global Nets and Buffers, page 12 for a description of the global clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure 6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal. The 5V Spartan family input buffers can be globally config- ured for either TTL (1.2V) or CMOS (VCC/2) thresholds, using an option in the bitstream generation software. The Spartan family output levels are also configurable; the two global adjustments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan family inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL family inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table 4. Spartan-XL family I/Os are fully 5V tolerant even though the VCC is 3.3V. This allows 5V signals to directly connect to the Spartan-XL family inputs without damage, as shown in Table 4. In addition, the 3.3V VCC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems. Figure 6: Simplified Spartan/XL IOB Block Diagram Multiplexer Controlled by Configuration Program T O OK Q GTS D CK EC I1 I2 IK EC QD CK EC Delay Package Pad Programmable Pull-Up/ Pull-Down Network OUTPUT DRIVER Programmable Slew Rate Programmable TTL/CMOS Drive (Spartan only) INPUT BUFFER DS060_06_041901DS060 (v2.0) March 1, 2013 www.xilinx.com 7 Product Specification

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Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under Obsolescence Spartan-XL Family VCC Clamping Spartan-XL FPGAs have an optional clamping diode con- nected from each I/O to VCC. When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins. Spartan-XL devices are fully 5V TTL I/O compatible if VCC clamping is not enabled. With VCC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above VCC. If enabled, TTL I/O com- patibility is maintained but full 5V I/O tolerance is sacrificed. The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground. Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5. Additional Fast Capture Input Latch (Spartan-XL Family Only) The Spartan-XL family OB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements. This additional latch allows the fast capture of input data, which is then synchronized to the internal clock by the IOB flip-flop or latch. To place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans- parent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB. IOB Output Signal Path Output signals can be optionally inverted within the IOB, and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in Table 6. Table 4: Supported Sources for Spartan/XL Inputs Source Spartan Inputs Spartan-XL Inputs 5V, TTL 5V, CMOS 3.3V CMOS Any device, VCC = 3.3V, CMOS outputs √ Unreli- able Data √ Spartan family, VCC = 5V, TTL outputs √ √ Any device, VCC = 5V, TTL outputs (VOH ≤ 3.7V) √ √ Any device, VCC = 5V, CMOS outputs √ √ √ (default mode) Table 5: I/O Standards Supported by Spartan-XL FPGAs Signaling Standard VCC Clamping Output Drive VIH MAX VIH MIN VIL MAX VOH MIN VOL MAX TTL Not allowed 12/24 mA 5.5 2.0 0.8 2.4 0.4 LVTTL OK 12/24 mA 3.6 2.0 0.8 2.4 0.4 PCI5V Not allowed 24 mA 5.5 2.0 0.8 2.4 0.4 PCI3V Required 12 mA 3.6 50% of VCC 30% of VCC 90% of VCC 10% of VCC LVCMOS 3V OK 12/24 mA 3.6 50% of VCC 30% of VCC 90% of VCC 10% of VCC Table 6: Output Flip-Flop Functionality Mode Clock Clock Enable T D Q Power-Up or GSR X X 0* X SR Flip-Flop X 0 0* X Q 1* 0* D D X X 1 X Z 0 X 0* X Q Legend: X Don’t care Rising edge (clock not inverted). SR Set or Reset value. Reset is default. 0* Input is Low or unconnected (default value) 1* Input is High or unconnected (default value) Z 3-state8 www.xilinx.com DS060 (v2.0) March 1, 2013 Product Specification

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Spartan and Spartan-XL FPGA Families Data Sheet R Product Obsolete/Under ObsolescenceOutput Multiplexer/2-Input Function Generator (Spartan-XL Family Only) The output path in the Spartan-XL family IOB contains an additional multiplexer not available in the Spartan family IOB. The multiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs. When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effec- tively doubling the number of device outputs without requir- ing a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK. When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB func- tion generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin — the IOB input with the shortest delay to the function generator. Two examples are shown in Figure 7. Output Buffer An active High 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure 6, page 7). An output can be config- ured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground. By default, a 5V Spartan device output buffer pull-up struc- ture is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below VCC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to VCC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programma- ble. All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL family outputs are individually programmable for 12 mA or 24 mA output drive. Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Sup- ported destinations for Spartan/XL device outputs are shown in Table 7. Three-State Register (Spartan-XL Family Only) Spartan-XL devices incorporate an optional register control- ling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time. Output Slew Rate The slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop. Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter- mined by the individual configuration option for each IOB. Pull-up and Pull-down Network Programmable pull-up and pull-down resistors are used for tying unused pins to VCC or Ground to minimize power con- sumption and reduce noise sensitivity. The configurable pull-up resistor is a p-channel transistor that pulls to VCC. The configurable pull-down resistor is an n-channel transis- tor that pulls to Ground. The value of these resistors is typi- cally 20 KΩ − 100 KΩ (See "Spartan Family DC Characteristics Over Operating Conditions" on page 43.). Figure 7: AND and MUX Symbols in Spartan-XL IOB DS060_07_081100 OAND2 OMUX2 F D0 D1 O S0DS060 (v2.0) March 1, 2013 www.xilinx.com 9 Product Specification

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XCS10XL-4VQ100C Related Products

hotXCS10XL-4VQ100C XCS10-3VQG100C Xilinx Inc., IC FPGA 77 I/O 100VQFP, 100-TQFP, Spartan?-XL View
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hotXCS10XL-4VQ100C XCS10-3VQ100C Xilinx Inc., IC FPGA 77 I/O 100VQFP, 100-TQFP, Spartan?-XL View
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