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Part Number XCV400-4HQ240C
Manufacturer Xilinx Inc.
Description IC FPGA 166 I/O 240HQFP
Datasheet XCV400-4HQ240C Datasheet
Package 240-BFQFP Exposed Pad
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Part Number # XCV400-4HQ240C (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XCV400-4HQ240C Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XCV400-4HQ240CDatasheet
Package240-BFQFP Exposed Pad
Number of LABs/CLBs2400
Number of Logic Elements/Cells10800
Total RAM Bits81920
Number of I/O166
Number of Gates468252
Voltage - Supply2.375 V ~ 2.625 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case240-BFQFP Exposed Pad
Supplier Device Package240-PQFP (32x32)

XCV400-4HQ240C Datasheet

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Product Obsolete/Under ObsolescenceFeatures • Fast, high-density Field Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI • Multi-standard SelectIO™ interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices • Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets • Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs • Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode • Supported by FPGA Foundation™ and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms • SRAM-based in-system configuration - Unlimited re-programmability - Four programming modes • 0.22 μm 5-layer metal process • 100% factory tested Description The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 μm CMOS process. These advances make Virtex FPGAs powerful and flexible alterna- tives to mask-programmed gate arrays. The Virtex family comprises the nine members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. 0 Virtex™ 2.5 V Field Programmable Gate Arrays DS003-1 (v4.0) March 1, 2013 0 0 Product Specification R Table 1: Virtex Field Programmable Gate Array Family Members Device System Gates CLB Array Logic Cells Maximum Available I/O Block RAM Bits Maximum SelectRAM+™ Bits XCV50 57,906 16x24 1,728 180 32,768 24,576 XCV100 108,904 20x30 2,700 180 40,960 38,400 XCV150 164,674 24x36 3,888 260 49,152 55,296 XCV200 236,666 28x42 5,292 284 57,344 75,264 XCV300 322,970 32x48 6,912 316 65,536 98,304 XCV400 468,252 40x60 10,800 404 81,920 153,600 XCV600 661,111 48x72 15,552 512 98,304 221,184 XCV800 888,439 56x84 21,168 512 114,688 301,056 XCV1000 1,124,022 64x96 27,648 512 131,072 393,216© 2001-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-1 (v4.0) March 1, 2013 Module 1 of 4 Product Specification 1-800-255-7778 1

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceVirtex Architecture Virtex devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing resources. The abundance of routing resources permits the Virtex family to accommodate even the largest and most complex designs. Virtex FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. In some modes, the FPGA reads its own configuration data from an external PROM (master serial mode). Otherwise, the configuration data is written into the FPGA (Select- MAP™, slave serial, and JTAG modes). The standard Xilinx Foundation™ and Alliance Series™ Development systems deliver complete design support for Virtex, covering every aspect from behavioral and sche- matic entry, through simulation, automatic design transla- tion and implementation, to the creation, downloading, and readback of a configuration bit stream. Higher Performance Virtex devices provide better performance than previous generations of FPGA. Designs can achieve synchronous system clock rates up to 200 MHz including I/O. Virtex inputs and outputs comply fully with PCI specifications, and interfaces can be implemented that operate at 33 MHz or 66 MHz. Additionally, Virtex supports the hot-swapping requirements of Compact PCI. Xilinx thoroughly benchmarked the Virtex family. While per- formance is design-dependent, many designs operated internally at speeds in excess of 100 MHz and can achieve 200 MHz. Table 2 shows performance data for representa- tive circuits, using worst-case timing parameters. Table 2: Performance for Common Circuit Functions Function Bits Virtex -6 Register-to-Register Adder 16 64 5.0 ns 7.2 ns Pipelined Multiplier 8 x 8 16 x 16 5.1 ns 6.0 ns Address Decoder 16 64 4.4 ns 6.4 ns 16:1 Multiplexer 5.4 ns Parity Tree 9 18 36 4.1 ns 5.0 ns 6.9 ns Chip-to-Chip HSTL Class IV 200 MHz LVTTL,16mA, fast slew 180 MHzModule 1 of 4 DS003-1 (v4.0) March 1, 2013 2 1-800-255-7778 Product Specification

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceVirtex Device/Package Combinations and Maximum I/O Virtex Ordering Information Table 3: Virtex Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) Package XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 CS144 94 94 TQ144 98 98 PQ240 166 166 166 166 166 HQ240 166 166 166 BG256 180 180 180 180 BG352 260 260 260 BG432 316 316 316 316 BG560 404 404 404 404 FG256 176 176 176 176 FG456 260 284 312 FG676 404 444 444 FG680 512 512 512 Figure 1: Virtex Ordering Information XCV300 -6 PQ 240 CExample: Temperature Range C = Commercial (TJ = 0°C to +85°C) I = Industrial (TJ = –40°C to +100°C) Number of Pins Device Type Speed Grade -4 -5 -6 Package Type BG = Ball Grid Array FG = Fine-pitch Ball Grid Array PQ = Plastic Quad Flat Pack HQ = High Heat Dissipation QFP TQ = Thin Quad Flat Pack CS = Chip-scale PackageDS003-1 (v4.0) March 1, 2013 Module 1 of 4 Product Specification 1-800-255-7778 3

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceRevision History Virtex Data Sheet The Virtex Data Sheet contains the following modules: • DS003-1, Virtex 2.5V FPGAs: Introduction and Ordering Information (Module 1) • DS003-2, Virtex 2.5V FPGAs: Functional Description (Module 2) • DS003-3, Virtex 2.5V FPGAs: DC and Switching Characteristics (Module 3) • DS003-4, Virtex 2.5V FPGAs: Pinout Tables (Module 4) Date Version Revision 11/98 1.0 Initial Xilinx release. 01/99-02/99 1.2-1.3 Both versions updated package drawings and specs. 05/99 1.4 Addition of package drawings and specifications. 05/99 1.5 Replaced FG 676 & FG680 package drawings. 07/99 1.6 Changed Boundary Scan Information and changed Figure 11, Boundary Scan Bit Sequence. Updated IOB Input & Output delays. Added Capacitance info for different I/O Standards. Added 5 V tolerant information. Added DLL Parameters and waveforms and new Pin-to-pin Input and Output Parameter tables for Global Clock Input to Output and Setup and Hold. Changed Configuration Information including Figures 12, 14, 17 & 19. Added device-dependent listings for quiescent currents ICCINTQ and ICCOQ. Updated IOB Input and Output Delays based on default standard of LVTTL, 12 mA, Fast Slew Rate. Added IOB Input Switching Characteristics Standard Adjustments. 09/99 1.7 Speed grade update to preliminary status, Power-on specification and Clock-to-Out Minimums additions, “0” hold time listing explanation, quiescent current listing update, and Figure 6 ADDRA input label correction. Added TIJITCC parameter, changed TOJIT to TOPHASE. 01/00 1.8 Update to speed.txt file 1.96. Corrections for CRs 111036,111137, 112697, 115479, 117153, 117154, and 117612. Modified notes for Recommended Operating Conditions (voltage and temperature). Changed Bank information for VCCO in CS144 package on p.43. 01/00 1.9 Updated DLL Jitter Parameter table and waveforms, added Delay Measurement Methodology table for different I/O standards, changed buffered Hex line info and Input/Output Timing measurement notes. 03/00 2.0 New TBCKO values; corrected FG680 package connection drawing; new note about status of CCLK pin after configuration. 05/00 2.1 Modified “Pins not listed...” statement. Speed grade update to Final status. 05/00 2.2 Modified Table 18. 09/00 2.3 • Added XCV400 values to table under Minimum Clock-to-Out for Virtex Devices. • Corrected Units column in table under IOB Input Switching Characteristics. • Added values to table under CLB SelectRAM Switching Characteristics. 10/00 2.4 • Corrected Pinout information for devices in the BG256, BG432, and BG560 packages in Table 18. • Corrected BG256 Pin Function Diagram. 04/01 2.5 • Revised minimums for Global Clock Set-Up and Hold for LVTTL Standard, with DLL. • Converted file to modularized format. See Virtex Data Sheet section. 03/13 4.0 The products listed in this data sheet are obsolete. See XCN10016 for further information.Module 1 of 4 DS003-1 (v4.0) March 1, 2013 4 1-800-255-7778 Product Specification

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Product Obsolete/Under ObsolescenceArchitectural Description Virtex Array The Virtex user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic • IOBs provide the interface between the package pins and the CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlock™ that also provides local routing resources to connect the CLB to the GRM. The VersaRing™ I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex architecture also includes the following circuits that connect to the GRM. • Dedicated block memories of 4096 bits each • Clock DLLs for clock-distribution delay compensation and clock domain control • 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Input/Output Block The Virtex IOB, Figure 2, features SelectIO™ inputs and outputs that support a wide variety of I/O signalling stan- dards, see Table 1. The three IOB storage elements function either as edge-trig- gered D-type flip-flops or as level sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. In addition to the CLK and CE control signals, the three flip-flops share a Set/Reset (SR). For each flip-flop, this sig- nal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asyn- chronous Clear. The output buffer and all of the IOB control signals have independent polarity controls. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. Two forms of over-voltage protection are provided, one that per- mits 5 V compliance, and one that does not. For 5 V compli- ance, a Zener-like structure connected to ground turns on when the output rises to approximately 6.5 V. When PCI 3.3 V compliance is required, a conventional clamp diode is connected to the output supply voltage, VCCO. Optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each pad. Prior to con- figuration, all pins not involved in configuration are forced into their high-impedance state. The pull-down resistors and the weak-keeper circuits are inactive, but inputs can option- ally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins will float. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex IOBs support IEEE 1149.1-compatible boundary scan testing. 0 Virtex™ 2.5 V Field Programmable Gate Arrays DS003-2 (v4.0) March 1, 2013 0 0 Product Specification R Figure 1: Virtex Architecture Overview vao_b.eps IOBs IOBs IO B s IO B s DLL DLLDLL DLL VersaRing V e rs a R in g VersaRing V e rs a R in g CLBs B R A M s B R A M s © 1999-2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS003-2 (v4.0) March 1, 2013 Module 2 of 4 Product Specification 1-800-255-7778 1

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceFigure 2: Virtex Input/Output Block (IOB) OBUFT IBUF Vref ds022_02_091300 SR CLK ICE OCE O I IQ T TCE D CE Q SR D CE Q SR D CE Q SR PAD Programmable Delay Weak Keeper Table 1: Supported Select I/O Standards I/O Standard Input Reference Voltage (VREF) Output Source Voltage (VCCO) Board Termination Voltage (VTT) 5 V Tolerant LVTTL 2 – 24 mA N/A 3.3 N/A Yes LVCMOS2 N/A 2.5 N/A Yes PCI, 5 V N/A 3.3 N/A Yes PCI, 3.3 V N/A 3.3 N/A No GTL 0.8 N/A 1.2 No GTL+ 1.0 N/A 1.5 No HSTL Class I 0.75 1.5 0.75 No HSTL Class III 0.9 1.5 1.5 No HSTL Class IV 0.9 1.5 1.5 No SSTL3 Class I &II 1.5 3.3 1.5 No SSTL2 Class I & II 1.25 2.5 1.25 No CTT 1.5 3.3 1.5 No AGP 1.32 3.3 N/A NoModule 2 of 4 DS003-2 (v4.0) March 1, 2013 2 1-800-255-7778 Product Specification

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceInput Path A buffer In the Virtex IOB input path routes the input signal either directly to internal logic or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can used in close proximity to each other. See I/O Banking, page 3. There are optional pull-up and pull-down resistors at each user I/O input for use after configuration. Their value is in the range 50 kΩ – 100 kΩ. Output Path The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides syn- chronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See I/O Bank- ing, page 3. An optional weak-keeper circuit is connected to each out- put. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source sig- nal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Because the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The pro- vision of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages externally and con- nected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are auto- matically configured as inputs for the VREF voltage. Approx- imately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be con- nected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. Input buffers that use VREF are not 5 V tolerant. LVTTL, LVCMOS2, and PCI 33 MHz 5 V, are 5 V tolerant. The VCCO and VREF pins for each bank appear in the device Pinout tables and diagrams. The diagrams also show the bank affiliation of each I/O. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, Figure 3: Virtex I/O Banks Table 2: Compatible Output Standards VCCO Compatible Standards 3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+ 2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+ 1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+ X8778_b Bank 0 GCLK3 GCLK2 GCLK1 GCLK0 Bank 1 Bank 5 Bank 4 Virtex Device B a n k 7 B a n k 6 B a n k 2 B a n k 3DS003-2 (v4.0) March 1, 2013 Module 2 of 4 Product Specification 1-800-255-7778 3

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under Obsolescencemore I/O pins convert to VREF pins. Since these are always a superset of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. In TQ144 and PQ/HQ240 packages, all VCCO pins are bonded together internally, and consequently the same VCCO voltage must be connected to all of them. In the CS144 package, bank pairs that share a side are intercon- nected internally, permitting four choices for VCCO. In both cases, the VREF pins remain internally connected as eight banks, and can be used as described previously. Configurable Logic Block The basic building block of the Virtex CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Virtex function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be com- bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16x1-bit dual-port synchronous RAM. The Virtex LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. Storage Elements The storage elements in the Virtex slice can be configured either as edge-triggered D-type flip-flops or as level-sensi- tive latches. The D inputs can be driven either by the func- tion generators within the slice or directly from slice inputs, bypassing the function generators. In addition to Clock and Clock Enable signals, each Slice has synchronous set and reset signals (SR and BY). SR forces a storage element into the initialization state speci- fied for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to oper- ate asynchronously. All of the control signals are indepen- dently invertible, and are shared by the two flip-flops within the slice. Figure 4: 2-Slice Virtex CLB F1 F2 F3 F4 G1 G2 G3 G4 Carry & Control Carry & Control Carry & Control Carry & Control LUT CINCIN COUT COUT YQ XQXQ YQ X XB Y YBYB Y BX BY BX BY G1 G2 G3 G4 F1 F2 F3 F4 slice_c.eps Slice 1 Slice 0 XB X LUTLUT LUT D EC Q RC SP D EC Q RC SP D EC Q RC SP D EC Q RC SPModule 2 of 4 DS003-2 (v4.0) March 1, 2013 4 1-800-255-7778 Product Specification

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Virtex™ 2.5 V Field Programmable Gate Arrays R Product Obsolete/Under ObsolescenceAdditional Logic The F5 multiplexer in each slice combines the function gen- erator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected func- tions of up to 19 inputs. Each CLB has four direct feedthrough paths, one per LC. These paths provide extra data input lines or additional local routing that does not consume logic resources. Arithmetic Logic Dedicated carry logic provides fast arithmetic carry capabil- ity for high-speed arithmetic functions. The Virtex CLB sup- ports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB. The arithmetic logic includes an XOR gate that allows a 1-bit full adder to be implemented within an LC. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade func- tion generators for implementing wide logic functions. BUFTs Each Virtex CLB contains two 3-state drivers (BUFTs) that can drive on-chip busses. See Dedicated Routing, page 7. Each Virtex BUFT has an independent 3-state control pin and an independent input pin. Block SelectRAM Virtex FPGAs incorporate several large block SelectRAM memories. These complement the distributed LUT SelectRAMs that provide shallow RAM structures imple- mented in CLBs. Block SelectRAM memory blocks are organized in columns. All Virtex devices contain two such columns, one along each vertical edge. These columns extend the full height of the chip. Each memory block is four CLBs high, and conse- quently, a Virtex device 64 CLBs high contains 16 memory blocks per column, and a total of 32 blocks. Table 3 shows the amount of block SelectRAM memory that is available in each Virtex device. Figure 5: Detailed View of Virtex Slice BY F5IN SR CLK CE BX YB Y YQ XB X XQ G4 G3 G2 G1 F4 F3 F2 F1 CIN 0 1 1 0 F5 F5 viewslc4.eps COUT CY D EC Q D EC Q F6 CK WSO WSH WE A4 BY DG BX DI DI O WEI3 I2 I1 I0 LUT CY I3 I2 I1 I0 O DIWE LUT INIT INIT REV REV Table 3: Virtex Block SelectRAM Amounts Device # of Blocks Total Block SelectRAM Bits XCV50 8 32,768 XCV100 10 40,960 XCV150 12 49,152 XCV200 14 57,344 XCV300 16 65,536 XCV400 20 81,920 XCV600 24 98,304 XCV800 28 114,688 XCV1000 32 131,072DS003-2 (v4.0) March 1, 2013 Module 2 of 4 Product Specification 1-800-255-7778 5

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